RISC-V: Fix bugs of ternary integer and floating-point ternary intrinsics.
Commit Message
From: Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
Co-authored-by: kito-cheng <kito.cheng@sifive.com>
Co-authored-by: kito-cheng <kito.cheng@gmail.com>
This patch is fixing the bugs reported by @kito.
// vnmsub.vx vd, rs1, vs2, vm # vd[i] = -(x[rs1] * vd[i]) + vs2[i]
// vd = -(vb * a) + vc
// = -(3 * 1) + 10
// = 7
// GCC wrongly optmize this pattern to `3 - 10` due to we write wrong RTL
// pattern.
// vd = (3 * 1) - 10
// = 3 - 10
// = -7
// NOTE: GCC optimized (vb * a) - vc to vb - vc
Signed-off-by: Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
Co-authored-by: kito-cheng <kito.cheng@sifive.com>
Co-authored-by: kito-cheng <kito.cheng@gmail.com>
gcc/ChangeLog:
* config/riscv/vector.md: Correct ternary patterns.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/bug-3.c: New test.
* gcc.target/riscv/rvv/base/bug-4.c: New test.
* gcc.target/riscv/rvv/base/bug-5.c: New test.
---
gcc/config/riscv/vector.md | 80 +++++++++----------
.../gcc.target/riscv/rvv/base/bug-3.c | 22 +++++
.../gcc.target/riscv/rvv/base/bug-4.c | 22 +++++
.../gcc.target/riscv/rvv/base/bug-5.c | 22 +++++
4 files changed, 106 insertions(+), 40 deletions(-)
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/bug-3.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/bug-4.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/bug-5.c
Comments
IIRC the canonical form of (plus (op) (mult (op) (op))) is (plus
(mult (op) (op) (op)), so using the first form might not friendly for
the combine pass.
On Tue, Mar 14, 2023 at 10:24 AM <juzhe.zhong@rivai.ai> wrote:
>
> From: Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
>
> Co-authored-by: kito-cheng <kito.cheng@sifive.com>
> Co-authored-by: kito-cheng <kito.cheng@gmail.com>
>
> This patch is fixing the bugs reported by @kito.
>
> // vnmsub.vx vd, rs1, vs2, vm # vd[i] = -(x[rs1] * vd[i]) + vs2[i]
> // vd = -(vb * a) + vc
> // = -(3 * 1) + 10
> // = 7
> // GCC wrongly optmize this pattern to `3 - 10` due to we write wrong RTL
> // pattern.
> // vd = (3 * 1) - 10
> // = 3 - 10
> // = -7
> // NOTE: GCC optimized (vb * a) - vc to vb - vc
>
> Signed-off-by: Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
> Co-authored-by: kito-cheng <kito.cheng@sifive.com>
> Co-authored-by: kito-cheng <kito.cheng@gmail.com>
>
> gcc/ChangeLog:
>
> * config/riscv/vector.md: Correct ternary patterns.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/rvv/base/bug-3.c: New test.
> * gcc.target/riscv/rvv/base/bug-4.c: New test.
> * gcc.target/riscv/rvv/base/bug-5.c: New test.
>
> ---
> gcc/config/riscv/vector.md | 80 +++++++++----------
> .../gcc.target/riscv/rvv/base/bug-3.c | 22 +++++
> .../gcc.target/riscv/rvv/base/bug-4.c | 22 +++++
> .../gcc.target/riscv/rvv/base/bug-5.c | 22 +++++
> 4 files changed, 106 insertions(+), 40 deletions(-)
> create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/bug-3.c
> create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/bug-4.c
> create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/bug-5.c
>
> diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md
> index 5f765cdbacb..27c5cccb451 100644
> --- a/gcc/config/riscv/vector.md
> +++ b/gcc/config/riscv/vector.md
> @@ -4160,10 +4160,10 @@
> (reg:SI VL_REGNUM)
> (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
> (plus_minus:VI
> + (match_operand:VI 4 "register_operand")
> (mult:VI
> (match_operand:VI 2 "register_operand")
> - (match_operand:VI 3 "register_operand"))
> - (match_operand:VI 4 "register_operand"))
> + (match_operand:VI 3 "register_operand")))
> (match_operand:VI 5 "register_operand")))]
> "TARGET_VECTOR"
> {
> @@ -4185,10 +4185,10 @@
> (reg:SI VL_REGNUM)
> (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
> (plus_minus:VI
> + (match_operand:VI 4 "register_operand" " vr, vr, vr")
> (mult:VI
> (match_operand:VI 2 "register_operand" " 0, 0, vr")
> - (match_operand:VI 3 "register_operand" " vr, vr, vr"))
> - (match_operand:VI 4 "register_operand" " vr, vr, vr"))
> + (match_operand:VI 3 "register_operand" " vr, vr, vr")))
> (match_dup 2)))]
> "TARGET_VECTOR"
> "@
> @@ -4215,10 +4215,10 @@
> (reg:SI VL_REGNUM)
> (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
> (plus_minus:VI
> + (match_operand:VI 4 "register_operand" " 0, 0, vr")
> (mult:VI
> (match_operand:VI 2 "register_operand" " vr, vr, vr")
> - (match_operand:VI 3 "register_operand" " vr, vr, vr"))
> - (match_operand:VI 4 "register_operand" " 0, 0, vr"))
> + (match_operand:VI 3 "register_operand" " vr, vr, vr")))
> (match_dup 4)))]
> "TARGET_VECTOR"
> "@
> @@ -4245,10 +4245,10 @@
> (reg:SI VL_REGNUM)
> (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
> (plus_minus:VI
> + (match_operand:VI 4 "vector_arith_operand" " vr, vi, vr, vr, vr")
> (mult:VI
> (match_operand:VI 2 "register_operand" " vr, vr, vi, vr, vr")
> - (match_operand:VI 3 "register_operand" " vr, vr, vr, vi, vr"))
> - (match_operand:VI 4 "vector_arith_operand" " vr, vi, vr, vr, vr"))
> + (match_operand:VI 3 "register_operand" " vr, vr, vr, vi, vr")))
> (match_operand:VI 5 "register_operand" " 0, vr, vr, vr, vr")))]
> "TARGET_VECTOR
> && !rtx_equal_p (operands[2], operands[5])
> @@ -4296,11 +4296,11 @@
> (reg:SI VL_REGNUM)
> (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
> (plus_minus:VI_QHS
> + (match_operand:VI_QHS 4 "register_operand")
> (mult:VI_QHS
> (vec_duplicate:VI_QHS
> (match_operand:<VEL> 2 "reg_or_int_operand"))
> - (match_operand:VI_QHS 3 "register_operand"))
> - (match_operand:VI_QHS 4 "register_operand"))
> + (match_operand:VI_QHS 3 "register_operand")))
> (match_operand:VI_QHS 5 "register_operand")))]
> "TARGET_VECTOR"
> {
> @@ -4319,11 +4319,11 @@
> (reg:SI VL_REGNUM)
> (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
> (plus_minus:VI
> + (match_operand:VI 4 "register_operand" " vr, vr, vr")
> (mult:VI
> (vec_duplicate:VI
> (match_operand:<VEL> 2 "register_operand" " r, r, vr"))
> - (match_operand:VI 3 "register_operand" " 0, 0, vr"))
> - (match_operand:VI 4 "register_operand" " vr, vr, vr"))
> + (match_operand:VI 3 "register_operand" " 0, 0, vr")))
> (match_dup 3)))]
> "TARGET_VECTOR"
> "@
> @@ -4350,11 +4350,11 @@
> (reg:SI VL_REGNUM)
> (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
> (plus_minus:VI
> + (match_operand:VI 4 "register_operand" " 0, 0, vr")
> (mult:VI
> (vec_duplicate:VI
> (match_operand:<VEL> 2 "register_operand" " r, r, vr"))
> - (match_operand:VI 3 "register_operand" " vr, vr, vr"))
> - (match_operand:VI 4 "register_operand" " 0, 0, vr"))
> + (match_operand:VI 3 "register_operand" " vr, vr, vr")))
> (match_dup 4)))]
> "TARGET_VECTOR"
> "@
> @@ -4381,11 +4381,11 @@
> (reg:SI VL_REGNUM)
> (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
> (plus_minus:VI
> + (match_operand:VI 4 "vector_arith_operand" " vr, vi, vr, vr")
> (mult:VI
> (vec_duplicate:VI
> (match_operand:<VEL> 2 "register_operand" " r, r, r, r"))
> - (match_operand:VI 3 "register_operand" " vr, vr, vi, vr"))
> - (match_operand:VI 4 "vector_arith_operand" " vr, vi, vr, vr"))
> + (match_operand:VI 3 "register_operand" " vr, vr, vi, vr")))
> (match_operand:VI 5 "register_operand" " 0, vr, vr, vr")))]
> "TARGET_VECTOR
> && !rtx_equal_p (operands[3], operands[5])
> @@ -4428,11 +4428,11 @@
> (reg:SI VL_REGNUM)
> (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
> (plus_minus:VI_D
> + (match_operand:VI_D 4 "register_operand")
> (mult:VI_D
> (vec_duplicate:VI_D
> (match_operand:<VEL> 2 "reg_or_int_operand"))
> - (match_operand:VI_D 3 "register_operand"))
> - (match_operand:VI_D 4 "register_operand"))
> + (match_operand:VI_D 3 "register_operand")))
> (match_operand:VI_D 5 "register_operand")))]
> "TARGET_VECTOR"
> {
> @@ -4463,12 +4463,12 @@
> (reg:SI VL_REGNUM)
> (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
> (plus_minus:VI_D
> + (match_operand:VI_D 4 "register_operand" " vr, vr, vr")
> (mult:VI_D
> (vec_duplicate:VI_D
> (sign_extend:<VEL>
> (match_operand:<VSUBEL> 2 "register_operand" " r, r, vr")))
> - (match_operand:VI_D 3 "register_operand" " 0, 0, vr"))
> - (match_operand:VI_D 4 "register_operand" " vr, vr, vr"))
> + (match_operand:VI_D 3 "register_operand" " 0, 0, vr")))
> (match_dup 3)))]
> "TARGET_VECTOR"
> "@
> @@ -4495,12 +4495,12 @@
> (reg:SI VL_REGNUM)
> (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
> (plus_minus:VI_D
> + (match_operand:VI_D 4 "register_operand" " 0, 0, vr")
> (mult:VI_D
> (vec_duplicate:VI_D
> (sign_extend:<VEL>
> (match_operand:<VSUBEL> 2 "register_operand" " r, r, vr")))
> - (match_operand:VI_D 3 "register_operand" " vr, vr, vr"))
> - (match_operand:VI_D 4 "register_operand" " 0, 0, vr"))
> + (match_operand:VI_D 3 "register_operand" " vr, vr, vr")))
> (match_dup 4)))]
> "TARGET_VECTOR"
> "@
> @@ -4527,12 +4527,12 @@
> (reg:SI VL_REGNUM)
> (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
> (plus_minus:VI_D
> + (match_operand:VI_D 4 "vector_arith_operand" " vr, vr, vr, vr")
> (mult:VI_D
> (vec_duplicate:VI_D
> (sign_extend:<VEL>
> (match_operand:<VSUBEL> 2 "register_operand" " r, r, r, r")))
> - (match_operand:VI_D 3 "register_operand" " vr, vr, vr, vr"))
> - (match_operand:VI_D 4 "vector_arith_operand" " vr, vr, vr, vr"))
> + (match_operand:VI_D 3 "register_operand" " vr, vr, vr, vr")))
> (match_operand:VI_D 5 "register_operand" " 0, vr, vr, vr")))]
> "TARGET_VECTOR
> && !rtx_equal_p (operands[3], operands[5])
> @@ -5033,10 +5033,10 @@
> (reg:SI VL_REGNUM)
> (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
> (plus_minus:VF
> + (match_operand:VF 4 "register_operand")
> (mult:VF
> (match_operand:VF 2 "register_operand")
> - (match_operand:VF 3 "register_operand"))
> - (match_operand:VF 4 "register_operand"))
> + (match_operand:VF 3 "register_operand")))
> (match_operand:VF 5 "register_operand")))]
> "TARGET_VECTOR"
> {
> @@ -5058,10 +5058,10 @@
> (reg:SI VL_REGNUM)
> (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
> (plus_minus:VF
> + (match_operand:VF 4 "register_operand" " vr, vr, vr")
> (mult:VF
> (match_operand:VF 2 "register_operand" " 0, 0, vr")
> - (match_operand:VF 3 "register_operand" " vr, vr, vr"))
> - (match_operand:VF 4 "register_operand" " vr, vr, vr"))
> + (match_operand:VF 3 "register_operand" " vr, vr, vr")))
> (match_dup 2)))]
> "TARGET_VECTOR"
> "@
> @@ -5088,10 +5088,10 @@
> (reg:SI VL_REGNUM)
> (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
> (plus_minus:VF
> + (match_operand:VF 4 "register_operand" " 0, 0, vr")
> (mult:VF
> (match_operand:VF 2 "register_operand" " vr, vr, vr")
> - (match_operand:VF 3 "register_operand" " vr, vr, vr"))
> - (match_operand:VF 4 "register_operand" " 0, 0, vr"))
> + (match_operand:VF 3 "register_operand" " vr, vr, vr")))
> (match_dup 4)))]
> "TARGET_VECTOR"
> "@
> @@ -5118,10 +5118,10 @@
> (reg:SI VL_REGNUM)
> (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
> (plus_minus:VF
> + (match_operand:VF 4 "vector_arith_operand" " vr, vr")
> (mult:VF
> (match_operand:VF 2 "register_operand" " vr, vr")
> - (match_operand:VF 3 "register_operand" " vr, vr"))
> - (match_operand:VF 4 "vector_arith_operand" " vr, vr"))
> + (match_operand:VF 3 "register_operand" " vr, vr")))
> (match_operand:VF 5 "register_operand" " 0, vr")))]
> "TARGET_VECTOR
> && !rtx_equal_p (operands[2], operands[5])
> @@ -5153,11 +5153,11 @@
> (reg:SI VL_REGNUM)
> (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
> (plus_minus:VF
> + (match_operand:VF 4 "register_operand")
> (mult:VF
> (vec_duplicate:VF
> (match_operand:<VEL> 2 "register_operand"))
> - (match_operand:VF 3 "register_operand"))
> - (match_operand:VF 4 "register_operand"))
> + (match_operand:VF 3 "register_operand")))
> (match_operand:VF 5 "register_operand")))]
> "TARGET_VECTOR"
> {})
> @@ -5174,11 +5174,11 @@
> (reg:SI VL_REGNUM)
> (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
> (plus_minus:VF
> + (match_operand:VF 4 "register_operand" " vr, vr, vr")
> (mult:VF
> (vec_duplicate:VF
> (match_operand:<VEL> 2 "register_operand" " f, f, vr"))
> - (match_operand:VF 3 "register_operand" " 0, 0, vr"))
> - (match_operand:VF 4 "register_operand" " vr, vr, vr"))
> + (match_operand:VF 3 "register_operand" " 0, 0, vr")))
> (match_dup 3)))]
> "TARGET_VECTOR"
> "@
> @@ -5205,11 +5205,11 @@
> (reg:SI VL_REGNUM)
> (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
> (plus_minus:VF
> + (match_operand:VF 4 "register_operand" " 0, 0, vr")
> (mult:VF
> (vec_duplicate:VF
> (match_operand:<VEL> 2 "register_operand" " f, f, vr"))
> - (match_operand:VF 3 "register_operand" " vr, vr, vr"))
> - (match_operand:VF 4 "register_operand" " 0, 0, vr"))
> + (match_operand:VF 3 "register_operand" " vr, vr, vr")))
> (match_dup 4)))]
> "TARGET_VECTOR"
> "@
> @@ -5236,11 +5236,11 @@
> (reg:SI VL_REGNUM)
> (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
> (plus_minus:VF
> + (match_operand:VF 4 "vector_arith_operand" " vr, vr")
> (mult:VF
> (vec_duplicate:VF
> (match_operand:<VEL> 2 "register_operand" " f, f"))
> - (match_operand:VF 3 "register_operand" " vr, vr"))
> - (match_operand:VF 4 "vector_arith_operand" " vr, vr"))
> + (match_operand:VF 3 "register_operand" " vr, vr")))
> (match_operand:VF 5 "register_operand" " 0, vr")))]
> "TARGET_VECTOR
> && !rtx_equal_p (operands[3], operands[5])
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/bug-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/bug-3.c
> new file mode 100644
> index 00000000000..35b76892598
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/bug-3.c
> @@ -0,0 +1,22 @@
> +/* { dg-do run } */
> +/* { dg-options "-O2" } */
> +
> +#include "riscv_vector.h"
> +#include <stdio.h>
> +
> +int main()
> +{
> + int32_t a = 1;
> + int32_t b[1] = {3};
> + int32_t c[1] = {10};
> + int32_t d[1] = {0};
> + vint32m1_t vb = __riscv_vle32_v_i32m1 (b, 1);
> + vint32m1_t vc = __riscv_vle32_v_i32m1 (c, 1);
> + vint32m1_t vd = __riscv_vnmsub_vx_i32m1 (vb, a, vc, 1);
> + __riscv_vse32_v_i32m1 (d, vd, 1);
> + if (d[0] != 7){
> + printf("d[0] should be 7, but got %d\n", d[0]);
> + __builtin_abort ();
> + }
> + return 0;
> +}
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/bug-4.c b/gcc/testsuite/gcc.target/riscv/rvv/base/bug-4.c
> new file mode 100644
> index 00000000000..62dd3f50e44
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/bug-4.c
> @@ -0,0 +1,22 @@
> +/* { dg-do run } */
> +/* { dg-options "-O2" } */
> +
> +#include "riscv_vector.h"
> +#include <stdio.h>
> +
> +int main()
> +{
> + float a = 1.0;
> + float b[1] = {3.0};
> + float c[1] = {10.0};
> + float d[1] = {0.0};
> + vfloat32m1_t vb = __riscv_vle32_v_f32m1 (b, 1);
> + vfloat32m1_t vc = __riscv_vle32_v_f32m1 (c, 1);
> + vfloat32m1_t vd = __riscv_vfnmsub_vf_f32m1 (vb, a, vc, 1);
> + __riscv_vse32_v_f32m1 (d, vd, 1);
> + if (d[0] != 7.0){
> + printf("d[0] should be 7.0, but got %f\n", d[0]);
> + __builtin_abort ();
> + }
> + return 0;
> +}
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/bug-5.c b/gcc/testsuite/gcc.target/riscv/rvv/base/bug-5.c
> new file mode 100644
> index 00000000000..e43f85a0730
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/bug-5.c
> @@ -0,0 +1,22 @@
> +/* { dg-do run } */
> +/* { dg-options "-O2" } */
> +
> +#include "riscv_vector.h"
> +#include <stdio.h>
> +
> +int main()
> +{
> + float a = 1.0;
> + float b[1] = {3.0};
> + float c[1] = {10.0};
> + float d[1] = {0.0};
> + vfloat32m1_t vb = __riscv_vle32_v_f32m1 (b, 1);
> + vfloat32m1_t vc = __riscv_vle32_v_f32m1 (c, 1);
> + vfloat32m1_t vd = __riscv_vfmsub_vf_f32m1 (vb, a, vc, 1);
> + __riscv_vse32_v_f32m1 (d, vd, 1);
> + if (d[0] != -7.0){
> + printf("d[0] should be -7.0, but got %f\n", d[0]);
> + __builtin_abort ();
> + }
> + return 0;
> +}
> --
> 2.36.3
>
On 3/13/23 20:37, Kito Cheng via Gcc-patches wrote:
> IIRC the canonical form of (plus (op) (mult (op) (op))) is (plus
> (mult (op) (op) (op)), so using the first form might not friendly for
> the combine pass.
You're correct. The other form shouldn't be used at all and should not
appear in the MD files.
jeff
@@ -4160,10 +4160,10 @@
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
(plus_minus:VI
+ (match_operand:VI 4 "register_operand")
(mult:VI
(match_operand:VI 2 "register_operand")
- (match_operand:VI 3 "register_operand"))
- (match_operand:VI 4 "register_operand"))
+ (match_operand:VI 3 "register_operand")))
(match_operand:VI 5 "register_operand")))]
"TARGET_VECTOR"
{
@@ -4185,10 +4185,10 @@
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
(plus_minus:VI
+ (match_operand:VI 4 "register_operand" " vr, vr, vr")
(mult:VI
(match_operand:VI 2 "register_operand" " 0, 0, vr")
- (match_operand:VI 3 "register_operand" " vr, vr, vr"))
- (match_operand:VI 4 "register_operand" " vr, vr, vr"))
+ (match_operand:VI 3 "register_operand" " vr, vr, vr")))
(match_dup 2)))]
"TARGET_VECTOR"
"@
@@ -4215,10 +4215,10 @@
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
(plus_minus:VI
+ (match_operand:VI 4 "register_operand" " 0, 0, vr")
(mult:VI
(match_operand:VI 2 "register_operand" " vr, vr, vr")
- (match_operand:VI 3 "register_operand" " vr, vr, vr"))
- (match_operand:VI 4 "register_operand" " 0, 0, vr"))
+ (match_operand:VI 3 "register_operand" " vr, vr, vr")))
(match_dup 4)))]
"TARGET_VECTOR"
"@
@@ -4245,10 +4245,10 @@
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
(plus_minus:VI
+ (match_operand:VI 4 "vector_arith_operand" " vr, vi, vr, vr, vr")
(mult:VI
(match_operand:VI 2 "register_operand" " vr, vr, vi, vr, vr")
- (match_operand:VI 3 "register_operand" " vr, vr, vr, vi, vr"))
- (match_operand:VI 4 "vector_arith_operand" " vr, vi, vr, vr, vr"))
+ (match_operand:VI 3 "register_operand" " vr, vr, vr, vi, vr")))
(match_operand:VI 5 "register_operand" " 0, vr, vr, vr, vr")))]
"TARGET_VECTOR
&& !rtx_equal_p (operands[2], operands[5])
@@ -4296,11 +4296,11 @@
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
(plus_minus:VI_QHS
+ (match_operand:VI_QHS 4 "register_operand")
(mult:VI_QHS
(vec_duplicate:VI_QHS
(match_operand:<VEL> 2 "reg_or_int_operand"))
- (match_operand:VI_QHS 3 "register_operand"))
- (match_operand:VI_QHS 4 "register_operand"))
+ (match_operand:VI_QHS 3 "register_operand")))
(match_operand:VI_QHS 5 "register_operand")))]
"TARGET_VECTOR"
{
@@ -4319,11 +4319,11 @@
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
(plus_minus:VI
+ (match_operand:VI 4 "register_operand" " vr, vr, vr")
(mult:VI
(vec_duplicate:VI
(match_operand:<VEL> 2 "register_operand" " r, r, vr"))
- (match_operand:VI 3 "register_operand" " 0, 0, vr"))
- (match_operand:VI 4 "register_operand" " vr, vr, vr"))
+ (match_operand:VI 3 "register_operand" " 0, 0, vr")))
(match_dup 3)))]
"TARGET_VECTOR"
"@
@@ -4350,11 +4350,11 @@
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
(plus_minus:VI
+ (match_operand:VI 4 "register_operand" " 0, 0, vr")
(mult:VI
(vec_duplicate:VI
(match_operand:<VEL> 2 "register_operand" " r, r, vr"))
- (match_operand:VI 3 "register_operand" " vr, vr, vr"))
- (match_operand:VI 4 "register_operand" " 0, 0, vr"))
+ (match_operand:VI 3 "register_operand" " vr, vr, vr")))
(match_dup 4)))]
"TARGET_VECTOR"
"@
@@ -4381,11 +4381,11 @@
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
(plus_minus:VI
+ (match_operand:VI 4 "vector_arith_operand" " vr, vi, vr, vr")
(mult:VI
(vec_duplicate:VI
(match_operand:<VEL> 2 "register_operand" " r, r, r, r"))
- (match_operand:VI 3 "register_operand" " vr, vr, vi, vr"))
- (match_operand:VI 4 "vector_arith_operand" " vr, vi, vr, vr"))
+ (match_operand:VI 3 "register_operand" " vr, vr, vi, vr")))
(match_operand:VI 5 "register_operand" " 0, vr, vr, vr")))]
"TARGET_VECTOR
&& !rtx_equal_p (operands[3], operands[5])
@@ -4428,11 +4428,11 @@
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
(plus_minus:VI_D
+ (match_operand:VI_D 4 "register_operand")
(mult:VI_D
(vec_duplicate:VI_D
(match_operand:<VEL> 2 "reg_or_int_operand"))
- (match_operand:VI_D 3 "register_operand"))
- (match_operand:VI_D 4 "register_operand"))
+ (match_operand:VI_D 3 "register_operand")))
(match_operand:VI_D 5 "register_operand")))]
"TARGET_VECTOR"
{
@@ -4463,12 +4463,12 @@
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
(plus_minus:VI_D
+ (match_operand:VI_D 4 "register_operand" " vr, vr, vr")
(mult:VI_D
(vec_duplicate:VI_D
(sign_extend:<VEL>
(match_operand:<VSUBEL> 2 "register_operand" " r, r, vr")))
- (match_operand:VI_D 3 "register_operand" " 0, 0, vr"))
- (match_operand:VI_D 4 "register_operand" " vr, vr, vr"))
+ (match_operand:VI_D 3 "register_operand" " 0, 0, vr")))
(match_dup 3)))]
"TARGET_VECTOR"
"@
@@ -4495,12 +4495,12 @@
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
(plus_minus:VI_D
+ (match_operand:VI_D 4 "register_operand" " 0, 0, vr")
(mult:VI_D
(vec_duplicate:VI_D
(sign_extend:<VEL>
(match_operand:<VSUBEL> 2 "register_operand" " r, r, vr")))
- (match_operand:VI_D 3 "register_operand" " vr, vr, vr"))
- (match_operand:VI_D 4 "register_operand" " 0, 0, vr"))
+ (match_operand:VI_D 3 "register_operand" " vr, vr, vr")))
(match_dup 4)))]
"TARGET_VECTOR"
"@
@@ -4527,12 +4527,12 @@
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
(plus_minus:VI_D
+ (match_operand:VI_D 4 "vector_arith_operand" " vr, vr, vr, vr")
(mult:VI_D
(vec_duplicate:VI_D
(sign_extend:<VEL>
(match_operand:<VSUBEL> 2 "register_operand" " r, r, r, r")))
- (match_operand:VI_D 3 "register_operand" " vr, vr, vr, vr"))
- (match_operand:VI_D 4 "vector_arith_operand" " vr, vr, vr, vr"))
+ (match_operand:VI_D 3 "register_operand" " vr, vr, vr, vr")))
(match_operand:VI_D 5 "register_operand" " 0, vr, vr, vr")))]
"TARGET_VECTOR
&& !rtx_equal_p (operands[3], operands[5])
@@ -5033,10 +5033,10 @@
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
(plus_minus:VF
+ (match_operand:VF 4 "register_operand")
(mult:VF
(match_operand:VF 2 "register_operand")
- (match_operand:VF 3 "register_operand"))
- (match_operand:VF 4 "register_operand"))
+ (match_operand:VF 3 "register_operand")))
(match_operand:VF 5 "register_operand")))]
"TARGET_VECTOR"
{
@@ -5058,10 +5058,10 @@
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
(plus_minus:VF
+ (match_operand:VF 4 "register_operand" " vr, vr, vr")
(mult:VF
(match_operand:VF 2 "register_operand" " 0, 0, vr")
- (match_operand:VF 3 "register_operand" " vr, vr, vr"))
- (match_operand:VF 4 "register_operand" " vr, vr, vr"))
+ (match_operand:VF 3 "register_operand" " vr, vr, vr")))
(match_dup 2)))]
"TARGET_VECTOR"
"@
@@ -5088,10 +5088,10 @@
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
(plus_minus:VF
+ (match_operand:VF 4 "register_operand" " 0, 0, vr")
(mult:VF
(match_operand:VF 2 "register_operand" " vr, vr, vr")
- (match_operand:VF 3 "register_operand" " vr, vr, vr"))
- (match_operand:VF 4 "register_operand" " 0, 0, vr"))
+ (match_operand:VF 3 "register_operand" " vr, vr, vr")))
(match_dup 4)))]
"TARGET_VECTOR"
"@
@@ -5118,10 +5118,10 @@
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
(plus_minus:VF
+ (match_operand:VF 4 "vector_arith_operand" " vr, vr")
(mult:VF
(match_operand:VF 2 "register_operand" " vr, vr")
- (match_operand:VF 3 "register_operand" " vr, vr"))
- (match_operand:VF 4 "vector_arith_operand" " vr, vr"))
+ (match_operand:VF 3 "register_operand" " vr, vr")))
(match_operand:VF 5 "register_operand" " 0, vr")))]
"TARGET_VECTOR
&& !rtx_equal_p (operands[2], operands[5])
@@ -5153,11 +5153,11 @@
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
(plus_minus:VF
+ (match_operand:VF 4 "register_operand")
(mult:VF
(vec_duplicate:VF
(match_operand:<VEL> 2 "register_operand"))
- (match_operand:VF 3 "register_operand"))
- (match_operand:VF 4 "register_operand"))
+ (match_operand:VF 3 "register_operand")))
(match_operand:VF 5 "register_operand")))]
"TARGET_VECTOR"
{})
@@ -5174,11 +5174,11 @@
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
(plus_minus:VF
+ (match_operand:VF 4 "register_operand" " vr, vr, vr")
(mult:VF
(vec_duplicate:VF
(match_operand:<VEL> 2 "register_operand" " f, f, vr"))
- (match_operand:VF 3 "register_operand" " 0, 0, vr"))
- (match_operand:VF 4 "register_operand" " vr, vr, vr"))
+ (match_operand:VF 3 "register_operand" " 0, 0, vr")))
(match_dup 3)))]
"TARGET_VECTOR"
"@
@@ -5205,11 +5205,11 @@
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
(plus_minus:VF
+ (match_operand:VF 4 "register_operand" " 0, 0, vr")
(mult:VF
(vec_duplicate:VF
(match_operand:<VEL> 2 "register_operand" " f, f, vr"))
- (match_operand:VF 3 "register_operand" " vr, vr, vr"))
- (match_operand:VF 4 "register_operand" " 0, 0, vr"))
+ (match_operand:VF 3 "register_operand" " vr, vr, vr")))
(match_dup 4)))]
"TARGET_VECTOR"
"@
@@ -5236,11 +5236,11 @@
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
(plus_minus:VF
+ (match_operand:VF 4 "vector_arith_operand" " vr, vr")
(mult:VF
(vec_duplicate:VF
(match_operand:<VEL> 2 "register_operand" " f, f"))
- (match_operand:VF 3 "register_operand" " vr, vr"))
- (match_operand:VF 4 "vector_arith_operand" " vr, vr"))
+ (match_operand:VF 3 "register_operand" " vr, vr")))
(match_operand:VF 5 "register_operand" " 0, vr")))]
"TARGET_VECTOR
&& !rtx_equal_p (operands[3], operands[5])
new file mode 100644
@@ -0,0 +1,22 @@
+/* { dg-do run } */
+/* { dg-options "-O2" } */
+
+#include "riscv_vector.h"
+#include <stdio.h>
+
+int main()
+{
+ int32_t a = 1;
+ int32_t b[1] = {3};
+ int32_t c[1] = {10};
+ int32_t d[1] = {0};
+ vint32m1_t vb = __riscv_vle32_v_i32m1 (b, 1);
+ vint32m1_t vc = __riscv_vle32_v_i32m1 (c, 1);
+ vint32m1_t vd = __riscv_vnmsub_vx_i32m1 (vb, a, vc, 1);
+ __riscv_vse32_v_i32m1 (d, vd, 1);
+ if (d[0] != 7){
+ printf("d[0] should be 7, but got %d\n", d[0]);
+ __builtin_abort ();
+ }
+ return 0;
+}
new file mode 100644
@@ -0,0 +1,22 @@
+/* { dg-do run } */
+/* { dg-options "-O2" } */
+
+#include "riscv_vector.h"
+#include <stdio.h>
+
+int main()
+{
+ float a = 1.0;
+ float b[1] = {3.0};
+ float c[1] = {10.0};
+ float d[1] = {0.0};
+ vfloat32m1_t vb = __riscv_vle32_v_f32m1 (b, 1);
+ vfloat32m1_t vc = __riscv_vle32_v_f32m1 (c, 1);
+ vfloat32m1_t vd = __riscv_vfnmsub_vf_f32m1 (vb, a, vc, 1);
+ __riscv_vse32_v_f32m1 (d, vd, 1);
+ if (d[0] != 7.0){
+ printf("d[0] should be 7.0, but got %f\n", d[0]);
+ __builtin_abort ();
+ }
+ return 0;
+}
new file mode 100644
@@ -0,0 +1,22 @@
+/* { dg-do run } */
+/* { dg-options "-O2" } */
+
+#include "riscv_vector.h"
+#include <stdio.h>
+
+int main()
+{
+ float a = 1.0;
+ float b[1] = {3.0};
+ float c[1] = {10.0};
+ float d[1] = {0.0};
+ vfloat32m1_t vb = __riscv_vle32_v_f32m1 (b, 1);
+ vfloat32m1_t vc = __riscv_vle32_v_f32m1 (c, 1);
+ vfloat32m1_t vd = __riscv_vfmsub_vf_f32m1 (vb, a, vc, 1);
+ __riscv_vse32_v_f32m1 (d, vd, 1);
+ if (d[0] != -7.0){
+ printf("d[0] should be -7.0, but got %f\n", d[0]);
+ __builtin_abort ();
+ }
+ return 0;
+}