[V2] RISC-V: Add fault first load C/C++ support

Message ID 20230308222146.102045-1-juzhe.zhong@rivai.ai
State Superseded
Headers
Series [V2] RISC-V: Add fault first load C/C++ support |

Commit Message

juzhe.zhong@rivai.ai March 8, 2023, 10:21 p.m. UTC
  From: Ju-Zhe Zhong <juzhe.zhong@rivai.ai>

gcc/ChangeLog:

        * config/riscv/riscv-vector-builtins-bases.cc: Remove magic number.

---
 gcc/config/riscv/riscv-vector-builtins-bases.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)
  

Patch

diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc b/gcc/config/riscv/riscv-vector-builtins-bases.cc
index 9f87f8c645a..3f0f809c714 100644
--- a/gcc/config/riscv/riscv-vector-builtins-bases.cc
+++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc
@@ -1617,7 +1617,7 @@  public:
        ====> vleff (const *base, size_t vl)
 	     new_vl = MEM_REF[read_vl ()].  */
 
-    auto_vec<tree, 8> vargs;
+    auto_vec<tree> vargs (gimple_call_num_args (f.call) - 1);
 
     for (unsigned i = 0; i < gimple_call_num_args (f.call); i++)
       {