From patchwork Wed Mar 8 03:27:37 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Collison X-Patchwork-Id: 66103 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 84046384B830 for ; Wed, 8 Mar 2023 03:28:06 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mail-qt1-x82e.google.com (mail-qt1-x82e.google.com [IPv6:2607:f8b0:4864:20::82e]) by sourceware.org (Postfix) with ESMTPS id 14A4D38582A3 for ; Wed, 8 Mar 2023 03:27:46 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 14A4D38582A3 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivosinc.com Received: by mail-qt1-x82e.google.com with SMTP id l13so16941216qtv.3 for ; Tue, 07 Mar 2023 19:27:46 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20210112.gappssmtp.com; s=20210112; t=1678246065; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=SADA01ucAQKrQ34c4/KrlbiUf8z7ta7yLCKyE6RlIBw=; b=PI4J9xzbhkvItTxR5F1664zdytz8BLoXUTX+p2eurEBt5Od7T7RwJzVmYHbrr0NZZs yRFA1fzD/uiNChkgp6LSoyzXA2Jv5Oh8PTnTAkZDKMQESpvbo2ydz16kjeyEQKzJp+xY Em1HNxSCu0Oe1e+gcfLj0yu6vBeeACO4WFXdLq0DF3/xjj8BlLQfeq4kxURjsqab/KCW yj1UzDLc5XIh5ZhHvnwloK4JGICt61hCLAeCOS9p1TRZRo1dzxW4O2X9E4DlNNJpgNju XTowf0OzpQBlON6vYp1hC3wH7AD8AWEb2rGm0KP9k27Q/7olwai/F3ZHsVweCcentbaD UTyg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1678246065; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=SADA01ucAQKrQ34c4/KrlbiUf8z7ta7yLCKyE6RlIBw=; b=BrBvjBnibgNOW+9mtJne2NOY8f86DKGPv1d/XCuRAJ465B0F5bU1jN20NJTvWNsluU iNc1PuADz9nEbYzTDXp0H8/21++RCnAi1WcxLfaecTuLXONYk5kEqWmdIbs5d4p5qI8X HDZTrSY7hPwZ7AzpP/bNhO63pijxa7ejxDrPtJxnowl7QyRD+OIgOcsXJWWRHnhYzQiM yaVf3thqzPe+zLg+M1rA/tEi7uRQgbUTFgbHrB0evwfrjb3jy6tv48eVV8yLobtMc4u2 Gnq/1AFbo49e8ESNA0h0iy5Vj01wi8XLNKx0uxEk/A2bjVa1q+CkixmHctkcxzCFhJQm iYnQ== X-Gm-Message-State: AO0yUKWp9qvBPoIc47loISRiDXsGfVSAy4l7kkoH1QO7M7RcDJfdFCgW /G+HIVBdxUFRzSZhHcF2scfC0Jwl7vFcvUpVHf8= X-Google-Smtp-Source: AK7set+Jh+ZM19Pdpde7b6NAN3/4TfuGyeONvR0oNm5Y+NnExl5cmqJxRZrzq1LMAWi2kRVYOg2NJw== X-Received: by 2002:ac8:594f:0:b0:3b8:68ef:d538 with SMTP id 15-20020ac8594f000000b003b868efd538mr2085403qtz.52.1678246065235; Tue, 07 Mar 2023 19:27:45 -0800 (PST) Received: from system76-pc.ba.rivosinc.com ([136.57.172.92]) by smtp.gmail.com with ESMTPSA id v21-20020ac87295000000b003b6382f66b1sm10759696qto.29.2023.03.07.19.27.44 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 07 Mar 2023 19:27:44 -0800 (PST) From: Michael Collison To: gcc-patches@gcc.gnu.org Subject: [PATCH v3 3/6] RISC-V: autovec: Add auto-vectorization support functions Date: Tue, 7 Mar 2023 22:27:37 -0500 Message-Id: <20230308032740.989275-4-collison@rivosinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230308032740.989275-1-collison@rivosinc.com> References: <20230308032740.989275-1-collison@rivosinc.com> MIME-Version: 1.0 X-Spam-Status: No, score=-12.4 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" 2023-03-02 Michael Collison Juzhe Zhong * config/riscv/riscv-v.cc (riscv_classify_vlmul_field): New function. (riscv_vector_preferred_simd_mode): Ditto. (get_mask_policy_no_pred): Ditto. (get_tail_policy_no_pred): Ditto. (riscv_tuple_mode_p): Ditto. (riscv_classify_nf): Ditto. (riscv_vlmul_regsize): Ditto. (riscv_vector_mask_mode_p): Ditto. (riscv_vector_get_mask_mode): Ditto. --- gcc/config/riscv/riscv-v.cc | 176 ++++++++++++++++++++++++++++++++++++ 1 file changed, 176 insertions(+) diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc index 2d2de6e4a6c..d21bde1bda6 100644 --- a/gcc/config/riscv/riscv-v.cc +++ b/gcc/config/riscv/riscv-v.cc @@ -39,9 +39,11 @@ #include "emit-rtl.h" #include "tm_p.h" #include "target.h" +#include "targhooks.h" #include "expr.h" #include "optabs.h" #include "tm-constrs.h" +#include "riscv-vector-builtins.h" #include "rtx-vector-builder.h" using namespace riscv_vector; @@ -109,6 +111,41 @@ const_vec_all_same_in_range_p (rtx x, HOST_WIDE_INT minval, && IN_RANGE (INTVAL (elt), minval, maxval)); } +/* Return the vlmul field for a specific machine mode. */ +unsigned int +riscv_classify_vlmul_field (enum machine_mode mode) +{ + /* Make the decision based on the mode's enum value rather than its + properties, so that we keep the correct classification regardless + of -mriscv-vector-bits. */ + switch (mode) + { + case E_VNx8BImode: + return VLMUL_FIELD_111; + + case E_VNx4BImode: + return VLMUL_FIELD_110; + + case E_VNx2BImode: + return VLMUL_FIELD_101; + + case E_VNx16BImode: + return VLMUL_FIELD_000; + + case E_VNx32BImode: + return VLMUL_FIELD_001; + + case E_VNx64BImode: + return VLMUL_FIELD_010; + + default: + break; + } + + /* we don't care about VLMUL for Mask. */ + return VLMUL_FIELD_000; +} + rtx emit_vlmax_vsetvl (machine_mode vmode) { @@ -163,6 +200,64 @@ calculate_ratio (unsigned int sew, enum vlmul_type vlmul) return ratio; } +/* Implement TARGET_VECTORIZE_PREFERRED_SIMD_MODE for RVV. */ + +machine_mode +riscv_vector_preferred_simd_mode (scalar_mode mode, unsigned vf) +{ + if (!TARGET_VECTOR) + return word_mode; + + switch (mode) + { + case E_QImode: + return vf == 1 ? VNx8QImode + : vf == 2 ? VNx16QImode + : vf == 4 ? VNx32QImode + : VNx64QImode; + break; + case E_HImode: + return vf == 1 ? VNx4HImode + : vf == 2 ? VNx8HImode + : vf == 4 ? VNx16HImode + : VNx32HImode; + break; + case E_SImode: + return vf == 1 ? VNx2SImode + : vf == 2 ? VNx4SImode + : vf == 4 ? VNx8SImode + : VNx16SImode; + break; + case E_DImode: + if (riscv_vector_elen_flags != MASK_VECTOR_ELEN_32 + && riscv_vector_elen_flags != MASK_VECTOR_ELEN_FP_32) + return vf == 1 ? VNx1DImode + : vf == 2 ? VNx2DImode + : vf == 4 ? VNx4DImode + : VNx8DImode; + break; + case E_SFmode: + if (TARGET_HARD_FLOAT && riscv_vector_elen_flags != MASK_VECTOR_ELEN_32 + && riscv_vector_elen_flags != MASK_VECTOR_ELEN_64) + return vf == 1 ? VNx2SFmode + : vf == 2 ? VNx4SFmode + : vf == 4 ? VNx8SFmode + : VNx16SFmode; + break; + case E_DFmode: + if (TARGET_DOUBLE_FLOAT && TARGET_VECTOR_ELEN_FP_64) + return vf == 1 ? VNx1DFmode + : vf == 2 ? VNx2DFmode + : vf == 4 ? VNx4DFmode + : VNx8DFmode; + break; + default: + break; + } + + return word_mode; +} + /* Emit an RVV unmask && vl mov from SRC to DEST. */ static void emit_pred_op (unsigned icode, rtx mask, rtx dest, rtx src, rtx len, @@ -375,6 +470,87 @@ get_avl_type_rtx (enum avl_type type) return gen_int_mode (type, Pmode); } +rtx +get_mask_policy_no_pred () +{ + return get_mask_policy_for_pred (PRED_TYPE_none); +} + +rtx +get_tail_policy_no_pred () +{ + return get_mask_policy_for_pred (PRED_TYPE_none); +} + +/* Return true if it is a RVV tuple mode. */ +bool +riscv_tuple_mode_p (machine_mode mode ATTRIBUTE_UNUSED) +{ + return false; +} + +/* Return nf for a machine mode. */ +int +riscv_classify_nf (machine_mode mode) +{ + switch (mode) + { + + default: + break; + } + + return 1; +} + +/* Return vlmul register size for a machine mode. */ +int +riscv_vlmul_regsize (machine_mode mode) +{ + if (GET_MODE_CLASS (mode) == MODE_VECTOR_BOOL) + return 1; + switch (riscv_classify_vlmul_field (mode)) + { + case VLMUL_FIELD_001: + return 2; + case VLMUL_FIELD_010: + return 4; + case VLMUL_FIELD_011: + return 8; + case VLMUL_FIELD_100: + gcc_unreachable (); + default: + return 1; + } +} + +/* Return true if it is a RVV mask mode. */ +bool +riscv_vector_mask_mode_p (machine_mode mode) +{ + return (mode == VNx1BImode || mode == VNx2BImode || mode == VNx4BImode + || mode == VNx8BImode || mode == VNx16BImode || mode == VNx32BImode + || mode == VNx64BImode); +} + +/* Implement TARGET_VECTORIZE_GET_MASK_MODE for RVV. */ + +opt_machine_mode +riscv_vector_get_mask_mode (machine_mode mode) +{ + machine_mode mask_mode; + int nf = 1; + if (riscv_tuple_mode_p (mode)) + nf = riscv_classify_nf (mode); + + FOR_EACH_MODE_IN_CLASS (mask_mode, MODE_VECTOR_BOOL) + if (GET_MODE_INNER (mask_mode) == BImode + && known_eq (GET_MODE_NUNITS (mask_mode) * nf, GET_MODE_NUNITS (mode)) + && riscv_vector_mask_mode_p (mask_mode)) + return mask_mode; + return default_get_mask_mode (mode); +} + /* Return the RVV vector mode that has NUNITS elements of mode INNER_MODE. This function is not only used by builtins, but also will be used by auto-vectorization in the future. */