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[62.178.148.172]) by smtp.gmail.com with ESMTPSA id p17-20020a170906229100b008e68d2c11d8sm6853872eja.218.2023.03.02.00.35.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 02 Mar 2023 00:35:43 -0800 (PST) From: Christoph Muellner To: gcc-patches@gcc.gnu.org, Kito Cheng , Jim Wilson , Palmer Dabbelt , Andrew Waterman , Philipp Tomsich , Cooper Qu , Lifang Xia , Yunhai Shang , Zhiwei Liu , Andrew Pinski , Hans-Peter Nilsson Cc: =?utf-8?q?Christoph_M=C3=BCllner?= Subject: [PATCH v4 4/9] riscv: thead: Add support for the XTheadBs ISA extension Date: Thu, 2 Mar 2023 09:35:29 +0100 Message-Id: <20230302083534.4076244-5-christoph.muellner@vrull.eu> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230302083534.4076244-1-christoph.muellner@vrull.eu> References: <20230302083534.4076244-1-christoph.muellner@vrull.eu> MIME-Version: 1.0 X-Spam-Status: No, score=-12.7 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, JMQ_SPF_NEUTRAL, KAM_MANYTO, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" From: Christoph Müllner This patch adds support for the XTheadBs ISA extension. The new INSN pattern is defined in a new file to separate this vendor extension from the standard extensions. The cost model adjustment reuses the xbs:bext cost. gcc/ChangeLog: * config/riscv/riscv.cc (riscv_rtx_costs): Add xthead:tst cost. * config/riscv/thead.md (*th_tst3): New INSN. gcc/testsuite/ChangeLog: * gcc.target/riscv/xtheadbs-tst.c: New test. Changes in v4: - Replace 'immediate_operand' by 'const_int_operand' - Add number of arguments to pattern name - Add range check Signed-off-by: Christoph Müllner --- gcc/config/riscv/riscv.cc | 4 ++-- gcc/config/riscv/thead.md | 11 +++++++++++ gcc/testsuite/gcc.target/riscv/xtheadbs-tst.c | 13 +++++++++++++ 3 files changed, 26 insertions(+), 2 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadbs-tst.c diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index f11b7949a49..e35bc0a745b 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -2400,8 +2400,8 @@ riscv_rtx_costs (rtx x, machine_mode mode, int outer_code, int opno ATTRIBUTE_UN *total = COSTS_N_INSNS (SINGLE_SHIFT_COST); return true; } - /* bext pattern for zbs. */ - if (TARGET_ZBS && outer_code == SET + /* bit extraction pattern (zbs:bext, xtheadbs:tst). */ + if ((TARGET_ZBS || TARGET_XTHEADBS) && outer_code == SET && GET_CODE (XEXP (x, 1)) == CONST_INT && INTVAL (XEXP (x, 1)) == 1) { diff --git a/gcc/config/riscv/thead.md b/gcc/config/riscv/thead.md index 2da5aaee94f..3842a194d16 100644 --- a/gcc/config/riscv/thead.md +++ b/gcc/config/riscv/thead.md @@ -29,3 +29,14 @@ (define_insn "*th_addsl4" "th.addsl\t%0,%3,%1,%2" [(set_attr "type" "bitmanip") (set_attr "mode" "")]) + +;; XTheadBs + +(define_insn "*th_tst3" + [(set (match_operand:X 0 "register_operand" "=r") + (zero_extract:X (match_operand:X 1 "register_operand" "r") + (const_int 1) + (match_operand 2 "const_int_operand" "n")))] + "TARGET_XTHEADBS && UINTVAL (operands[2]) < GET_MODE_BITSIZE (mode)" + "th.tst\t%0,%1,%2" + [(set_attr "type" "bitmanip")]) diff --git a/gcc/testsuite/gcc.target/riscv/xtheadbs-tst.c b/gcc/testsuite/gcc.target/riscv/xtheadbs-tst.c new file mode 100644 index 00000000000..674cec09128 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/xtheadbs-tst.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc_xtheadbs" { target { rv32 } } } */ +/* { dg-options "-march=rv64gc_xtheadbs" { target { rv64 } } } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +long +foo1 (long i) +{ + return 1L & (i >> 20); +} + +/* { dg-final { scan-assembler-times "th.tst\t" 1 } } */ +/* { dg-final { scan-assembler-not "andi" } } */