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[62.178.148.172]) by smtp.gmail.com with ESMTPSA id p17-20020a170906229100b008e68d2c11d8sm6853872eja.218.2023.03.02.00.35.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 02 Mar 2023 00:35:38 -0800 (PST) From: Christoph Muellner To: gcc-patches@gcc.gnu.org, Kito Cheng , Jim Wilson , Palmer Dabbelt , Andrew Waterman , Philipp Tomsich , Cooper Qu , Lifang Xia , Yunhai Shang , Zhiwei Liu , Andrew Pinski , Hans-Peter Nilsson Cc: =?utf-8?q?Christoph_M=C3=BCllner?= Subject: [PATCH v4 1/9] riscv: Add basic XThead* vendor extension support Date: Thu, 2 Mar 2023 09:35:26 +0100 Message-Id: <20230302083534.4076244-2-christoph.muellner@vrull.eu> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230302083534.4076244-1-christoph.muellner@vrull.eu> References: <20230302083534.4076244-1-christoph.muellner@vrull.eu> MIME-Version: 1.0 X-Spam-Status: No, score=-12.7 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, JMQ_SPF_NEUTRAL, KAM_MANYTO, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" From: Christoph Müllner This patch add basic support for the following XThead* ISA extensions: * XTheadBa * XTheadBb * XTheadBs * XTheadCmo * XTheadCondMov * XTheadFMemIdx * XTheadFmv * XTheadInt * XTheadMac * XTheadMemIdx * XTheadMemPair * XTheadSync The extensions are just recognized by the compiler and feature test macros are generated (which this patch also brings tests for). gcc/ChangeLog: * common/config/riscv/riscv-common.cc: Add xthead* extensions. * config/riscv/riscv-opts.h (MASK_XTHEADBA): New. (MASK_XTHEADBB): New. (MASK_XTHEADBS): New. (MASK_XTHEADCMO): New. (MASK_XTHEADCONDMOV): New. (MASK_XTHEADFMEMIDX): New. (MASK_XTHEADFMV): New. (MASK_XTHEADINT): New. (MASK_XTHEADMAC): New. (MASK_XTHEADMEMIDX): New. (MASK_XTHEADMEMPAIR): New. (MASK_XTHEADSYNC): New. (TARGET_XTHEADBA): New. (TARGET_XTHEADBB): New. (TARGET_XTHEADBS): New. (TARGET_XTHEADCMO): New. (TARGET_XTHEADCONDMOV): New. (TARGET_XTHEADFMEMIDX): New. (TARGET_XTHEADFMV): New. (TARGET_XTHEADINT): New. (TARGET_XTHEADMAC): New. (TARGET_XTHEADMEMIDX): New. (TARGET_XTHEADMEMPAIR): new. (TARGET_XTHEADSYNC): New. * config/riscv/riscv.opt: Add riscv_xthead_subext. gcc/testsuite/ChangeLog: * gcc.target/riscv/xtheadba.c: New test. * gcc.target/riscv/xtheadbb.c: New test. * gcc.target/riscv/xtheadbs.c: New test. * gcc.target/riscv/xtheadcmo.c: New test. * gcc.target/riscv/xtheadcondmov.c: New test. * gcc.target/riscv/xtheadfmemidx.c: New test. * gcc.target/riscv/xtheadfmv.c: New test. * gcc.target/riscv/xtheadint.c: New test. * gcc.target/riscv/xtheadmac.c: New test. * gcc.target/riscv/xtheadmemidx.c: New test. * gcc.target/riscv/xtheadmempair.c: New test. * gcc.target/riscv/xtheadsync.c: New test. Signed-off-by: Christoph Müllner --- gcc/common/config/riscv/riscv-common.cc | 26 +++++++++++++++++++ gcc/config/riscv/riscv-opts.h | 26 +++++++++++++++++++ gcc/config/riscv/riscv.opt | 3 +++ gcc/testsuite/gcc.target/riscv/xtheadba.c | 14 ++++++++++ gcc/testsuite/gcc.target/riscv/xtheadbb.c | 14 ++++++++++ gcc/testsuite/gcc.target/riscv/xtheadbs.c | 14 ++++++++++ gcc/testsuite/gcc.target/riscv/xtheadcmo.c | 14 ++++++++++ .../gcc.target/riscv/xtheadcondmov.c | 14 ++++++++++ .../gcc.target/riscv/xtheadfmemidx.c | 14 ++++++++++ gcc/testsuite/gcc.target/riscv/xtheadfmv.c | 14 ++++++++++ gcc/testsuite/gcc.target/riscv/xtheadint.c | 14 ++++++++++ gcc/testsuite/gcc.target/riscv/xtheadmac.c | 14 ++++++++++ gcc/testsuite/gcc.target/riscv/xtheadmemidx.c | 14 ++++++++++ .../gcc.target/riscv/xtheadmempair.c | 13 ++++++++++ gcc/testsuite/gcc.target/riscv/xtheadsync.c | 14 ++++++++++ 15 files changed, 222 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadba.c create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadbb.c create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadbs.c create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadcmo.c create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadcondmov.c create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadfmemidx.c create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadfmv.c create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadint.c create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadmac.c create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadmemidx.c create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadmempair.c create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadsync.c diff --git a/gcc/common/config/riscv/riscv-common.cc b/gcc/common/config/riscv/riscv-common.cc index ebc1ed7d7e4..ef221be1eb1 100644 --- a/gcc/common/config/riscv/riscv-common.cc +++ b/gcc/common/config/riscv/riscv-common.cc @@ -222,6 +222,19 @@ static const struct riscv_ext_version riscv_ext_version_table[] = {"svinval", ISA_SPEC_CLASS_NONE, 1, 0}, {"svnapot", ISA_SPEC_CLASS_NONE, 1, 0}, + {"xtheadba", ISA_SPEC_CLASS_NONE, 1, 0}, + {"xtheadbb", ISA_SPEC_CLASS_NONE, 1, 0}, + {"xtheadbs", ISA_SPEC_CLASS_NONE, 1, 0}, + {"xtheadcmo", ISA_SPEC_CLASS_NONE, 1, 0}, + {"xtheadcondmov", ISA_SPEC_CLASS_NONE, 1, 0}, + {"xtheadfmemidx", ISA_SPEC_CLASS_NONE, 1, 0}, + {"xtheadfmv", ISA_SPEC_CLASS_NONE, 1, 0}, + {"xtheadint", ISA_SPEC_CLASS_NONE, 1, 0}, + {"xtheadmac", ISA_SPEC_CLASS_NONE, 1, 0}, + {"xtheadmemidx", ISA_SPEC_CLASS_NONE, 1, 0}, + {"xtheadmempair", ISA_SPEC_CLASS_NONE, 1, 0}, + {"xtheadsync", ISA_SPEC_CLASS_NONE, 1, 0}, + /* Terminate the list. */ {NULL, ISA_SPEC_CLASS_NONE, 0, 0} }; @@ -1248,6 +1261,19 @@ static const riscv_ext_flag_table_t riscv_ext_flag_table[] = {"svinval", &gcc_options::x_riscv_sv_subext, MASK_SVINVAL}, {"svnapot", &gcc_options::x_riscv_sv_subext, MASK_SVNAPOT}, + {"xtheadba", &gcc_options::x_riscv_xthead_subext, MASK_XTHEADBA}, + {"xtheadbb", &gcc_options::x_riscv_xthead_subext, MASK_XTHEADBB}, + {"xtheadbs", &gcc_options::x_riscv_xthead_subext, MASK_XTHEADBS}, + {"xtheadcmo", &gcc_options::x_riscv_xthead_subext, MASK_XTHEADCMO}, + {"xtheadcondmov", &gcc_options::x_riscv_xthead_subext, MASK_XTHEADCONDMOV}, + {"xtheadfmemidx", &gcc_options::x_riscv_xthead_subext, MASK_XTHEADFMEMIDX}, + {"xtheadfmv", &gcc_options::x_riscv_xthead_subext, MASK_XTHEADFMV}, + {"xtheadint", &gcc_options::x_riscv_xthead_subext, MASK_XTHEADINT}, + {"xtheadmac", &gcc_options::x_riscv_xthead_subext, MASK_XTHEADMAC}, + {"xtheadmemidx", &gcc_options::x_riscv_xthead_subext, MASK_XTHEADMEMIDX}, + {"xtheadmempair", &gcc_options::x_riscv_xthead_subext, MASK_XTHEADMEMPAIR}, + {"xtheadsync", &gcc_options::x_riscv_xthead_subext, MASK_XTHEADSYNC}, + {NULL, NULL, 0} }; diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h index ff398c0a2ae..cf0cd669be4 100644 --- a/gcc/config/riscv/riscv-opts.h +++ b/gcc/config/riscv/riscv-opts.h @@ -189,4 +189,30 @@ enum stack_protector_guard { ? 0 \ : 32 << (__builtin_popcount (riscv_zvl_flags) - 1)) +#define MASK_XTHEADBA (1 << 0) +#define MASK_XTHEADBB (1 << 1) +#define MASK_XTHEADBS (1 << 2) +#define MASK_XTHEADCMO (1 << 3) +#define MASK_XTHEADCONDMOV (1 << 4) +#define MASK_XTHEADFMEMIDX (1 << 5) +#define MASK_XTHEADFMV (1 << 6) +#define MASK_XTHEADINT (1 << 7) +#define MASK_XTHEADMAC (1 << 8) +#define MASK_XTHEADMEMIDX (1 << 9) +#define MASK_XTHEADMEMPAIR (1 << 10) +#define MASK_XTHEADSYNC (1 << 11) + +#define TARGET_XTHEADBA ((riscv_xthead_subext & MASK_XTHEADBA) != 0) +#define TARGET_XTHEADBB ((riscv_xthead_subext & MASK_XTHEADBB) != 0) +#define TARGET_XTHEADBS ((riscv_xthead_subext & MASK_XTHEADBS) != 0) +#define TARGET_XTHEADCMO ((riscv_xthead_subext & MASK_XTHEADCMO) != 0) +#define TARGET_XTHEADCONDMOV ((riscv_xthead_subext & MASK_XTHEADCONDMOV) != 0) +#define TARGET_XTHEADFMEMIDX ((riscv_xthead_subext & MASK_XTHEADFMEMIDX) != 0) +#define TARGET_XTHEADFMV ((riscv_xthead_subext & MASK_XTHEADFMV) != 0) +#define TARGET_XTHEADINT ((riscv_xthead_subext & MASK_XTHEADINT) != 0) +#define TARGET_XTHEADMAC ((riscv_xthead_subext & MASK_XTHEADMAC) != 0) +#define TARGET_XTHEADMEMIDX ((riscv_xthead_subext & MASK_XTHEADMEMIDX) != 0) +#define TARGET_XTHEADMEMPAIR ((riscv_xthead_subext & MASK_XTHEADMEMPAIR) != 0) +#define TARGET_XTHEADSYNC ((riscv_xthead_subext & MASK_XTHEADSYNC) != 0) + #endif /* ! GCC_RISCV_OPTS_H */ diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt index 95535235354..ff1dd4ddd4f 100644 --- a/gcc/config/riscv/riscv.opt +++ b/gcc/config/riscv/riscv.opt @@ -235,6 +235,9 @@ int riscv_zm_subext TargetVariable int riscv_sv_subext +TargetVariable +int riscv_xthead_subext + Enum Name(isa_spec_class) Type(enum riscv_isa_spec_class) Supported ISA specs (for use with the -misa-spec= option): diff --git a/gcc/testsuite/gcc.target/riscv/xtheadba.c b/gcc/testsuite/gcc.target/riscv/xtheadba.c new file mode 100644 index 00000000000..14cdb1ffe2e --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/xtheadba.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc_xtheadba" { target { rv32 } } } */ +/* { dg-options "-march=rv64gc_xtheadba" { target { rv64 } } } */ + +#ifndef __riscv_xtheadba +#error Feature macro not defined +#endif + +int +foo (int a) +{ + return a; +} + diff --git a/gcc/testsuite/gcc.target/riscv/xtheadbb.c b/gcc/testsuite/gcc.target/riscv/xtheadbb.c new file mode 100644 index 00000000000..66988abf221 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/xtheadbb.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc_xtheadbb" { target { rv32 } } } */ +/* { dg-options "-march=rv64gc_xtheadbb" { target { rv64 } } } */ + +#ifndef __riscv_xtheadbb +#error Feature macro not defined +#endif + +int +foo (int a) +{ + return a; +} + diff --git a/gcc/testsuite/gcc.target/riscv/xtheadbs.c b/gcc/testsuite/gcc.target/riscv/xtheadbs.c new file mode 100644 index 00000000000..808d7378a7b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/xtheadbs.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc_xtheadbs" { target { rv32 } } } */ +/* { dg-options "-march=rv64gc_xtheadbs" { target { rv64 } } } */ + +#ifndef __riscv_xtheadbs +#error Feature macro not defined +#endif + +int +foo (int a) +{ + return a; +} + diff --git a/gcc/testsuite/gcc.target/riscv/xtheadcmo.c b/gcc/testsuite/gcc.target/riscv/xtheadcmo.c new file mode 100644 index 00000000000..eab8fef421c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/xtheadcmo.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc_xtheadcmo" { target { rv32 } } } */ +/* { dg-options "-march=rv64gc_xtheadcmo" { target { rv64 } } } */ + +#ifndef __riscv_xtheadcmo +#error Feature macro not defined +#endif + +int +foo (int a) +{ + return a; +} + diff --git a/gcc/testsuite/gcc.target/riscv/xtheadcondmov.c b/gcc/testsuite/gcc.target/riscv/xtheadcondmov.c new file mode 100644 index 00000000000..a239c3f9f46 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/xtheadcondmov.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc_xtheadcondmov" { target { rv32 } } } */ +/* { dg-options "-march=rv64gc_xtheadcondmov" { target { rv64 } } } */ + +#ifndef __riscv_xtheadcondmov +#error Feature macro not defined +#endif + +int +foo (int a) +{ + return a; +} + diff --git a/gcc/testsuite/gcc.target/riscv/xtheadfmemidx.c b/gcc/testsuite/gcc.target/riscv/xtheadfmemidx.c new file mode 100644 index 00000000000..e450c5e5c5a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/xtheadfmemidx.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc_xtheadfmemidx" { target { rv32 } } } */ +/* { dg-options "-march=rv64gc_xtheadfmemidx" { target { rv64 } } } */ + +#ifndef __riscv_xtheadfmemidx +#error Feature macro not defined +#endif + +int +foo (int a) +{ + return a; +} + diff --git a/gcc/testsuite/gcc.target/riscv/xtheadfmv.c b/gcc/testsuite/gcc.target/riscv/xtheadfmv.c new file mode 100644 index 00000000000..e97e8f461f6 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/xtheadfmv.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc_xtheadfmv" { target { rv32 } } } */ +/* { dg-options "-march=rv64gc_xtheadfmv" { target { rv64 } } } */ + +#ifndef __riscv_xtheadfmv +#error Feature macro not defined +#endif + +int +foo (int a) +{ + return a; +} + diff --git a/gcc/testsuite/gcc.target/riscv/xtheadint.c b/gcc/testsuite/gcc.target/riscv/xtheadint.c new file mode 100644 index 00000000000..ee6989a380e --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/xtheadint.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc_xtheadint" { target { rv32 } } } */ +/* { dg-options "-march=rv64gc_xtheadint" { target { rv64 } } } */ + +#ifndef __riscv_xtheadint +#error Feature macro not defined +#endif + +int +foo (int a) +{ + return a; +} + diff --git a/gcc/testsuite/gcc.target/riscv/xtheadmac.c b/gcc/testsuite/gcc.target/riscv/xtheadmac.c new file mode 100644 index 00000000000..7c635407b31 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/xtheadmac.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc_xtheadmac" { target { rv32 } } } */ +/* { dg-options "-march=rv64gc_xtheadmac" { target { rv64 } } } */ + +#ifndef __riscv_xtheadmac +#error Feature macro not defined +#endif + +int +foo (int a) +{ + return a; +} + diff --git a/gcc/testsuite/gcc.target/riscv/xtheadmemidx.c b/gcc/testsuite/gcc.target/riscv/xtheadmemidx.c new file mode 100644 index 00000000000..076eab00f54 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/xtheadmemidx.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc_xtheadmemidx" { target { rv32 } } } */ +/* { dg-options "-march=rv64gc_xtheadmemidx" { target { rv64 } } } */ + +#ifndef __riscv_xtheadmemidx +#error Feature macro not defined +#endif + +int +foo (int a) +{ + return a; +} + diff --git a/gcc/testsuite/gcc.target/riscv/xtheadmempair.c b/gcc/testsuite/gcc.target/riscv/xtheadmempair.c new file mode 100644 index 00000000000..5135d2175dc --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/xtheadmempair.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc_xtheadmempair" { target { rv32 } } } */ +/* { dg-options "-march=rv64gc_xtheadmempair" { target { rv64 } } } */ + +#ifndef __riscv_xtheadmempair +#error Feature macro not defined +#endif + +int +foo (int a) +{ + return a; +} diff --git a/gcc/testsuite/gcc.target/riscv/xtheadsync.c b/gcc/testsuite/gcc.target/riscv/xtheadsync.c new file mode 100644 index 00000000000..835d60c96e9 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/xtheadsync.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc_xtheadsync" { target { rv32 } } } */ +/* { dg-options "-march=rv64gc_xtheadsync" { target { rv64 } } } */ + +#ifndef __riscv_xtheadsync +#error Feature macro not defined +#endif + +int +foo (int a) +{ + return a; +} +