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[62.178.148.172]) by smtp.gmail.com with ESMTPSA id f18-20020adffcd2000000b002c59e001631sm11704055wrs.77.2023.02.23.21.51.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 23 Feb 2023 21:51:35 -0800 (PST) From: Christoph Muellner To: gcc-patches@gcc.gnu.org, Kito Cheng , Jim Wilson , Palmer Dabbelt , Andrew Waterman , Philipp Tomsich , Jeff Law , Cooper Qu , Lifang Xia , Yunhai Shang , Zhiwei Liu Cc: =?utf-8?q?Christoph_M=C3=BCllner?= Subject: [PATCH v3 03/11] riscv: thead: Add support for the XTheadBa ISA extension Date: Fri, 24 Feb 2023 06:51:19 +0100 Message-Id: <20230224055127.2500953-4-christoph.muellner@vrull.eu> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230224055127.2500953-1-christoph.muellner@vrull.eu> References: <20230224055127.2500953-1-christoph.muellner@vrull.eu> MIME-Version: 1.0 X-Spam-Status: No, score=-12.8 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, JMQ_SPF_NEUTRAL, KAM_MANYTO, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" From: Christoph Müllner This patch adds support for the XTheadBa ISA extension. The new INSN pattern is defined in a new file to separate this vendor extension from the standard extensions. gcc/ChangeLog: * config/riscv/riscv.md: Include thead.md * config/riscv/thead.md: New file. gcc/testsuite/ChangeLog: * gcc.target/riscv/xtheadba-addsl.c: New test. Changes in v3: - Fix operand order for th.addsl. Signed-off-by: Christoph Müllner --- gcc/config/riscv/riscv.md | 1 + gcc/config/riscv/thead.md | 31 +++++++++++ .../gcc.target/riscv/xtheadba-addsl.c | 55 +++++++++++++++++++ 3 files changed, 87 insertions(+) create mode 100644 gcc/config/riscv/thead.md create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadba-addsl.c diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md index 05924e9bbf1..d6c2265e9d4 100644 --- a/gcc/config/riscv/riscv.md +++ b/gcc/config/riscv/riscv.md @@ -3093,4 +3093,5 @@ (define_insn "riscv_prefetchi_" (include "pic.md") (include "generic.md") (include "sifive-7.md") +(include "thead.md") (include "vector.md") diff --git a/gcc/config/riscv/thead.md b/gcc/config/riscv/thead.md new file mode 100644 index 00000000000..158e9124c3a --- /dev/null +++ b/gcc/config/riscv/thead.md @@ -0,0 +1,31 @@ +;; Machine description for T-Head vendor extensions +;; Copyright (C) 2021-2022 Free Software Foundation, Inc. + +;; This file is part of GCC. + +;; GCC is free software; you can redistribute it and/or modify +;; it under the terms of the GNU General Public License as published by +;; the Free Software Foundation; either version 3, or (at your option) +;; any later version. + +;; GCC is distributed in the hope that it will be useful, +;; but WITHOUT ANY WARRANTY; without even the implied warranty of +;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +;; GNU General Public License for more details. + +;; You should have received a copy of the GNU General Public License +;; along with GCC; see the file COPYING3. If not see +;; . + +;; XTheadBa + +(define_insn "*th_addsl" + [(set (match_operand:X 0 "register_operand" "=r") + (plus:X (ashift:X (match_operand:X 1 "register_operand" "r") + (match_operand:QI 2 "immediate_operand" "I")) + (match_operand:X 3 "register_operand" "r")))] + "TARGET_XTHEADBA + && (INTVAL (operands[2]) >= 0) && (INTVAL (operands[2]) <= 3)" + "th.addsl\t%0,%3,%1,%2" + [(set_attr "type" "bitmanip") + (set_attr "mode" "")]) diff --git a/gcc/testsuite/gcc.target/riscv/xtheadba-addsl.c b/gcc/testsuite/gcc.target/riscv/xtheadba-addsl.c new file mode 100644 index 00000000000..5004735a246 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/xtheadba-addsl.c @@ -0,0 +1,55 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc_xtheadba" { target { rv32 } } } */ +/* { dg-options "-march=rv64gc_xtheadba" { target { rv64 } } } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +long +test_1 (long a, long b) +{ + /* th.addsl aX, aX, 1 */ + return a + (b << 1); +} + +int +foos (short *x, int n) +{ + /* th.addsl aX, aX, 1 */ + return x[n]; +} + +long +test_2 (long a, long b) +{ + /* th.addsl aX, aX, 2 */ + return a + (b << 2); +} + +int +fooi (int *x, int n) +{ + /* th.addsl aX, aX, 2 */ + return x[n]; +} + +long +test_3 (long a, long b) +{ + /* th.addsl aX, aX, 3 */ + return a + (b << 3); +} + +long +fool (long *x, int n) +{ + /* th.addsl aX, aX, 2 (rv32) */ + /* th.addsl aX, aX, 3 (rv64) */ + return x[n]; +} + +/* { dg-final { scan-assembler-times "th.addsl\[ \t\]*a\[0-9\]+,a\[0-9\]+,a\[0-9\]+,1" 2 } } */ + +/* { dg-final { scan-assembler-times "th.addsl\[ \t\]*a\[0-9\]+,a\[0-9\]+,a\[0-9\]+,2" 3 { target { rv32 } } } } */ +/* { dg-final { scan-assembler-times "th.addsl\[ \t\]*a\[0-9\]+,a\[0-9\]+,a\[0-9\]+,2" 2 { target { rv64 } } } } */ + +/* { dg-final { scan-assembler-times "th.addsl\[ \t\]*a\[0-9\]+,a\[0-9\]+,a\[0-9\]+,3" 1 { target { rv32 } } } } */ +/* { dg-final { scan-assembler-times "th.addsl\[ \t\]*a\[0-9\]+,a\[0-9\]+,a\[0-9\]+,3" 2 { target { rv64 } } } } */