[v3,03/11] riscv: thead: Add support for the XTheadBa ISA extension

  From: Christoph Müllner <christoph.muellner@vrull.eu>

This patch adds support for the XTheadBa ISA extension.
The new INSN pattern is defined in a new file to separate
this vendor extension from the standard extensions.

gcc/ChangeLog:

	* config/riscv/riscv.md: Include thead.md
	* config/riscv/thead.md: New file.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/xtheadba-addsl.c: New test.

Changes in v3:
- Fix operand order for th.addsl.

Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
---
 gcc/config/riscv/riscv.md                     |  1 +
 gcc/config/riscv/thead.md                     | 31 +++++++++++
 .../gcc.target/riscv/xtheadba-addsl.c         | 55 +++++++++++++++++++
 3 files changed, 87 insertions(+)
 create mode 100644 gcc/config/riscv/thead.md
 create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadba-addsl.c
  

On Thu, Feb 23, 2023 at 9:55 PM Christoph Muellner
<christoph.muellner@vrull.eu> wrote:
>
> From: Christoph Müllner <christoph.muellner@vrull.eu>
>
> This patch adds support for the XTheadBa ISA extension.
> The new INSN pattern is defined in a new file to separate
> this vendor extension from the standard extensions.

How does this interact with doing -march=rv32gc_xtheadba_zba ?
Seems like it might be better handle that case correctly. I suspect
these all XThreadB* extensions have a similar problem too.

Thanks,
Andrew Pinski

>
> gcc/ChangeLog:
>
>         * config/riscv/riscv.md: Include thead.md
>         * config/riscv/thead.md: New file.
>
> gcc/testsuite/ChangeLog:
>
>         * gcc.target/riscv/xtheadba-addsl.c: New test.
>
> Changes in v3:
> - Fix operand order for th.addsl.
>
> Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
> ---
>  gcc/config/riscv/riscv.md                     |  1 +
>  gcc/config/riscv/thead.md                     | 31 +++++++++++
>  .../gcc.target/riscv/xtheadba-addsl.c         | 55 +++++++++++++++++++
>  3 files changed, 87 insertions(+)
>  create mode 100644 gcc/config/riscv/thead.md
>  create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadba-addsl.c
>
> diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
> index 05924e9bbf1..d6c2265e9d4 100644
> --- a/gcc/config/riscv/riscv.md
> +++ b/gcc/config/riscv/riscv.md
> @@ -3093,4 +3093,5 @@ (define_insn "riscv_prefetchi_<mode>"
>  (include "pic.md")
>  (include "generic.md")
>  (include "sifive-7.md")
> +(include "thead.md")
>  (include "vector.md")
> diff --git a/gcc/config/riscv/thead.md b/gcc/config/riscv/thead.md
> new file mode 100644
> index 00000000000..158e9124c3a
> --- /dev/null
> +++ b/gcc/config/riscv/thead.md
> @@ -0,0 +1,31 @@
> +;; Machine description for T-Head vendor extensions
> +;; Copyright (C) 2021-2022 Free Software Foundation, Inc.
> +
> +;; This file is part of GCC.
> +
> +;; GCC is free software; you can redistribute it and/or modify
> +;; it under the terms of the GNU General Public License as published by
> +;; the Free Software Foundation; either version 3, or (at your option)
> +;; any later version.
> +
> +;; GCC is distributed in the hope that it will be useful,
> +;; but WITHOUT ANY WARRANTY; without even the implied warranty of
> +;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> +;; GNU General Public License for more details.
> +
> +;; You should have received a copy of the GNU General Public License
> +;; along with GCC; see the file COPYING3.  If not see
> +;; <http://www.gnu.org/licenses/>.
> +
> +;; XTheadBa
> +
> +(define_insn "*th_addsl"
> +  [(set (match_operand:X 0 "register_operand" "=r")
> +       (plus:X (ashift:X (match_operand:X 1 "register_operand" "r")
> +                         (match_operand:QI 2 "immediate_operand" "I"))
> +               (match_operand:X 3 "register_operand" "r")))]
> +  "TARGET_XTHEADBA
> +   && (INTVAL (operands[2]) >= 0) && (INTVAL (operands[2]) <= 3)"
> +  "th.addsl\t%0,%3,%1,%2"
> +  [(set_attr "type" "bitmanip")
> +   (set_attr "mode" "<X:MODE>")])
> diff --git a/gcc/testsuite/gcc.target/riscv/xtheadba-addsl.c b/gcc/testsuite/gcc.target/riscv/xtheadba-addsl.c
> new file mode 100644
> index 00000000000..5004735a246
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/xtheadba-addsl.c
> @@ -0,0 +1,55 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32gc_xtheadba" { target { rv32 } } } */
> +/* { dg-options "-march=rv64gc_xtheadba" { target { rv64 } } } */
> +/* { dg-skip-if "" { *-*-* } { "-O0" } } */
> +
> +long
> +test_1 (long a, long b)
> +{
> +  /* th.addsl aX, aX, 1  */
> +  return a + (b << 1);
> +}
> +
> +int
> +foos (short *x, int n)
> +{
> +  /* th.addsl aX, aX, 1  */
> +  return x[n];
> +}
> +
> +long
> +test_2 (long a, long b)
> +{
> +  /* th.addsl aX, aX, 2  */
> +  return a + (b << 2);
> +}
> +
> +int
> +fooi (int *x, int n)
> +{
> +  /* th.addsl aX, aX, 2  */
> +  return x[n];
> +}
> +
> +long
> +test_3 (long a, long b)
> +{
> +  /* th.addsl aX, aX, 3  */
> +  return a + (b << 3);
> +}
> +
> +long
> +fool (long *x, int n)
> +{
> +  /* th.addsl aX, aX, 2 (rv32)  */
> +  /* th.addsl aX, aX, 3 (rv64)  */
> +  return x[n];
> +}
> +
> +/* { dg-final { scan-assembler-times "th.addsl\[ \t\]*a\[0-9\]+,a\[0-9\]+,a\[0-9\]+,1" 2 } } */
> +
> +/* { dg-final { scan-assembler-times "th.addsl\[ \t\]*a\[0-9\]+,a\[0-9\]+,a\[0-9\]+,2" 3 { target { rv32 } } } } */
> +/* { dg-final { scan-assembler-times "th.addsl\[ \t\]*a\[0-9\]+,a\[0-9\]+,a\[0-9\]+,2" 2 { target { rv64 } } } } */
> +
> +/* { dg-final { scan-assembler-times "th.addsl\[ \t\]*a\[0-9\]+,a\[0-9\]+,a\[0-9\]+,3" 1 { target { rv32 } } } } */
> +/* { dg-final { scan-assembler-times "th.addsl\[ \t\]*a\[0-9\]+,a\[0-9\]+,a\[0-9\]+,3" 2 { target { rv64 } } } } */
> --
> 2.39.2
>
  

My impression is that md patterns will use first-match patterns? so
the zba will get higher priority than xtheadba if both patterns are
matched?

On Fri, Feb 24, 2023 at 2:52 PM Andrew Pinski via Gcc-patches
<gcc-patches@gcc.gnu.org> wrote:
>
> On Thu, Feb 23, 2023 at 9:55 PM Christoph Muellner
> <christoph.muellner@vrull.eu> wrote:
> >
> > From: Christoph Müllner <christoph.muellner@vrull.eu>
> >
> > This patch adds support for the XTheadBa ISA extension.
> > The new INSN pattern is defined in a new file to separate
> > this vendor extension from the standard extensions.
>
> How does this interact with doing -march=rv32gc_xtheadba_zba ?
> Seems like it might be better handle that case correctly. I suspect
> these all XThreadB* extensions have a similar problem too.
>
> Thanks,
> Andrew Pinski
>
> >
> > gcc/ChangeLog:
> >
> >         * config/riscv/riscv.md: Include thead.md
> >         * config/riscv/thead.md: New file.
> >
> > gcc/testsuite/ChangeLog:
> >
> >         * gcc.target/riscv/xtheadba-addsl.c: New test.
> >
> > Changes in v3:
> > - Fix operand order for th.addsl.
> >
> > Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
> > ---
> >  gcc/config/riscv/riscv.md                     |  1 +
> >  gcc/config/riscv/thead.md                     | 31 +++++++++++
> >  .../gcc.target/riscv/xtheadba-addsl.c         | 55 +++++++++++++++++++
> >  3 files changed, 87 insertions(+)
> >  create mode 100644 gcc/config/riscv/thead.md
> >  create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadba-addsl.c
> >
> > diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
> > index 05924e9bbf1..d6c2265e9d4 100644
> > --- a/gcc/config/riscv/riscv.md
> > +++ b/gcc/config/riscv/riscv.md
> > @@ -3093,4 +3093,5 @@ (define_insn "riscv_prefetchi_<mode>"
> >  (include "pic.md")
> >  (include "generic.md")
> >  (include "sifive-7.md")
> > +(include "thead.md")
> >  (include "vector.md")
> > diff --git a/gcc/config/riscv/thead.md b/gcc/config/riscv/thead.md
> > new file mode 100644
> > index 00000000000..158e9124c3a
> > --- /dev/null
> > +++ b/gcc/config/riscv/thead.md
> > @@ -0,0 +1,31 @@
> > +;; Machine description for T-Head vendor extensions
> > +;; Copyright (C) 2021-2022 Free Software Foundation, Inc.
> > +
> > +;; This file is part of GCC.
> > +
> > +;; GCC is free software; you can redistribute it and/or modify
> > +;; it under the terms of the GNU General Public License as published by
> > +;; the Free Software Foundation; either version 3, or (at your option)
> > +;; any later version.
> > +
> > +;; GCC is distributed in the hope that it will be useful,
> > +;; but WITHOUT ANY WARRANTY; without even the implied warranty of
> > +;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> > +;; GNU General Public License for more details.
> > +
> > +;; You should have received a copy of the GNU General Public License
> > +;; along with GCC; see the file COPYING3.  If not see
> > +;; <http://www.gnu.org/licenses/>.
> > +
> > +;; XTheadBa
> > +
> > +(define_insn "*th_addsl"
> > +  [(set (match_operand:X 0 "register_operand" "=r")
> > +       (plus:X (ashift:X (match_operand:X 1 "register_operand" "r")
> > +                         (match_operand:QI 2 "immediate_operand" "I"))
> > +               (match_operand:X 3 "register_operand" "r")))]
> > +  "TARGET_XTHEADBA
> > +   && (INTVAL (operands[2]) >= 0) && (INTVAL (operands[2]) <= 3)"
> > +  "th.addsl\t%0,%3,%1,%2"
> > +  [(set_attr "type" "bitmanip")
> > +   (set_attr "mode" "<X:MODE>")])
> > diff --git a/gcc/testsuite/gcc.target/riscv/xtheadba-addsl.c b/gcc/testsuite/gcc.target/riscv/xtheadba-addsl.c
> > new file mode 100644
> > index 00000000000..5004735a246
> > --- /dev/null
> > +++ b/gcc/testsuite/gcc.target/riscv/xtheadba-addsl.c
> > @@ -0,0 +1,55 @@
> > +/* { dg-do compile } */
> > +/* { dg-options "-march=rv32gc_xtheadba" { target { rv32 } } } */
> > +/* { dg-options "-march=rv64gc_xtheadba" { target { rv64 } } } */
> > +/* { dg-skip-if "" { *-*-* } { "-O0" } } */
> > +
> > +long
> > +test_1 (long a, long b)
> > +{
> > +  /* th.addsl aX, aX, 1  */
> > +  return a + (b << 1);
> > +}
> > +
> > +int
> > +foos (short *x, int n)
> > +{
> > +  /* th.addsl aX, aX, 1  */
> > +  return x[n];
> > +}
> > +
> > +long
> > +test_2 (long a, long b)
> > +{
> > +  /* th.addsl aX, aX, 2  */
> > +  return a + (b << 2);
> > +}
> > +
> > +int
> > +fooi (int *x, int n)
> > +{
> > +  /* th.addsl aX, aX, 2  */
> > +  return x[n];
> > +}
> > +
> > +long
> > +test_3 (long a, long b)
> > +{
> > +  /* th.addsl aX, aX, 3  */
> > +  return a + (b << 3);
> > +}
> > +
> > +long
> > +fool (long *x, int n)
> > +{
> > +  /* th.addsl aX, aX, 2 (rv32)  */
> > +  /* th.addsl aX, aX, 3 (rv64)  */
> > +  return x[n];
> > +}
> > +
> > +/* { dg-final { scan-assembler-times "th.addsl\[ \t\]*a\[0-9\]+,a\[0-9\]+,a\[0-9\]+,1" 2 } } */
> > +
> > +/* { dg-final { scan-assembler-times "th.addsl\[ \t\]*a\[0-9\]+,a\[0-9\]+,a\[0-9\]+,2" 3 { target { rv32 } } } } */
> > +/* { dg-final { scan-assembler-times "th.addsl\[ \t\]*a\[0-9\]+,a\[0-9\]+,a\[0-9\]+,2" 2 { target { rv64 } } } } */
> > +
> > +/* { dg-final { scan-assembler-times "th.addsl\[ \t\]*a\[0-9\]+,a\[0-9\]+,a\[0-9\]+,3" 1 { target { rv32 } } } } */
> > +/* { dg-final { scan-assembler-times "th.addsl\[ \t\]*a\[0-9\]+,a\[0-9\]+,a\[0-9\]+,3" 2 { target { rv64 } } } } */
> > --
> > 2.39.2
> >
  

On Fri, Feb 24, 2023 at 10:54 AM Kito Cheng <kito.cheng@gmail.com> wrote:
>
> My impression is that md patterns will use first-match patterns? so
> the zba will get higher priority than xtheadba if both patterns are
> matched?

Yes, I was just about to write this.

/opt/riscv-thead/bin/riscv64-unknown-linux-gnu-gcc -O2
-march=rv64gc_zba_xtheadba -mtune=thead-c906 -S
./gcc/testsuite/gcc.target/riscv/xtheadba-addsl.c

The resulting xtheadba-addsl.s file has:
        .attribute arch, "rv64i2p0_m2p0_a2p0_f2p0_d2p0_c2p0_zba1p0_xtheadba1p0"
[...]
        sh1add  a0,a1,a0

So the standard extension will be preferred over the custom extension.


>
> On Fri, Feb 24, 2023 at 2:52 PM Andrew Pinski via Gcc-patches
> <gcc-patches@gcc.gnu.org> wrote:
> >
> > On Thu, Feb 23, 2023 at 9:55 PM Christoph Muellner
> > <christoph.muellner@vrull.eu> wrote:
> > >
> > > From: Christoph Müllner <christoph.muellner@vrull.eu>
> > >
> > > This patch adds support for the XTheadBa ISA extension.
> > > The new INSN pattern is defined in a new file to separate
> > > this vendor extension from the standard extensions.
> >
> > How does this interact with doing -march=rv32gc_xtheadba_zba ?
> > Seems like it might be better handle that case correctly. I suspect
> > these all XThreadB* extensions have a similar problem too.
> >
> > Thanks,
> > Andrew Pinski
> >
> > >
> > > gcc/ChangeLog:
> > >
> > >         * config/riscv/riscv.md: Include thead.md
> > >         * config/riscv/thead.md: New file.
> > >
> > > gcc/testsuite/ChangeLog:
> > >
> > >         * gcc.target/riscv/xtheadba-addsl.c: New test.
> > >
> > > Changes in v3:
> > > - Fix operand order for th.addsl.
> > >
> > > Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
> > > ---
> > >  gcc/config/riscv/riscv.md                     |  1 +
> > >  gcc/config/riscv/thead.md                     | 31 +++++++++++
> > >  .../gcc.target/riscv/xtheadba-addsl.c         | 55 +++++++++++++++++++
> > >  3 files changed, 87 insertions(+)
> > >  create mode 100644 gcc/config/riscv/thead.md
> > >  create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadba-addsl.c
> > >
> > > diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
> > > index 05924e9bbf1..d6c2265e9d4 100644
> > > --- a/gcc/config/riscv/riscv.md
> > > +++ b/gcc/config/riscv/riscv.md
> > > @@ -3093,4 +3093,5 @@ (define_insn "riscv_prefetchi_<mode>"
> > >  (include "pic.md")
> > >  (include "generic.md")
> > >  (include "sifive-7.md")
> > > +(include "thead.md")
> > >  (include "vector.md")
> > > diff --git a/gcc/config/riscv/thead.md b/gcc/config/riscv/thead.md
> > > new file mode 100644
> > > index 00000000000..158e9124c3a
> > > --- /dev/null
> > > +++ b/gcc/config/riscv/thead.md
> > > @@ -0,0 +1,31 @@
> > > +;; Machine description for T-Head vendor extensions
> > > +;; Copyright (C) 2021-2022 Free Software Foundation, Inc.
> > > +
> > > +;; This file is part of GCC.
> > > +
> > > +;; GCC is free software; you can redistribute it and/or modify
> > > +;; it under the terms of the GNU General Public License as published by
> > > +;; the Free Software Foundation; either version 3, or (at your option)
> > > +;; any later version.
> > > +
> > > +;; GCC is distributed in the hope that it will be useful,
> > > +;; but WITHOUT ANY WARRANTY; without even the implied warranty of
> > > +;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> > > +;; GNU General Public License for more details.
> > > +
> > > +;; You should have received a copy of the GNU General Public License
> > > +;; along with GCC; see the file COPYING3.  If not see
> > > +;; <http://www.gnu.org/licenses/>.
> > > +
> > > +;; XTheadBa
> > > +
> > > +(define_insn "*th_addsl"
> > > +  [(set (match_operand:X 0 "register_operand" "=r")
> > > +       (plus:X (ashift:X (match_operand:X 1 "register_operand" "r")
> > > +                         (match_operand:QI 2 "immediate_operand" "I"))
> > > +               (match_operand:X 3 "register_operand" "r")))]
> > > +  "TARGET_XTHEADBA
> > > +   && (INTVAL (operands[2]) >= 0) && (INTVAL (operands[2]) <= 3)"
> > > +  "th.addsl\t%0,%3,%1,%2"
> > > +  [(set_attr "type" "bitmanip")
> > > +   (set_attr "mode" "<X:MODE>")])
> > > diff --git a/gcc/testsuite/gcc.target/riscv/xtheadba-addsl.c b/gcc/testsuite/gcc.target/riscv/xtheadba-addsl.c
> > > new file mode 100644
> > > index 00000000000..5004735a246
> > > --- /dev/null
> > > +++ b/gcc/testsuite/gcc.target/riscv/xtheadba-addsl.c
> > > @@ -0,0 +1,55 @@
> > > +/* { dg-do compile } */
> > > +/* { dg-options "-march=rv32gc_xtheadba" { target { rv32 } } } */
> > > +/* { dg-options "-march=rv64gc_xtheadba" { target { rv64 } } } */
> > > +/* { dg-skip-if "" { *-*-* } { "-O0" } } */
> > > +
> > > +long
> > > +test_1 (long a, long b)
> > > +{
> > > +  /* th.addsl aX, aX, 1  */
> > > +  return a + (b << 1);
> > > +}
> > > +
> > > +int
> > > +foos (short *x, int n)
> > > +{
> > > +  /* th.addsl aX, aX, 1  */
> > > +  return x[n];
> > > +}
> > > +
> > > +long
> > > +test_2 (long a, long b)
> > > +{
> > > +  /* th.addsl aX, aX, 2  */
> > > +  return a + (b << 2);
> > > +}
> > > +
> > > +int
> > > +fooi (int *x, int n)
> > > +{
> > > +  /* th.addsl aX, aX, 2  */
> > > +  return x[n];
> > > +}
> > > +
> > > +long
> > > +test_3 (long a, long b)
> > > +{
> > > +  /* th.addsl aX, aX, 3  */
> > > +  return a + (b << 3);
> > > +}
> > > +
> > > +long
> > > +fool (long *x, int n)
> > > +{
> > > +  /* th.addsl aX, aX, 2 (rv32)  */
> > > +  /* th.addsl aX, aX, 3 (rv64)  */
> > > +  return x[n];
> > > +}
> > > +
> > > +/* { dg-final { scan-assembler-times "th.addsl\[ \t\]*a\[0-9\]+,a\[0-9\]+,a\[0-9\]+,1" 2 } } */
> > > +
> > > +/* { dg-final { scan-assembler-times "th.addsl\[ \t\]*a\[0-9\]+,a\[0-9\]+,a\[0-9\]+,2" 3 { target { rv32 } } } } */
> > > +/* { dg-final { scan-assembler-times "th.addsl\[ \t\]*a\[0-9\]+,a\[0-9\]+,a\[0-9\]+,2" 2 { target { rv64 } } } } */
> > > +
> > > +/* { dg-final { scan-assembler-times "th.addsl\[ \t\]*a\[0-9\]+,a\[0-9\]+,a\[0-9\]+,3" 1 { target { rv32 } } } } */
> > > +/* { dg-final { scan-assembler-times "th.addsl\[ \t\]*a\[0-9\]+,a\[0-9\]+,a\[0-9\]+,3" 2 { target { rv64 } } } } */
> > > --
> > > 2.39.2
> > >
  

On Fri, Feb 24, 2023 at 11:05 AM Christoph Müllner
<christoph.muellner@vrull.eu> wrote:
>
> On Fri, Feb 24, 2023 at 10:54 AM Kito Cheng <kito.cheng@gmail.com> wrote:
> >
> > My impression is that md patterns will use first-match patterns? so
> > the zba will get higher priority than xtheadba if both patterns are
> > matched?
>
> Yes, I was just about to write this.
>
> /opt/riscv-thead/bin/riscv64-unknown-linux-gnu-gcc -O2
> -march=rv64gc_zba_xtheadba -mtune=thead-c906 -S
> ./gcc/testsuite/gcc.target/riscv/xtheadba-addsl.c
>
> The resulting xtheadba-addsl.s file has:
>         .attribute arch, "rv64i2p0_m2p0_a2p0_f2p0_d2p0_c2p0_zba1p0_xtheadba1p0"
> [...]
>         sh1add  a0,a1,a0
>
> So the standard extension will be preferred over the custom extension.

I tested now with all of them (RV32 and RV64):

/opt/riscv-thead/bin/riscv64-unknown-linux-gnu-gcc -O2
-march=rv64gc_zba_xtheadba -mtune=thead-c906 -S
./gcc/testsuite/gcc.target/riscv/xtheadba-addsl.c
/opt/riscv-thead/bin/riscv64-unknown-linux-gnu-gcc -O2
-march=rv64gc_zbb_xtheadbb -mtune=thead-c906 -S
./gcc/testsuite/gcc.target/riscv/xtheadbb-ext.c
/opt/riscv-thead/bin/riscv64-unknown-linux-gnu-gcc -O2
-march=rv64gc_zbb_xtheadbb -mtune=thead-c906 -S
./gcc/testsuite/gcc.target/riscv/xtheadbb-extu.c
/opt/riscv-thead/bin/riscv64-unknown-linux-gnu-gcc -O2
-march=rv64gc_zbb_xtheadbb -mtune=thead-c906 -S
./gcc/testsuite/gcc.target/riscv/xtheadbb-extu-2.c
/opt/riscv-thead/bin/riscv64-unknown-linux-gnu-gcc -O2
-march=rv64gc_zbb_xtheadbb -mtune=thead-c906 -S
./gcc/testsuite/gcc.target/riscv/xtheadbb-ff1.c
/opt/riscv-thead/bin/riscv64-unknown-linux-gnu-gcc -O2
-march=rv64gc_zbb_xtheadbb -mtune=thead-c906 -S
./gcc/testsuite/gcc.target/riscv/xtheadbb-rev.c
/opt/riscv-thead/bin/riscv64-unknown-linux-gnu-gcc -O2
-march=rv64gc_zbb_xtheadbb -mtune=thead-c906 -S
./gcc/testsuite/gcc.target/riscv/xtheadbb-srri.c
/opt/riscv-thead/bin/riscv64-unknown-linux-gnu-gcc -O2
-march=rv64gc_zbb_xtheadbs -mtune=thead-c906 -S
./gcc/testsuite/gcc.target/riscv/xtheadbs-tst.c

/opt/riscv-thead32/bin/riscv32-unknown-linux-gnu-gcc -O2
-march=rv32gc_zba_xtheadba -mtune=thead-c906 -S
./gcc/testsuite/gcc.target/riscv/xtheadba-addsl.c
/opt/riscv-thead32/bin/riscv32-unknown-linux-gnu-gcc -O2
-march=rv32gc_zbb_xtheadbb -mtune=thead-c906 -S
./gcc/testsuite/gcc.target/riscv/xtheadbb-ext.c
/opt/riscv-thead32/bin/riscv32-unknown-linux-gnu-gcc -O2
-march=rv32gc_zbb_xtheadbb -mtune=thead-c906 -S
./gcc/testsuite/gcc.target/riscv/xtheadbb-extu.c
/opt/riscv-thead32/bin/riscv32-unknown-linux-gnu-gcc -O2
-march=rv32gc_zbb_xtheadbb -mtune=thead-c906 -S
./gcc/testsuite/gcc.target/riscv/xtheadbb-extu-2.c
/opt/riscv-thead32/bin/riscv32-unknown-linux-gnu-gcc -O2
-march=rv32gc_zbb_xtheadbb -mtune=thead-c906 -S
./gcc/testsuite/gcc.target/riscv/xtheadbb-ff1.c
/opt/riscv-thead32/bin/riscv32-unknown-linux-gnu-gcc -O2
-march=rv32gc_zbb_xtheadbb -mtune=thead-c906 -S
./gcc/testsuite/gcc.target/riscv/xtheadbb-rev.c
/opt/riscv-thead32/bin/riscv32-unknown-linux-gnu-gcc -O2
-march=rv32gc_zbb_xtheadbb -mtune=thead-c906 -S
./gcc/testsuite/gcc.target/riscv/xtheadbb-srri.c
/opt/riscv-thead32/bin/riscv32-unknown-linux-gnu-gcc -O2
-march=rv32gc_zbb_xtheadbs -mtune=thead-c906 -S
./gcc/testsuite/gcc.target/riscv/xtheadbs-tst.c

All behave ok (also when dropping the xtheadb* from the -march).

Is it ok to leave this as is?

Thanks,
Christoph

>
>
> >
> > On Fri, Feb 24, 2023 at 2:52 PM Andrew Pinski via Gcc-patches
> > <gcc-patches@gcc.gnu.org> wrote:
> > >
> > > On Thu, Feb 23, 2023 at 9:55 PM Christoph Muellner
> > > <christoph.muellner@vrull.eu> wrote:
> > > >
> > > > From: Christoph Müllner <christoph.muellner@vrull.eu>
> > > >
> > > > This patch adds support for the XTheadBa ISA extension.
> > > > The new INSN pattern is defined in a new file to separate
> > > > this vendor extension from the standard extensions.
> > >
> > > How does this interact with doing -march=rv32gc_xtheadba_zba ?
> > > Seems like it might be better handle that case correctly. I suspect
> > > these all XThreadB* extensions have a similar problem too.
> > >
> > > Thanks,
> > > Andrew Pinski
> > >
> > > >
> > > > gcc/ChangeLog:
> > > >
> > > >         * config/riscv/riscv.md: Include thead.md
> > > >         * config/riscv/thead.md: New file.
> > > >
> > > > gcc/testsuite/ChangeLog:
> > > >
> > > >         * gcc.target/riscv/xtheadba-addsl.c: New test.
> > > >
> > > > Changes in v3:
> > > > - Fix operand order for th.addsl.
> > > >
> > > > Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
> > > > ---
> > > >  gcc/config/riscv/riscv.md                     |  1 +
> > > >  gcc/config/riscv/thead.md                     | 31 +++++++++++
> > > >  .../gcc.target/riscv/xtheadba-addsl.c         | 55 +++++++++++++++++++
> > > >  3 files changed, 87 insertions(+)
> > > >  create mode 100644 gcc/config/riscv/thead.md
> > > >  create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadba-addsl.c
> > > >
> > > > diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
> > > > index 05924e9bbf1..d6c2265e9d4 100644
> > > > --- a/gcc/config/riscv/riscv.md
> > > > +++ b/gcc/config/riscv/riscv.md
> > > > @@ -3093,4 +3093,5 @@ (define_insn "riscv_prefetchi_<mode>"
> > > >  (include "pic.md")
> > > >  (include "generic.md")
> > > >  (include "sifive-7.md")
> > > > +(include "thead.md")
> > > >  (include "vector.md")
> > > > diff --git a/gcc/config/riscv/thead.md b/gcc/config/riscv/thead.md
> > > > new file mode 100644
> > > > index 00000000000..158e9124c3a
> > > > --- /dev/null
> > > > +++ b/gcc/config/riscv/thead.md
> > > > @@ -0,0 +1,31 @@
> > > > +;; Machine description for T-Head vendor extensions
> > > > +;; Copyright (C) 2021-2022 Free Software Foundation, Inc.
> > > > +
> > > > +;; This file is part of GCC.
> > > > +
> > > > +;; GCC is free software; you can redistribute it and/or modify
> > > > +;; it under the terms of the GNU General Public License as published by
> > > > +;; the Free Software Foundation; either version 3, or (at your option)
> > > > +;; any later version.
> > > > +
> > > > +;; GCC is distributed in the hope that it will be useful,
> > > > +;; but WITHOUT ANY WARRANTY; without even the implied warranty of
> > > > +;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> > > > +;; GNU General Public License for more details.
> > > > +
> > > > +;; You should have received a copy of the GNU General Public License
> > > > +;; along with GCC; see the file COPYING3.  If not see
> > > > +;; <http://www.gnu.org/licenses/>.
> > > > +
> > > > +;; XTheadBa
> > > > +
> > > > +(define_insn "*th_addsl"
> > > > +  [(set (match_operand:X 0 "register_operand" "=r")
> > > > +       (plus:X (ashift:X (match_operand:X 1 "register_operand" "r")
> > > > +                         (match_operand:QI 2 "immediate_operand" "I"))
> > > > +               (match_operand:X 3 "register_operand" "r")))]
> > > > +  "TARGET_XTHEADBA
> > > > +   && (INTVAL (operands[2]) >= 0) && (INTVAL (operands[2]) <= 3)"
> > > > +  "th.addsl\t%0,%3,%1,%2"
> > > > +  [(set_attr "type" "bitmanip")
> > > > +   (set_attr "mode" "<X:MODE>")])
> > > > diff --git a/gcc/testsuite/gcc.target/riscv/xtheadba-addsl.c b/gcc/testsuite/gcc.target/riscv/xtheadba-addsl.c
> > > > new file mode 100644
> > > > index 00000000000..5004735a246
> > > > --- /dev/null
> > > > +++ b/gcc/testsuite/gcc.target/riscv/xtheadba-addsl.c
> > > > @@ -0,0 +1,55 @@
> > > > +/* { dg-do compile } */
> > > > +/* { dg-options "-march=rv32gc_xtheadba" { target { rv32 } } } */
> > > > +/* { dg-options "-march=rv64gc_xtheadba" { target { rv64 } } } */
> > > > +/* { dg-skip-if "" { *-*-* } { "-O0" } } */
> > > > +
> > > > +long
> > > > +test_1 (long a, long b)
> > > > +{
> > > > +  /* th.addsl aX, aX, 1  */
> > > > +  return a + (b << 1);
> > > > +}
> > > > +
> > > > +int
> > > > +foos (short *x, int n)
> > > > +{
> > > > +  /* th.addsl aX, aX, 1  */
> > > > +  return x[n];
> > > > +}
> > > > +
> > > > +long
> > > > +test_2 (long a, long b)
> > > > +{
> > > > +  /* th.addsl aX, aX, 2  */
> > > > +  return a + (b << 2);
> > > > +}
> > > > +
> > > > +int
> > > > +fooi (int *x, int n)
> > > > +{
> > > > +  /* th.addsl aX, aX, 2  */
> > > > +  return x[n];
> > > > +}
> > > > +
> > > > +long
> > > > +test_3 (long a, long b)
> > > > +{
> > > > +  /* th.addsl aX, aX, 3  */
> > > > +  return a + (b << 3);
> > > > +}
> > > > +
> > > > +long
> > > > +fool (long *x, int n)
> > > > +{
> > > > +  /* th.addsl aX, aX, 2 (rv32)  */
> > > > +  /* th.addsl aX, aX, 3 (rv64)  */
> > > > +  return x[n];
> > > > +}
> > > > +
> > > > +/* { dg-final { scan-assembler-times "th.addsl\[ \t\]*a\[0-9\]+,a\[0-9\]+,a\[0-9\]+,1" 2 } } */
> > > > +
> > > > +/* { dg-final { scan-assembler-times "th.addsl\[ \t\]*a\[0-9\]+,a\[0-9\]+,a\[0-9\]+,2" 3 { target { rv32 } } } } */
> > > > +/* { dg-final { scan-assembler-times "th.addsl\[ \t\]*a\[0-9\]+,a\[0-9\]+,a\[0-9\]+,2" 2 { target { rv64 } } } } */
> > > > +
> > > > +/* { dg-final { scan-assembler-times "th.addsl\[ \t\]*a\[0-9\]+,a\[0-9\]+,a\[0-9\]+,3" 1 { target { rv32 } } } } */
> > > > +/* { dg-final { scan-assembler-times "th.addsl\[ \t\]*a\[0-9\]+,a\[0-9\]+,a\[0-9\]+,3" 2 { target { rv64 } } } } */
> > > > --
> > > > 2.39.2
> > > >