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([2a01:4f9:3a:1e26::2]) by smtp.gmail.com with ESMTPSA id c15-20020a17090603cf00b0088bd62b1cbbsm2976956eja.192.2023.02.10.14.41.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 10 Feb 2023 14:41:59 -0800 (PST) From: Philipp Tomsich To: gcc-patches@gcc.gnu.org Cc: Kito Cheng , Christoph Muellner , Palmer Dabbelt , Andrew Waterman , Vineet Gupta , Philipp Tomsich Subject: [RFC PATCH v1 06/10] RISC-V: Recognize sign-extract + and cases for czero.eqz/nez Date: Fri, 10 Feb 2023 23:41:46 +0100 Message-Id: <20230210224150.2801962-7-philipp.tomsich@vrull.eu> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230210224150.2801962-1-philipp.tomsich@vrull.eu> References: <20230210224150.2801962-1-philipp.tomsich@vrull.eu> MIME-Version: 1.0 X-Spam-Status: No, score=-11.0 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, JMQ_SPF_NEUTRAL, KAM_SHORT, LIKELY_SPAM_BODY, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" Users might use explicit arithmetic operations to create a mask and then and it, in a sequence like cond = (bits >> SHIFT) & 1; mask = ~(cond - 1); val &= mask; which will present as a single-bit sign-extract. Dependening on what combination of XVentanaCondOps and Zbs are available, this will map to the following sequences: - bexti + czero, if both Zbs and XVentanaCondOps are present - andi + czero, if only XVentanaCondOps is available and the sign-extract is operating on bits 10:0 (bit 11 can't be reached, as the immediate is sign-extended) - slli + srli + and, otherwise. gcc/ChangeLog: * config/riscv/zicond.md: Recognize SIGN_EXTRACT of a single-bit followed by AND for Zicond. gcc/testsuite/ChangeLog: * gcc.target/riscv/zicond-le-01.c: New test. Signed-off-by: Philipp Tomsich --- gcc/config/riscv/zicond.md | 45 +++++++++++++++++++ gcc/testsuite/gcc.target/riscv/zicond-le-01.c | 16 +++++++ 2 files changed, 61 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/zicond-le-01.c diff --git a/gcc/config/riscv/zicond.md b/gcc/config/riscv/zicond.md index 9d1ce067150..15fdaa539f1 100644 --- a/gcc/config/riscv/zicond.md +++ b/gcc/config/riscv/zicond.md @@ -98,3 +98,48 @@ (define_split operands[6] = gen_rtx_fmt_ee (GET_CODE (operands[1]) == LE ? GT : GTU, mode, operands[2], operands[3]); }) + +;; Users might use explicit arithmetic operations to create a mask and +;; then and it, in a sequence like +;; cond = (bits >> SHIFT) & 1; +;; mask = ~(cond - 1); +;; val &= mask; +;; which will present as a single-bit sign-extract in the combiner. +;; +;; This will give rise to any of the following cases: +;; - with Zbs and XVentanaCondOps: bexti + vt.maskc +;; - with XVentanaCondOps (but w/o Zbs): +;; - andi + vt.maskc, if the mask is representable in the immediate +;; (which requires extra care due to the immediate +;; being sign-extended) +;; - slli + srli + and +;; - otherwise: slli + srli + and + +;; With Zbb, we have bexti for all possible bits... +(define_split + [(set (match_operand:X 0 "register_operand") + (and:X (sign_extract:X (match_operand:X 1 "register_operand") + (const_int 1) + (match_operand 2 "immediate_operand")) + (match_operand:X 3 "register_operand"))) + (clobber (match_operand:X 4 "register_operand"))] + "TARGET_ZICOND && TARGET_ZBS" + [(set (match_dup 4) (zero_extract:X (match_dup 1) (const_int 1) (match_dup 2))) + (set (match_dup 0) (and:X (neg:X (ne:X (match_dup 4) (const_int 0))) + (match_dup 3)))]) + +;; ...whereas RV64I only allows us access to bits 0..10 in a single andi. +(define_split + [(set (match_operand:X 0 "register_operand") + (and:X (sign_extract:X (match_operand:X 1 "register_operand") + (const_int 1) + (match_operand 2 "immediate_operand")) + (match_operand:X 3 "register_operand"))) + (clobber (match_operand:X 4 "register_operand"))] + "TARGET_ZICOND && !TARGET_ZBS && (UINTVAL (operands[2]) < 11)" + [(set (match_dup 4) (and:X (match_dup 1) (match_dup 2))) + (set (match_dup 0) (and:X (neg:X (ne:X (match_dup 4) (const_int 0))) + (match_dup 3)))] +{ + operands[2] = GEN_INT(1 << UINTVAL(operands[2])); +}) diff --git a/gcc/testsuite/gcc.target/riscv/zicond-le-01.c b/gcc/testsuite/gcc.target/riscv/zicond-le-01.c new file mode 100644 index 00000000000..e5902d1ca5b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/zicond-le-01.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zicond -mabi=lp64 -mbranch-cost=4" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-O1" "-Os" "-Oz" } } */ + +long long sink (long long); + +long long le1 (long long a, long long b) +{ + if (a <= b) + b = 0; + + return sink(b); +} + +/* { dg-final { scan-assembler-times "sgt\t" 1 } } */ +/* { dg-final { scan-assembler-times "czero.eqz\t" 1 } } */