From patchwork Tue Feb 7 13:25:11 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiufu Guo X-Patchwork-Id: 64446 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id D541B3858C83 for ; Tue, 7 Feb 2023 13:25:52 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org D541B3858C83 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1675776352; bh=6Uyej99rE1AMCNI8CWJuyHg/NHvwEvW4PmPwcbSO+6A=; h=To:Cc:Subject:Date:List-Id:List-Unsubscribe:List-Archive: List-Post:List-Help:List-Subscribe:From:Reply-To:From; b=xQdwDVRUVdF9ASG6TZuc98VTnFD++GC5qsSf/mIJSU7tdG2gIBZtvT7qKsmFORwN4 93Y9JOI3EnWFeN6JyTwc1wmjstQteK2ZeyCwCC53HEcEJ28L4uRwgUrf4B8WXbYq9j HTk0pDyBdfAAZ9FBmdXQUB1MZdplvBhD+TEaU2y4= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mx0a-001b2d01.pphosted.com (mx0a-001b2d01.pphosted.com [148.163.156.1]) by sourceware.org (Postfix) with ESMTPS id C7A1C3858D33; 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Tue, 7 Feb 2023 13:25:16 GMT Received: from smtprelay02.fra02v.mail.ibm.com ([9.218.2.226]) by ppma04ams.nl.ibm.com (PPS) with ESMTPS id 3nhf06unn2-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 07 Feb 2023 13:25:16 +0000 Received: from smtpav03.fra02v.mail.ibm.com (smtpav03.fra02v.mail.ibm.com [10.20.54.102]) by smtprelay02.fra02v.mail.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 317DPDu332178622 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Tue, 7 Feb 2023 13:25:13 GMT Received: from smtpav03.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id AFFA72004B; Tue, 7 Feb 2023 13:25:13 +0000 (GMT) Received: from smtpav03.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 982082004E; Tue, 7 Feb 2023 13:25:12 +0000 (GMT) Received: from pike.rch.stglabs.ibm.com (unknown [9.5.12.127]) by smtpav03.fra02v.mail.ibm.com (Postfix) with ESMTP; Tue, 7 Feb 2023 13:25:12 +0000 (GMT) To: gcc-patches@gcc.gnu.org Cc: segher@kernel.crashing.org, dje.gcc@gmail.com, linkw@gcc.gnu.org, guojiufu@linux.ibm.com Subject: [PATCH] rs6000: Add new patterns rlwinm with mask Date: Tue, 7 Feb 2023 21:25:11 +0800 Message-Id: <20230207132511.94760-1-guojiufu@linux.ibm.com> X-Mailer: git-send-email 2.17.1 X-TM-AS-GCONF: 00 X-Proofpoint-GUID: CGCD61voRQYcE0_sKYkQykjqEqBBAowG X-Proofpoint-ORIG-GUID: PfUzHzzHj-hHg-UCoIWsSVXFP4H1IV1s X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.219,Aquarius:18.0.930,Hydra:6.0.562,FMLib:17.11.122.1 definitions=2023-02-07_05,2023-02-06_03,2022-06-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 lowpriorityscore=0 phishscore=0 malwarescore=0 mlxlogscore=675 priorityscore=1501 bulkscore=0 suspectscore=0 spamscore=0 mlxscore=0 impostorscore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2212070000 definitions=main-2302070116 X-Spam-Status: No, score=-11.8 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Jiufu Guo via Gcc-patches From: Jiufu Guo Reply-To: Jiufu Guo Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" Hi, For code: ``` u64 test_rlwinm_lowpart_mask (u32 v) { u32 v1 = ((v << N) | (v >> (32 - N))) & 0xfffff00; return (u64)v1; } ``` We generate "rlwinm 3,3,4,4,23; rldicl 3,3,0,32" instead of "rlwinm 3,3,4,4,23". Here the "rlwinm" cleans high32 bits already, so "rldicl" is reductant. Similarly, for the below code which is the functionality of "rlwinm". ``` u64 test_rlwinm_mask (u32 v) { u32 v1 = ((v << N) | (v >> (32 - N))); u64 v2 = (u64) v1 | ((u64) v1 << 32); return v2 & 0xffffffffe0000003ULL; } ``` We generate "rotlwi 3,3,4; sldi 9,3,32; add 3,9,3; rldicl 3,3,35,27; rldicl 3,3,29,0" instead of "rlwinm 3,3,4,30,2". This patch optimizes these two kinds of code to use just one "rlwinm" insn. Bootstrap and regtests pass on ppc64{,le}. Is this patch ok for trunk (or next stage1)? BR, Jeff (Jiufu) gcc/ChangeLog: * config/rs6000/predicates.md (lowpart_subreg_operand): New define_predicate. * config/rs6000/rs6000.md (rlwinm_lowpart_mask): New define_insn. (rlwinm_mask_): New define_insn. gcc/testsuite/ChangeLog: * gcc.target/powerpc/rlwinm-0.c: Reduce instruction number. * gcc.target/powerpc/rlwinm_3.c: New test. --- gcc/config/rs6000/predicates.md | 18 ++++++++ gcc/config/rs6000/rs6000.md | 34 +++++++++++++++ gcc/testsuite/gcc.target/powerpc/rlwinm-0.c | 6 +-- gcc/testsuite/gcc.target/powerpc/rlwinm_3.c | 47 +++++++++++++++++++++ 4 files changed, 102 insertions(+), 3 deletions(-) create mode 100644 gcc/testsuite/gcc.target/powerpc/rlwinm_3.c diff --git a/gcc/config/rs6000/predicates.md b/gcc/config/rs6000/predicates.md index 52c65534e51..3cc51d797c6 100644 --- a/gcc/config/rs6000/predicates.md +++ b/gcc/config/rs6000/predicates.md @@ -1290,6 +1290,24 @@ (define_predicate "mma_disassemble_output_operand" return vsx_register_operand (op, mode); }) +;; Return 1 if this operand is lowpart subreg +(define_predicate "lowpart_subreg_operand" + (match_code "subreg,reg") +{ + if (REG_P (op)) + return 1; + + rtx inner_reg = SUBREG_REG (op); + if (!REG_P (inner_reg)) + return 0; + + machine_mode inner_mode = GET_MODE (inner_reg); + if (SUBREG_BYTE (op) != subreg_lowpart_offset (mode, inner_mode)) + return 0; + + return 1; +}) + ;; Return true if operand is an operator used in rotate-and-mask instructions. (define_predicate "rotate_mask_operator" (match_code "rotate,ashift,lshiftrt")) diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index 4a7812fa592..a5d2b6ea000 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -4325,6 +4325,40 @@ (define_insn "*rotldi3_insert_7" [(set_attr "type" "insert") (set_attr "size" "64")]) +(define_insn "rlwinm_lowpart_mask" + [(set (match_operand:DI 0 "gpc_reg_operand" "=r") + (and:DI + (subreg:DI + (match_operator:SI 4 "rotate_mask_operator" + [(match_operand:SI 1 "lowpart_subreg_operand" "r") + (match_operand:SI 2 "const_int_operand" "n")]) 0) + (match_operand:DI 3 "const_int_operand" "n")))] + "TARGET_POWERPC64 && (UINTVAL (operands[3]) >> 32) == 0 + && rs6000_is_valid_shift_mask (operands[3], operands[4], SImode)" +{ + return rs6000_insn_for_shift_mask (SImode, operands, false); +} + [(set_attr "type" "shift")]) + +(define_insn "rlwinm_mask_" + [(set (match_operand:DI 0 "gpc_reg_operand" "=r") + (and:DI + (plus_ior_xor:DI + (ashift:DI + (subreg:DI + (match_operator:SI 4 "rotate_mask_operator" + [(match_operand:SI 1 "lowpart_subreg_operand" "r") + (match_operand:SI 2 "const_int_operand" "n")]) 0) + (const_int 32)) + (zero_extend:DI (match_dup 4))) + (match_operand:DI 3 "const_int_operand" "n")))] + "TARGET_POWERPC64 + && (UINTVAL (operands[3]) & 0xffffffff80000001ULL) == 0xffffffff80000001ULL + && rs6000_is_valid_mask (operands[3], NULL, NULL, SImode)" +{ + return rs6000_insn_for_shift_mask (SImode, operands, false); +} + [(set_attr "type" "shift")]) ; This handles the important case of multiple-precision shifts. There is ; no canonicalization rule for ASHIFT vs. LSHIFTRT, so two patterns. diff --git a/gcc/testsuite/gcc.target/powerpc/rlwinm-0.c b/gcc/testsuite/gcc.target/powerpc/rlwinm-0.c index 4f4fca2d8ef..50ff01e1925 100644 --- a/gcc/testsuite/gcc.target/powerpc/rlwinm-0.c +++ b/gcc/testsuite/gcc.target/powerpc/rlwinm-0.c @@ -2,12 +2,12 @@ /* { dg-options "-O2" } */ /* { dg-final { scan-assembler-times {(?n)^\s+[a-z]} 6739 { target ilp32 } } } */ -/* { dg-final { scan-assembler-times {(?n)^\s+[a-z]} 9716 { target lp64 } } } */ +/* { dg-final { scan-assembler-times {(?n)^\s+[a-z]} 8164 { target lp64 } } } */ /* { dg-final { scan-assembler-times {(?n)^\s+blr} 3375 } } */ -/* { dg-final { scan-assembler-times {(?n)^\s+rldicl} 3081 { target lp64 } } } */ +/* { dg-final { scan-assembler-times {(?n)^\s+rldicl} 1538 { target lp64 } } } */ /* { dg-final { scan-assembler-times {(?n)^\s+rlwinm} 3197 { target ilp32 } } } */ -/* { dg-final { scan-assembler-times {(?n)^\s+rlwinm} 3093 { target lp64 } } } */ +/* { dg-final { scan-assembler-times {(?n)^\s+rlwinm} 3084 { target lp64 } } } */ /* { dg-final { scan-assembler-times {(?n)^\s+rotlwi} 154 } } */ /* { dg-final { scan-assembler-times {(?n)^\s+srwi} 13 { target ilp32 } } } */ /* { dg-final { scan-assembler-times {(?n)^\s+srdi} 13 { target lp64 } } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/rlwinm_3.c b/gcc/testsuite/gcc.target/powerpc/rlwinm_3.c new file mode 100644 index 00000000000..65dcd69ace2 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/rlwinm_3.c @@ -0,0 +1,47 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -save-temps" } */ + +typedef unsigned long long u64; +typedef unsigned int u32; +#define NOINLE __attribute__ ((noinline)) +#define V (0x9753) + +#define MASK 0xffffffffe0000003ULL +#define N 4 +#define LMASK 0xfffff00 + +u64 NOINLE +test_rlwinm_lowpart_mask (u32 v) +{ + u32 v1 = ((v << N) | (v >> (32 - N))) & LMASK; + return (u64)v1; +} + +u64 NOINLE +test_rlwinm_mask (u32 v) +{ + u32 v1 = ((v << N) | (v >> (32 - N))); + u64 v2 = (u64) v1 | ((u64) v1 << 32); + return v2 & MASK; +} + +/* { dg-final { scan-assembler-times {\mrlwinm\M} 2 { target has_arch_ppc64 } } } */ + +#define RLWINM_L(v, n) \ + ((((v & 0xffffffffLL) << n) | ((v & 0xffffffffLL) >> (32 - n))) \ + & 0xffffffffLL) +#define RLWINM_MASK(v, n, m) (((RLWINM_L (v, n) << 32) | (RLWINM_L (v, n))) & m) + +u64 v_low_mask = RLWINM_MASK (V, N, LMASK); +u64 v_mask = RLWINM_MASK (V, N, MASK); + +int +main () +{ + u64 v = V; + if (test_rlwinm_lowpart_mask (v) != v_low_mask + || test_rlwinm_mask (v) != v_mask) + __builtin_abort (); + + return 0; +}