From patchwork Tue Feb 7 06:51:55 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?6ZKf5bGF5ZOy?= X-Patchwork-Id: 64430 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 800F93858C62 for ; Tue, 7 Feb 2023 06:52:30 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from smtpbgsg1.qq.com (smtpbgsg1.qq.com [54.254.200.92]) by sourceware.org (Postfix) with ESMTPS id 4B21D3858D1E for ; Tue, 7 Feb 2023 06:52:02 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 4B21D3858D1E Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivai.ai Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivai.ai X-QQ-mid: bizesmtp79t1675752717tpbb7o6r Received: from server1.localdomain ( [58.60.1.22]) by bizesmtp.qq.com (ESMTP) with id ; Tue, 07 Feb 2023 14:51:56 +0800 (CST) X-QQ-SSF: 01400000000000E0L000000A0000000 X-QQ-FEAT: q+yjhizk/eJS5ETI5dorrkGYwj8jiyvQ6VCPLFLCjm4wvGVruD76nVQiVqqv0 UAPVIRR7/pfv35lQ5Oyj04/HSDh6L/ZvxdKrHMP853RML65tG1zqMfUFGaluxwT3/60pQV6 qhwmuSzY6D1FCx8IhiOoEWajx8MElI/u97XD929zcrhid6wIpUafV0k1Tpuim5HrOQBG4aJ Gawnj7a5QDZw1EsQkZ4JHuOWqGIqI3aDRK6WQDxW3UGHv1k8FCwM1THvl9zDC8D91+gIVhs zllK/zUm8AQtqmPL3wKpBrKQ0YSL4UmHTRn0HFu8J7bIP+5ose9rjcj5hiqwOB7H+4RL2xJ qO/btNph80f0cWcKrv3KdqcgAeU+bn7s9TBmXSUU8zpAjoh92/6zCFaNCm18cIvjApGNnSx X-QQ-GoodBg: 2 From: juzhe.zhong@rivai.ai To: gcc-patches@gcc.gnu.org Cc: kito.cheng@gmail.com, Ju-Zhe Zhong Subject: [PATCH] RISC-V: Add vwaddu.v C++ API tests Date: Tue, 7 Feb 2023 14:51:55 +0800 Message-Id: <20230207065155.49564-1-juzhe.zhong@rivai.ai> X-Mailer: git-send-email 2.36.1 MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:rivai.ai:qybglogicsvr:qybglogicsvr7 X-Spam-Status: No, score=-10.9 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, RCVD_IN_BARRACUDACENTRAL, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_PASS, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" From: Ju-Zhe Zhong gcc/testsuite/ChangeLog: * g++.target/riscv/rvv/base/vwaddu_vv-1.C: New test. * g++.target/riscv/rvv/base/vwaddu_vv-2.C: New test. * g++.target/riscv/rvv/base/vwaddu_vv-3.C: New test. * g++.target/riscv/rvv/base/vwaddu_vv_mu-1.C: New test. * g++.target/riscv/rvv/base/vwaddu_vv_mu-2.C: New test. * g++.target/riscv/rvv/base/vwaddu_vv_mu-3.C: New test. * g++.target/riscv/rvv/base/vwaddu_vv_tu-1.C: New test. * g++.target/riscv/rvv/base/vwaddu_vv_tu-2.C: New test. * g++.target/riscv/rvv/base/vwaddu_vv_tu-3.C: New test. * g++.target/riscv/rvv/base/vwaddu_vv_tum-1.C: New test. * g++.target/riscv/rvv/base/vwaddu_vv_tum-2.C: New test. * g++.target/riscv/rvv/base/vwaddu_vv_tum-3.C: New test. * g++.target/riscv/rvv/base/vwaddu_vv_tumu-1.C: New test. * g++.target/riscv/rvv/base/vwaddu_vv_tumu-2.C: New test. * g++.target/riscv/rvv/base/vwaddu_vv_tumu-3.C: New test. * g++.target/riscv/rvv/base/vwaddu_vx-1.C: New test. * g++.target/riscv/rvv/base/vwaddu_vx-2.C: New test. * g++.target/riscv/rvv/base/vwaddu_vx-3.C: New test. * g++.target/riscv/rvv/base/vwaddu_vx_mu-1.C: New test. * g++.target/riscv/rvv/base/vwaddu_vx_mu-2.C: New test. * g++.target/riscv/rvv/base/vwaddu_vx_mu-3.C: New test. * g++.target/riscv/rvv/base/vwaddu_vx_tu-1.C: New test. * g++.target/riscv/rvv/base/vwaddu_vx_tu-2.C: New test. * g++.target/riscv/rvv/base/vwaddu_vx_tu-3.C: New test. * g++.target/riscv/rvv/base/vwaddu_vx_tum-1.C: New test. * g++.target/riscv/rvv/base/vwaddu_vx_tum-2.C: New test. * g++.target/riscv/rvv/base/vwaddu_vx_tum-3.C: New test. * g++.target/riscv/rvv/base/vwaddu_vx_tumu-1.C: New test. * g++.target/riscv/rvv/base/vwaddu_vx_tumu-2.C: New test. * g++.target/riscv/rvv/base/vwaddu_vx_tumu-3.C: New test. --- .../g++.target/riscv/rvv/base/vwaddu_vv-1.C | 216 ++++++++++++++++++ .../g++.target/riscv/rvv/base/vwaddu_vv-2.C | 216 ++++++++++++++++++ .../g++.target/riscv/rvv/base/vwaddu_vv-3.C | 216 ++++++++++++++++++ .../riscv/rvv/base/vwaddu_vv_mu-1.C | 111 +++++++++ .../riscv/rvv/base/vwaddu_vv_mu-2.C | 111 +++++++++ .../riscv/rvv/base/vwaddu_vv_mu-3.C | 111 +++++++++ .../riscv/rvv/base/vwaddu_vv_tu-1.C | 111 +++++++++ .../riscv/rvv/base/vwaddu_vv_tu-2.C | 111 +++++++++ .../riscv/rvv/base/vwaddu_vv_tu-3.C | 111 +++++++++ .../riscv/rvv/base/vwaddu_vv_tum-1.C | 111 +++++++++ .../riscv/rvv/base/vwaddu_vv_tum-2.C | 111 +++++++++ .../riscv/rvv/base/vwaddu_vv_tum-3.C | 111 +++++++++ .../riscv/rvv/base/vwaddu_vv_tumu-1.C | 111 +++++++++ .../riscv/rvv/base/vwaddu_vv_tumu-2.C | 111 +++++++++ .../riscv/rvv/base/vwaddu_vv_tumu-3.C | 111 +++++++++ .../g++.target/riscv/rvv/base/vwaddu_vx-1.C | 216 ++++++++++++++++++ .../g++.target/riscv/rvv/base/vwaddu_vx-2.C | 216 ++++++++++++++++++ .../g++.target/riscv/rvv/base/vwaddu_vx-3.C | 216 ++++++++++++++++++ .../riscv/rvv/base/vwaddu_vx_mu-1.C | 111 +++++++++ .../riscv/rvv/base/vwaddu_vx_mu-2.C | 111 +++++++++ .../riscv/rvv/base/vwaddu_vx_mu-3.C | 111 +++++++++ .../riscv/rvv/base/vwaddu_vx_tu-1.C | 111 +++++++++ .../riscv/rvv/base/vwaddu_vx_tu-2.C | 111 +++++++++ .../riscv/rvv/base/vwaddu_vx_tu-3.C | 111 +++++++++ .../riscv/rvv/base/vwaddu_vx_tum-1.C | 111 +++++++++ .../riscv/rvv/base/vwaddu_vx_tum-2.C | 111 +++++++++ .../riscv/rvv/base/vwaddu_vx_tum-3.C | 111 +++++++++ .../riscv/rvv/base/vwaddu_vx_tumu-1.C | 111 +++++++++ .../riscv/rvv/base/vwaddu_vx_tumu-2.C | 111 +++++++++ .../riscv/rvv/base/vwaddu_vx_tumu-3.C | 111 +++++++++ 30 files changed, 3960 insertions(+) create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_vv-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_vv-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_vv-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_vv_mu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_vv_mu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_vv_mu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_vv_tu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_vv_tu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_vv_tu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_vv_tum-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_vv_tum-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_vv_tum-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_vv_tumu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_vv_tumu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_vv_tumu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_vx-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_vx-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_vx-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_vx_mu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_vx_mu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_vx_mu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_vx_tu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_vx_tu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_vx_tu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_vx_tum-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_vx_tum-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_vx_tum-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_vx_tumu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_vx_tumu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_vx_tumu-3.C diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_vv-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_vv-1.C new file mode 100644 index 00000000000..d02b3dc99c9 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_vv-1.C @@ -0,0 +1,216 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwaddu_vv(vuint8mf8_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vwaddu_vv(op1,op2,vl); +} + + +vuint16mf2_t test___riscv_vwaddu_vv(vuint8mf4_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vwaddu_vv(op1,op2,vl); +} + + +vuint16m1_t test___riscv_vwaddu_vv(vuint8mf2_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vwaddu_vv(op1,op2,vl); +} + + +vuint16m2_t test___riscv_vwaddu_vv(vuint8m1_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vwaddu_vv(op1,op2,vl); +} + + +vuint16m4_t test___riscv_vwaddu_vv(vuint8m2_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vwaddu_vv(op1,op2,vl); +} + + +vuint16m8_t test___riscv_vwaddu_vv(vuint8m4_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vwaddu_vv(op1,op2,vl); +} + + +vuint32mf2_t test___riscv_vwaddu_vv(vuint16mf4_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vwaddu_vv(op1,op2,vl); +} + + +vuint32m1_t test___riscv_vwaddu_vv(vuint16mf2_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vwaddu_vv(op1,op2,vl); +} + + +vuint32m2_t test___riscv_vwaddu_vv(vuint16m1_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vwaddu_vv(op1,op2,vl); +} + + +vuint32m4_t test___riscv_vwaddu_vv(vuint16m2_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vwaddu_vv(op1,op2,vl); +} + + +vuint32m8_t test___riscv_vwaddu_vv(vuint16m4_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vwaddu_vv(op1,op2,vl); +} + + +vuint64m1_t test___riscv_vwaddu_vv(vuint32mf2_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vwaddu_vv(op1,op2,vl); +} + + +vuint64m2_t test___riscv_vwaddu_vv(vuint32m1_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vwaddu_vv(op1,op2,vl); +} + + +vuint64m4_t test___riscv_vwaddu_vv(vuint32m2_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vwaddu_vv(op1,op2,vl); +} + + +vuint64m8_t test___riscv_vwaddu_vv(vuint32m4_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vwaddu_vv(op1,op2,vl); +} + + +vuint16mf4_t test___riscv_vwaddu_vv(vbool64_t mask,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vwaddu_vv(mask,op1,op2,vl); +} + + +vuint16mf2_t test___riscv_vwaddu_vv(vbool32_t mask,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vwaddu_vv(mask,op1,op2,vl); +} + + +vuint16m1_t test___riscv_vwaddu_vv(vbool16_t mask,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vwaddu_vv(mask,op1,op2,vl); +} + + +vuint16m2_t test___riscv_vwaddu_vv(vbool8_t mask,vuint8m1_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vwaddu_vv(mask,op1,op2,vl); +} + + +vuint16m4_t test___riscv_vwaddu_vv(vbool4_t mask,vuint8m2_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vwaddu_vv(mask,op1,op2,vl); +} + + +vuint16m8_t test___riscv_vwaddu_vv(vbool2_t mask,vuint8m4_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vwaddu_vv(mask,op1,op2,vl); +} + + +vuint32mf2_t test___riscv_vwaddu_vv(vbool64_t mask,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vwaddu_vv(mask,op1,op2,vl); +} + + +vuint32m1_t test___riscv_vwaddu_vv(vbool32_t mask,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vwaddu_vv(mask,op1,op2,vl); +} + + +vuint32m2_t test___riscv_vwaddu_vv(vbool16_t mask,vuint16m1_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vwaddu_vv(mask,op1,op2,vl); +} + + +vuint32m4_t test___riscv_vwaddu_vv(vbool8_t mask,vuint16m2_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vwaddu_vv(mask,op1,op2,vl); +} + + +vuint32m8_t test___riscv_vwaddu_vv(vbool4_t mask,vuint16m4_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vwaddu_vv(mask,op1,op2,vl); +} + + +vuint64m1_t test___riscv_vwaddu_vv(vbool64_t mask,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vwaddu_vv(mask,op1,op2,vl); +} + + +vuint64m2_t test___riscv_vwaddu_vv(vbool32_t mask,vuint32m1_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vwaddu_vv(mask,op1,op2,vl); +} + + +vuint64m4_t test___riscv_vwaddu_vv(vbool16_t mask,vuint32m2_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vwaddu_vv(mask,op1,op2,vl); +} + + +vuint64m8_t test___riscv_vwaddu_vv(vbool8_t mask,vuint32m4_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vwaddu_vv(mask,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_vv-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_vv-2.C new file mode 100644 index 00000000000..761ee5d7ae1 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_vv-2.C @@ -0,0 +1,216 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwaddu_vv(vuint8mf8_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vwaddu_vv(op1,op2,31); +} + + +vuint16mf2_t test___riscv_vwaddu_vv(vuint8mf4_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vwaddu_vv(op1,op2,31); +} + + +vuint16m1_t test___riscv_vwaddu_vv(vuint8mf2_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vwaddu_vv(op1,op2,31); +} + + +vuint16m2_t test___riscv_vwaddu_vv(vuint8m1_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vwaddu_vv(op1,op2,31); +} + + +vuint16m4_t test___riscv_vwaddu_vv(vuint8m2_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vwaddu_vv(op1,op2,31); +} + + +vuint16m8_t test___riscv_vwaddu_vv(vuint8m4_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vwaddu_vv(op1,op2,31); +} + + +vuint32mf2_t test___riscv_vwaddu_vv(vuint16mf4_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vwaddu_vv(op1,op2,31); +} + + +vuint32m1_t test___riscv_vwaddu_vv(vuint16mf2_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vwaddu_vv(op1,op2,31); +} + + +vuint32m2_t test___riscv_vwaddu_vv(vuint16m1_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vwaddu_vv(op1,op2,31); +} + + +vuint32m4_t test___riscv_vwaddu_vv(vuint16m2_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vwaddu_vv(op1,op2,31); +} + + +vuint32m8_t test___riscv_vwaddu_vv(vuint16m4_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vwaddu_vv(op1,op2,31); +} + + +vuint64m1_t test___riscv_vwaddu_vv(vuint32mf2_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vwaddu_vv(op1,op2,31); +} + + +vuint64m2_t test___riscv_vwaddu_vv(vuint32m1_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vwaddu_vv(op1,op2,31); +} + + +vuint64m4_t test___riscv_vwaddu_vv(vuint32m2_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vwaddu_vv(op1,op2,31); +} + + +vuint64m8_t test___riscv_vwaddu_vv(vuint32m4_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vwaddu_vv(op1,op2,31); +} + + +vuint16mf4_t test___riscv_vwaddu_vv(vbool64_t mask,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vwaddu_vv(mask,op1,op2,31); +} + + +vuint16mf2_t test___riscv_vwaddu_vv(vbool32_t mask,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vwaddu_vv(mask,op1,op2,31); +} + + +vuint16m1_t test___riscv_vwaddu_vv(vbool16_t mask,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vwaddu_vv(mask,op1,op2,31); +} + + +vuint16m2_t test___riscv_vwaddu_vv(vbool8_t mask,vuint8m1_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vwaddu_vv(mask,op1,op2,31); +} + + +vuint16m4_t test___riscv_vwaddu_vv(vbool4_t mask,vuint8m2_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vwaddu_vv(mask,op1,op2,31); +} + + +vuint16m8_t test___riscv_vwaddu_vv(vbool2_t mask,vuint8m4_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vwaddu_vv(mask,op1,op2,31); +} + + +vuint32mf2_t test___riscv_vwaddu_vv(vbool64_t mask,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vwaddu_vv(mask,op1,op2,31); +} + + +vuint32m1_t test___riscv_vwaddu_vv(vbool32_t mask,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vwaddu_vv(mask,op1,op2,31); +} + + +vuint32m2_t test___riscv_vwaddu_vv(vbool16_t mask,vuint16m1_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vwaddu_vv(mask,op1,op2,31); +} + + +vuint32m4_t test___riscv_vwaddu_vv(vbool8_t mask,vuint16m2_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vwaddu_vv(mask,op1,op2,31); +} + + +vuint32m8_t test___riscv_vwaddu_vv(vbool4_t mask,vuint16m4_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vwaddu_vv(mask,op1,op2,31); +} + + +vuint64m1_t test___riscv_vwaddu_vv(vbool64_t mask,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vwaddu_vv(mask,op1,op2,31); +} + + +vuint64m2_t test___riscv_vwaddu_vv(vbool32_t mask,vuint32m1_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vwaddu_vv(mask,op1,op2,31); +} + + +vuint64m4_t test___riscv_vwaddu_vv(vbool16_t mask,vuint32m2_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vwaddu_vv(mask,op1,op2,31); +} + + +vuint64m8_t test___riscv_vwaddu_vv(vbool8_t mask,vuint32m4_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vwaddu_vv(mask,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_vv-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_vv-3.C new file mode 100644 index 00000000000..ce250cad294 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_vv-3.C @@ -0,0 +1,216 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwaddu_vv(vuint8mf8_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vwaddu_vv(op1,op2,32); +} + + +vuint16mf2_t test___riscv_vwaddu_vv(vuint8mf4_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vwaddu_vv(op1,op2,32); +} + + +vuint16m1_t test___riscv_vwaddu_vv(vuint8mf2_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vwaddu_vv(op1,op2,32); +} + + +vuint16m2_t test___riscv_vwaddu_vv(vuint8m1_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vwaddu_vv(op1,op2,32); +} + + +vuint16m4_t test___riscv_vwaddu_vv(vuint8m2_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vwaddu_vv(op1,op2,32); +} + + +vuint16m8_t test___riscv_vwaddu_vv(vuint8m4_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vwaddu_vv(op1,op2,32); +} + + +vuint32mf2_t test___riscv_vwaddu_vv(vuint16mf4_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vwaddu_vv(op1,op2,32); +} + + +vuint32m1_t test___riscv_vwaddu_vv(vuint16mf2_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vwaddu_vv(op1,op2,32); +} + + +vuint32m2_t test___riscv_vwaddu_vv(vuint16m1_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vwaddu_vv(op1,op2,32); +} + + +vuint32m4_t test___riscv_vwaddu_vv(vuint16m2_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vwaddu_vv(op1,op2,32); +} + + +vuint32m8_t test___riscv_vwaddu_vv(vuint16m4_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vwaddu_vv(op1,op2,32); +} + + +vuint64m1_t test___riscv_vwaddu_vv(vuint32mf2_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vwaddu_vv(op1,op2,32); +} + + +vuint64m2_t test___riscv_vwaddu_vv(vuint32m1_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vwaddu_vv(op1,op2,32); +} + + +vuint64m4_t test___riscv_vwaddu_vv(vuint32m2_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vwaddu_vv(op1,op2,32); +} + + +vuint64m8_t test___riscv_vwaddu_vv(vuint32m4_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vwaddu_vv(op1,op2,32); +} + + +vuint16mf4_t test___riscv_vwaddu_vv(vbool64_t mask,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vwaddu_vv(mask,op1,op2,32); +} + + +vuint16mf2_t test___riscv_vwaddu_vv(vbool32_t mask,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vwaddu_vv(mask,op1,op2,32); +} + + +vuint16m1_t test___riscv_vwaddu_vv(vbool16_t mask,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vwaddu_vv(mask,op1,op2,32); +} + + +vuint16m2_t test___riscv_vwaddu_vv(vbool8_t mask,vuint8m1_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vwaddu_vv(mask,op1,op2,32); +} + + +vuint16m4_t test___riscv_vwaddu_vv(vbool4_t mask,vuint8m2_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vwaddu_vv(mask,op1,op2,32); +} + + +vuint16m8_t test___riscv_vwaddu_vv(vbool2_t mask,vuint8m4_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vwaddu_vv(mask,op1,op2,32); +} + + +vuint32mf2_t test___riscv_vwaddu_vv(vbool64_t mask,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vwaddu_vv(mask,op1,op2,32); +} + + +vuint32m1_t test___riscv_vwaddu_vv(vbool32_t mask,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vwaddu_vv(mask,op1,op2,32); +} + + +vuint32m2_t test___riscv_vwaddu_vv(vbool16_t mask,vuint16m1_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vwaddu_vv(mask,op1,op2,32); +} + + +vuint32m4_t test___riscv_vwaddu_vv(vbool8_t mask,vuint16m2_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vwaddu_vv(mask,op1,op2,32); +} + + +vuint32m8_t test___riscv_vwaddu_vv(vbool4_t mask,vuint16m4_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vwaddu_vv(mask,op1,op2,32); +} + + +vuint64m1_t test___riscv_vwaddu_vv(vbool64_t mask,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vwaddu_vv(mask,op1,op2,32); +} + + +vuint64m2_t test___riscv_vwaddu_vv(vbool32_t mask,vuint32m1_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vwaddu_vv(mask,op1,op2,32); +} + + +vuint64m4_t test___riscv_vwaddu_vv(vbool16_t mask,vuint32m2_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vwaddu_vv(mask,op1,op2,32); +} + + +vuint64m8_t test___riscv_vwaddu_vv(vbool8_t mask,vuint32m4_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vwaddu_vv(mask,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_vv_mu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_vv_mu-1.C new file mode 100644 index 00000000000..e324e63c2eb --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_vv_mu-1.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwaddu_vv_mu(vbool64_t mask,vuint16mf4_t merge,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_mu(mask,merge,op1,op2,vl); +} + + +vuint16mf2_t test___riscv_vwaddu_vv_mu(vbool32_t mask,vuint16mf2_t merge,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_mu(mask,merge,op1,op2,vl); +} + + +vuint16m1_t test___riscv_vwaddu_vv_mu(vbool16_t mask,vuint16m1_t merge,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_mu(mask,merge,op1,op2,vl); +} + + +vuint16m2_t test___riscv_vwaddu_vv_mu(vbool8_t mask,vuint16m2_t merge,vuint8m1_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_mu(mask,merge,op1,op2,vl); +} + + +vuint16m4_t test___riscv_vwaddu_vv_mu(vbool4_t mask,vuint16m4_t merge,vuint8m2_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_mu(mask,merge,op1,op2,vl); +} + + +vuint16m8_t test___riscv_vwaddu_vv_mu(vbool2_t mask,vuint16m8_t merge,vuint8m4_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_mu(mask,merge,op1,op2,vl); +} + + +vuint32mf2_t test___riscv_vwaddu_vv_mu(vbool64_t mask,vuint32mf2_t merge,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_mu(mask,merge,op1,op2,vl); +} + + +vuint32m1_t test___riscv_vwaddu_vv_mu(vbool32_t mask,vuint32m1_t merge,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_mu(mask,merge,op1,op2,vl); +} + + +vuint32m2_t test___riscv_vwaddu_vv_mu(vbool16_t mask,vuint32m2_t merge,vuint16m1_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_mu(mask,merge,op1,op2,vl); +} + + +vuint32m4_t test___riscv_vwaddu_vv_mu(vbool8_t mask,vuint32m4_t merge,vuint16m2_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_mu(mask,merge,op1,op2,vl); +} + + +vuint32m8_t test___riscv_vwaddu_vv_mu(vbool4_t mask,vuint32m8_t merge,vuint16m4_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_mu(mask,merge,op1,op2,vl); +} + + +vuint64m1_t test___riscv_vwaddu_vv_mu(vbool64_t mask,vuint64m1_t merge,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_mu(mask,merge,op1,op2,vl); +} + + +vuint64m2_t test___riscv_vwaddu_vv_mu(vbool32_t mask,vuint64m2_t merge,vuint32m1_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_mu(mask,merge,op1,op2,vl); +} + + +vuint64m4_t test___riscv_vwaddu_vv_mu(vbool16_t mask,vuint64m4_t merge,vuint32m2_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_mu(mask,merge,op1,op2,vl); +} + + +vuint64m8_t test___riscv_vwaddu_vv_mu(vbool8_t mask,vuint64m8_t merge,vuint32m4_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_mu(mask,merge,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_vv_mu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_vv_mu-2.C new file mode 100644 index 00000000000..1bca86eeb15 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_vv_mu-2.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwaddu_vv_mu(vbool64_t mask,vuint16mf4_t merge,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_mu(mask,merge,op1,op2,31); +} + + +vuint16mf2_t test___riscv_vwaddu_vv_mu(vbool32_t mask,vuint16mf2_t merge,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_mu(mask,merge,op1,op2,31); +} + + +vuint16m1_t test___riscv_vwaddu_vv_mu(vbool16_t mask,vuint16m1_t merge,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_mu(mask,merge,op1,op2,31); +} + + +vuint16m2_t test___riscv_vwaddu_vv_mu(vbool8_t mask,vuint16m2_t merge,vuint8m1_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_mu(mask,merge,op1,op2,31); +} + + +vuint16m4_t test___riscv_vwaddu_vv_mu(vbool4_t mask,vuint16m4_t merge,vuint8m2_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_mu(mask,merge,op1,op2,31); +} + + +vuint16m8_t test___riscv_vwaddu_vv_mu(vbool2_t mask,vuint16m8_t merge,vuint8m4_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_mu(mask,merge,op1,op2,31); +} + + +vuint32mf2_t test___riscv_vwaddu_vv_mu(vbool64_t mask,vuint32mf2_t merge,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_mu(mask,merge,op1,op2,31); +} + + +vuint32m1_t test___riscv_vwaddu_vv_mu(vbool32_t mask,vuint32m1_t merge,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_mu(mask,merge,op1,op2,31); +} + + +vuint32m2_t test___riscv_vwaddu_vv_mu(vbool16_t mask,vuint32m2_t merge,vuint16m1_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_mu(mask,merge,op1,op2,31); +} + + +vuint32m4_t test___riscv_vwaddu_vv_mu(vbool8_t mask,vuint32m4_t merge,vuint16m2_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_mu(mask,merge,op1,op2,31); +} + + +vuint32m8_t test___riscv_vwaddu_vv_mu(vbool4_t mask,vuint32m8_t merge,vuint16m4_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_mu(mask,merge,op1,op2,31); +} + + +vuint64m1_t test___riscv_vwaddu_vv_mu(vbool64_t mask,vuint64m1_t merge,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_mu(mask,merge,op1,op2,31); +} + + +vuint64m2_t test___riscv_vwaddu_vv_mu(vbool32_t mask,vuint64m2_t merge,vuint32m1_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_mu(mask,merge,op1,op2,31); +} + + +vuint64m4_t test___riscv_vwaddu_vv_mu(vbool16_t mask,vuint64m4_t merge,vuint32m2_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_mu(mask,merge,op1,op2,31); +} + + +vuint64m8_t test___riscv_vwaddu_vv_mu(vbool8_t mask,vuint64m8_t merge,vuint32m4_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_mu(mask,merge,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*mu\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*mu\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*mu\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*mu\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*mu\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*mu\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*mu\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*mu\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*mu\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_vv_mu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_vv_mu-3.C new file mode 100644 index 00000000000..365bacfe19b --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_vv_mu-3.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwaddu_vv_mu(vbool64_t mask,vuint16mf4_t merge,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_mu(mask,merge,op1,op2,32); +} + + +vuint16mf2_t test___riscv_vwaddu_vv_mu(vbool32_t mask,vuint16mf2_t merge,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_mu(mask,merge,op1,op2,32); +} + + +vuint16m1_t test___riscv_vwaddu_vv_mu(vbool16_t mask,vuint16m1_t merge,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_mu(mask,merge,op1,op2,32); +} + + +vuint16m2_t test___riscv_vwaddu_vv_mu(vbool8_t mask,vuint16m2_t merge,vuint8m1_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_mu(mask,merge,op1,op2,32); +} + + +vuint16m4_t test___riscv_vwaddu_vv_mu(vbool4_t mask,vuint16m4_t merge,vuint8m2_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_mu(mask,merge,op1,op2,32); +} + + +vuint16m8_t test___riscv_vwaddu_vv_mu(vbool2_t mask,vuint16m8_t merge,vuint8m4_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_mu(mask,merge,op1,op2,32); +} + + +vuint32mf2_t test___riscv_vwaddu_vv_mu(vbool64_t mask,vuint32mf2_t merge,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_mu(mask,merge,op1,op2,32); +} + + +vuint32m1_t test___riscv_vwaddu_vv_mu(vbool32_t mask,vuint32m1_t merge,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_mu(mask,merge,op1,op2,32); +} + + +vuint32m2_t test___riscv_vwaddu_vv_mu(vbool16_t mask,vuint32m2_t merge,vuint16m1_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_mu(mask,merge,op1,op2,32); +} + + +vuint32m4_t test___riscv_vwaddu_vv_mu(vbool8_t mask,vuint32m4_t merge,vuint16m2_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_mu(mask,merge,op1,op2,32); +} + + +vuint32m8_t test___riscv_vwaddu_vv_mu(vbool4_t mask,vuint32m8_t merge,vuint16m4_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_mu(mask,merge,op1,op2,32); +} + + +vuint64m1_t test___riscv_vwaddu_vv_mu(vbool64_t mask,vuint64m1_t merge,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_mu(mask,merge,op1,op2,32); +} + + +vuint64m2_t test___riscv_vwaddu_vv_mu(vbool32_t mask,vuint64m2_t merge,vuint32m1_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_mu(mask,merge,op1,op2,32); +} + + +vuint64m4_t test___riscv_vwaddu_vv_mu(vbool16_t mask,vuint64m4_t merge,vuint32m2_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_mu(mask,merge,op1,op2,32); +} + + +vuint64m8_t test___riscv_vwaddu_vv_mu(vbool8_t mask,vuint64m8_t merge,vuint32m4_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_mu(mask,merge,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_vv_tu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_vv_tu-1.C new file mode 100644 index 00000000000..f201e487fcb --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_vv_tu-1.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwaddu_vv_tu(vuint16mf4_t merge,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_tu(merge,op1,op2,vl); +} + + +vuint16mf2_t test___riscv_vwaddu_vv_tu(vuint16mf2_t merge,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_tu(merge,op1,op2,vl); +} + + +vuint16m1_t test___riscv_vwaddu_vv_tu(vuint16m1_t merge,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_tu(merge,op1,op2,vl); +} + + +vuint16m2_t test___riscv_vwaddu_vv_tu(vuint16m2_t merge,vuint8m1_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_tu(merge,op1,op2,vl); +} + + +vuint16m4_t test___riscv_vwaddu_vv_tu(vuint16m4_t merge,vuint8m2_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_tu(merge,op1,op2,vl); +} + + +vuint16m8_t test___riscv_vwaddu_vv_tu(vuint16m8_t merge,vuint8m4_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_tu(merge,op1,op2,vl); +} + + +vuint32mf2_t test___riscv_vwaddu_vv_tu(vuint32mf2_t merge,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_tu(merge,op1,op2,vl); +} + + +vuint32m1_t test___riscv_vwaddu_vv_tu(vuint32m1_t merge,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_tu(merge,op1,op2,vl); +} + + +vuint32m2_t test___riscv_vwaddu_vv_tu(vuint32m2_t merge,vuint16m1_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_tu(merge,op1,op2,vl); +} + + +vuint32m4_t test___riscv_vwaddu_vv_tu(vuint32m4_t merge,vuint16m2_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_tu(merge,op1,op2,vl); +} + + +vuint32m8_t test___riscv_vwaddu_vv_tu(vuint32m8_t merge,vuint16m4_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_tu(merge,op1,op2,vl); +} + + +vuint64m1_t test___riscv_vwaddu_vv_tu(vuint64m1_t merge,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_tu(merge,op1,op2,vl); +} + + +vuint64m2_t test___riscv_vwaddu_vv_tu(vuint64m2_t merge,vuint32m1_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_tu(merge,op1,op2,vl); +} + + +vuint64m4_t test___riscv_vwaddu_vv_tu(vuint64m4_t merge,vuint32m2_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_tu(merge,op1,op2,vl); +} + + +vuint64m8_t test___riscv_vwaddu_vv_tu(vuint64m8_t merge,vuint32m4_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_tu(merge,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_vv_tu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_vv_tu-2.C new file mode 100644 index 00000000000..74c3769a828 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_vv_tu-2.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwaddu_vv_tu(vuint16mf4_t merge,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_tu(merge,op1,op2,31); +} + + +vuint16mf2_t test___riscv_vwaddu_vv_tu(vuint16mf2_t merge,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_tu(merge,op1,op2,31); +} + + +vuint16m1_t test___riscv_vwaddu_vv_tu(vuint16m1_t merge,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_tu(merge,op1,op2,31); +} + + +vuint16m2_t test___riscv_vwaddu_vv_tu(vuint16m2_t merge,vuint8m1_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_tu(merge,op1,op2,31); +} + + +vuint16m4_t test___riscv_vwaddu_vv_tu(vuint16m4_t merge,vuint8m2_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_tu(merge,op1,op2,31); +} + + +vuint16m8_t test___riscv_vwaddu_vv_tu(vuint16m8_t merge,vuint8m4_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_tu(merge,op1,op2,31); +} + + +vuint32mf2_t test___riscv_vwaddu_vv_tu(vuint32mf2_t merge,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_tu(merge,op1,op2,31); +} + + +vuint32m1_t test___riscv_vwaddu_vv_tu(vuint32m1_t merge,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_tu(merge,op1,op2,31); +} + + +vuint32m2_t test___riscv_vwaddu_vv_tu(vuint32m2_t merge,vuint16m1_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_tu(merge,op1,op2,31); +} + + +vuint32m4_t test___riscv_vwaddu_vv_tu(vuint32m4_t merge,vuint16m2_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_tu(merge,op1,op2,31); +} + + +vuint32m8_t test___riscv_vwaddu_vv_tu(vuint32m8_t merge,vuint16m4_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_tu(merge,op1,op2,31); +} + + +vuint64m1_t test___riscv_vwaddu_vv_tu(vuint64m1_t merge,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_tu(merge,op1,op2,31); +} + + +vuint64m2_t test___riscv_vwaddu_vv_tu(vuint64m2_t merge,vuint32m1_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_tu(merge,op1,op2,31); +} + + +vuint64m4_t test___riscv_vwaddu_vv_tu(vuint64m4_t merge,vuint32m2_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_tu(merge,op1,op2,31); +} + + +vuint64m8_t test___riscv_vwaddu_vv_tu(vuint64m8_t merge,vuint32m4_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_tu(merge,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_vv_tu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_vv_tu-3.C new file mode 100644 index 00000000000..67278b15781 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_vv_tu-3.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwaddu_vv_tu(vuint16mf4_t merge,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_tu(merge,op1,op2,32); +} + + +vuint16mf2_t test___riscv_vwaddu_vv_tu(vuint16mf2_t merge,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_tu(merge,op1,op2,32); +} + + +vuint16m1_t test___riscv_vwaddu_vv_tu(vuint16m1_t merge,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_tu(merge,op1,op2,32); +} + + +vuint16m2_t test___riscv_vwaddu_vv_tu(vuint16m2_t merge,vuint8m1_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_tu(merge,op1,op2,32); +} + + +vuint16m4_t test___riscv_vwaddu_vv_tu(vuint16m4_t merge,vuint8m2_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_tu(merge,op1,op2,32); +} + + +vuint16m8_t test___riscv_vwaddu_vv_tu(vuint16m8_t merge,vuint8m4_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_tu(merge,op1,op2,32); +} + + +vuint32mf2_t test___riscv_vwaddu_vv_tu(vuint32mf2_t merge,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_tu(merge,op1,op2,32); +} + + +vuint32m1_t test___riscv_vwaddu_vv_tu(vuint32m1_t merge,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_tu(merge,op1,op2,32); +} + + +vuint32m2_t test___riscv_vwaddu_vv_tu(vuint32m2_t merge,vuint16m1_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_tu(merge,op1,op2,32); +} + + +vuint32m4_t test___riscv_vwaddu_vv_tu(vuint32m4_t merge,vuint16m2_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_tu(merge,op1,op2,32); +} + + +vuint32m8_t test___riscv_vwaddu_vv_tu(vuint32m8_t merge,vuint16m4_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_tu(merge,op1,op2,32); +} + + +vuint64m1_t test___riscv_vwaddu_vv_tu(vuint64m1_t merge,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_tu(merge,op1,op2,32); +} + + +vuint64m2_t test___riscv_vwaddu_vv_tu(vuint64m2_t merge,vuint32m1_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_tu(merge,op1,op2,32); +} + + +vuint64m4_t test___riscv_vwaddu_vv_tu(vuint64m4_t merge,vuint32m2_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_tu(merge,op1,op2,32); +} + + +vuint64m8_t test___riscv_vwaddu_vv_tu(vuint64m8_t merge,vuint32m4_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_tu(merge,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_vv_tum-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_vv_tum-1.C new file mode 100644 index 00000000000..38985b8bfe8 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_vv_tum-1.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwaddu_vv_tum(vbool64_t mask,vuint16mf4_t merge,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_tum(mask,merge,op1,op2,vl); +} + + +vuint16mf2_t test___riscv_vwaddu_vv_tum(vbool32_t mask,vuint16mf2_t merge,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_tum(mask,merge,op1,op2,vl); +} + + +vuint16m1_t test___riscv_vwaddu_vv_tum(vbool16_t mask,vuint16m1_t merge,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_tum(mask,merge,op1,op2,vl); +} + + +vuint16m2_t test___riscv_vwaddu_vv_tum(vbool8_t mask,vuint16m2_t merge,vuint8m1_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_tum(mask,merge,op1,op2,vl); +} + + +vuint16m4_t test___riscv_vwaddu_vv_tum(vbool4_t mask,vuint16m4_t merge,vuint8m2_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_tum(mask,merge,op1,op2,vl); +} + + +vuint16m8_t test___riscv_vwaddu_vv_tum(vbool2_t mask,vuint16m8_t merge,vuint8m4_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_tum(mask,merge,op1,op2,vl); +} + + +vuint32mf2_t test___riscv_vwaddu_vv_tum(vbool64_t mask,vuint32mf2_t merge,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_tum(mask,merge,op1,op2,vl); +} + + +vuint32m1_t test___riscv_vwaddu_vv_tum(vbool32_t mask,vuint32m1_t merge,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_tum(mask,merge,op1,op2,vl); +} + + +vuint32m2_t test___riscv_vwaddu_vv_tum(vbool16_t mask,vuint32m2_t merge,vuint16m1_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_tum(mask,merge,op1,op2,vl); +} + + +vuint32m4_t test___riscv_vwaddu_vv_tum(vbool8_t mask,vuint32m4_t merge,vuint16m2_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_tum(mask,merge,op1,op2,vl); +} + + +vuint32m8_t test___riscv_vwaddu_vv_tum(vbool4_t mask,vuint32m8_t merge,vuint16m4_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_tum(mask,merge,op1,op2,vl); +} + + +vuint64m1_t test___riscv_vwaddu_vv_tum(vbool64_t mask,vuint64m1_t merge,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_tum(mask,merge,op1,op2,vl); +} + + +vuint64m2_t test___riscv_vwaddu_vv_tum(vbool32_t mask,vuint64m2_t merge,vuint32m1_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_tum(mask,merge,op1,op2,vl); +} + + +vuint64m4_t test___riscv_vwaddu_vv_tum(vbool16_t mask,vuint64m4_t merge,vuint32m2_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_tum(mask,merge,op1,op2,vl); +} + + +vuint64m8_t test___riscv_vwaddu_vv_tum(vbool8_t mask,vuint64m8_t merge,vuint32m4_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_tum(mask,merge,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_vv_tum-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_vv_tum-2.C new file mode 100644 index 00000000000..ca6fad08683 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_vv_tum-2.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwaddu_vv_tum(vbool64_t mask,vuint16mf4_t merge,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_tum(mask,merge,op1,op2,31); +} + + +vuint16mf2_t test___riscv_vwaddu_vv_tum(vbool32_t mask,vuint16mf2_t merge,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_tum(mask,merge,op1,op2,31); +} + + +vuint16m1_t test___riscv_vwaddu_vv_tum(vbool16_t mask,vuint16m1_t merge,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_tum(mask,merge,op1,op2,31); +} + + +vuint16m2_t test___riscv_vwaddu_vv_tum(vbool8_t mask,vuint16m2_t merge,vuint8m1_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_tum(mask,merge,op1,op2,31); +} + + +vuint16m4_t test___riscv_vwaddu_vv_tum(vbool4_t mask,vuint16m4_t merge,vuint8m2_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_tum(mask,merge,op1,op2,31); +} + + +vuint16m8_t test___riscv_vwaddu_vv_tum(vbool2_t mask,vuint16m8_t merge,vuint8m4_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_tum(mask,merge,op1,op2,31); +} + + +vuint32mf2_t test___riscv_vwaddu_vv_tum(vbool64_t mask,vuint32mf2_t merge,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_tum(mask,merge,op1,op2,31); +} + + +vuint32m1_t test___riscv_vwaddu_vv_tum(vbool32_t mask,vuint32m1_t merge,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_tum(mask,merge,op1,op2,31); +} + + +vuint32m2_t test___riscv_vwaddu_vv_tum(vbool16_t mask,vuint32m2_t merge,vuint16m1_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_tum(mask,merge,op1,op2,31); +} + + +vuint32m4_t test___riscv_vwaddu_vv_tum(vbool8_t mask,vuint32m4_t merge,vuint16m2_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_tum(mask,merge,op1,op2,31); +} + + +vuint32m8_t test___riscv_vwaddu_vv_tum(vbool4_t mask,vuint32m8_t merge,vuint16m4_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_tum(mask,merge,op1,op2,31); +} + + +vuint64m1_t test___riscv_vwaddu_vv_tum(vbool64_t mask,vuint64m1_t merge,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_tum(mask,merge,op1,op2,31); +} + + +vuint64m2_t test___riscv_vwaddu_vv_tum(vbool32_t mask,vuint64m2_t merge,vuint32m1_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_tum(mask,merge,op1,op2,31); +} + + +vuint64m4_t test___riscv_vwaddu_vv_tum(vbool16_t mask,vuint64m4_t merge,vuint32m2_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_tum(mask,merge,op1,op2,31); +} + + +vuint64m8_t test___riscv_vwaddu_vv_tum(vbool8_t mask,vuint64m8_t merge,vuint32m4_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_tum(mask,merge,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_vv_tum-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_vv_tum-3.C new file mode 100644 index 00000000000..51525f2c127 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_vv_tum-3.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwaddu_vv_tum(vbool64_t mask,vuint16mf4_t merge,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_tum(mask,merge,op1,op2,32); +} + + +vuint16mf2_t test___riscv_vwaddu_vv_tum(vbool32_t mask,vuint16mf2_t merge,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_tum(mask,merge,op1,op2,32); +} + + +vuint16m1_t test___riscv_vwaddu_vv_tum(vbool16_t mask,vuint16m1_t merge,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_tum(mask,merge,op1,op2,32); +} + + +vuint16m2_t test___riscv_vwaddu_vv_tum(vbool8_t mask,vuint16m2_t merge,vuint8m1_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_tum(mask,merge,op1,op2,32); +} + + +vuint16m4_t test___riscv_vwaddu_vv_tum(vbool4_t mask,vuint16m4_t merge,vuint8m2_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_tum(mask,merge,op1,op2,32); +} + + +vuint16m8_t test___riscv_vwaddu_vv_tum(vbool2_t mask,vuint16m8_t merge,vuint8m4_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_tum(mask,merge,op1,op2,32); +} + + +vuint32mf2_t test___riscv_vwaddu_vv_tum(vbool64_t mask,vuint32mf2_t merge,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_tum(mask,merge,op1,op2,32); +} + + +vuint32m1_t test___riscv_vwaddu_vv_tum(vbool32_t mask,vuint32m1_t merge,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_tum(mask,merge,op1,op2,32); +} + + +vuint32m2_t test___riscv_vwaddu_vv_tum(vbool16_t mask,vuint32m2_t merge,vuint16m1_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_tum(mask,merge,op1,op2,32); +} + + +vuint32m4_t test___riscv_vwaddu_vv_tum(vbool8_t mask,vuint32m4_t merge,vuint16m2_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_tum(mask,merge,op1,op2,32); +} + + +vuint32m8_t test___riscv_vwaddu_vv_tum(vbool4_t mask,vuint32m8_t merge,vuint16m4_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_tum(mask,merge,op1,op2,32); +} + + +vuint64m1_t test___riscv_vwaddu_vv_tum(vbool64_t mask,vuint64m1_t merge,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_tum(mask,merge,op1,op2,32); +} + + +vuint64m2_t test___riscv_vwaddu_vv_tum(vbool32_t mask,vuint64m2_t merge,vuint32m1_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_tum(mask,merge,op1,op2,32); +} + + +vuint64m4_t test___riscv_vwaddu_vv_tum(vbool16_t mask,vuint64m4_t merge,vuint32m2_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_tum(mask,merge,op1,op2,32); +} + + +vuint64m8_t test___riscv_vwaddu_vv_tum(vbool8_t mask,vuint64m8_t merge,vuint32m4_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_tum(mask,merge,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_vv_tumu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_vv_tumu-1.C new file mode 100644 index 00000000000..66ac7630ede --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_vv_tumu-1.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwaddu_vv_tumu(vbool64_t mask,vuint16mf4_t merge,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_tumu(mask,merge,op1,op2,vl); +} + + +vuint16mf2_t test___riscv_vwaddu_vv_tumu(vbool32_t mask,vuint16mf2_t merge,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_tumu(mask,merge,op1,op2,vl); +} + + +vuint16m1_t test___riscv_vwaddu_vv_tumu(vbool16_t mask,vuint16m1_t merge,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_tumu(mask,merge,op1,op2,vl); +} + + +vuint16m2_t test___riscv_vwaddu_vv_tumu(vbool8_t mask,vuint16m2_t merge,vuint8m1_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_tumu(mask,merge,op1,op2,vl); +} + + +vuint16m4_t test___riscv_vwaddu_vv_tumu(vbool4_t mask,vuint16m4_t merge,vuint8m2_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_tumu(mask,merge,op1,op2,vl); +} + + +vuint16m8_t test___riscv_vwaddu_vv_tumu(vbool2_t mask,vuint16m8_t merge,vuint8m4_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_tumu(mask,merge,op1,op2,vl); +} + + +vuint32mf2_t test___riscv_vwaddu_vv_tumu(vbool64_t mask,vuint32mf2_t merge,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_tumu(mask,merge,op1,op2,vl); +} + + +vuint32m1_t test___riscv_vwaddu_vv_tumu(vbool32_t mask,vuint32m1_t merge,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_tumu(mask,merge,op1,op2,vl); +} + + +vuint32m2_t test___riscv_vwaddu_vv_tumu(vbool16_t mask,vuint32m2_t merge,vuint16m1_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_tumu(mask,merge,op1,op2,vl); +} + + +vuint32m4_t test___riscv_vwaddu_vv_tumu(vbool8_t mask,vuint32m4_t merge,vuint16m2_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_tumu(mask,merge,op1,op2,vl); +} + + +vuint32m8_t test___riscv_vwaddu_vv_tumu(vbool4_t mask,vuint32m8_t merge,vuint16m4_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_tumu(mask,merge,op1,op2,vl); +} + + +vuint64m1_t test___riscv_vwaddu_vv_tumu(vbool64_t mask,vuint64m1_t merge,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_tumu(mask,merge,op1,op2,vl); +} + + +vuint64m2_t test___riscv_vwaddu_vv_tumu(vbool32_t mask,vuint64m2_t merge,vuint32m1_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_tumu(mask,merge,op1,op2,vl); +} + + +vuint64m4_t test___riscv_vwaddu_vv_tumu(vbool16_t mask,vuint64m4_t merge,vuint32m2_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_tumu(mask,merge,op1,op2,vl); +} + + +vuint64m8_t test___riscv_vwaddu_vv_tumu(vbool8_t mask,vuint64m8_t merge,vuint32m4_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_tumu(mask,merge,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_vv_tumu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_vv_tumu-2.C new file mode 100644 index 00000000000..624b0e66364 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_vv_tumu-2.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwaddu_vv_tumu(vbool64_t mask,vuint16mf4_t merge,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_tumu(mask,merge,op1,op2,31); +} + + +vuint16mf2_t test___riscv_vwaddu_vv_tumu(vbool32_t mask,vuint16mf2_t merge,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_tumu(mask,merge,op1,op2,31); +} + + +vuint16m1_t test___riscv_vwaddu_vv_tumu(vbool16_t mask,vuint16m1_t merge,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_tumu(mask,merge,op1,op2,31); +} + + +vuint16m2_t test___riscv_vwaddu_vv_tumu(vbool8_t mask,vuint16m2_t merge,vuint8m1_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_tumu(mask,merge,op1,op2,31); +} + + +vuint16m4_t test___riscv_vwaddu_vv_tumu(vbool4_t mask,vuint16m4_t merge,vuint8m2_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_tumu(mask,merge,op1,op2,31); +} + + +vuint16m8_t test___riscv_vwaddu_vv_tumu(vbool2_t mask,vuint16m8_t merge,vuint8m4_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_tumu(mask,merge,op1,op2,31); +} + + +vuint32mf2_t test___riscv_vwaddu_vv_tumu(vbool64_t mask,vuint32mf2_t merge,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_tumu(mask,merge,op1,op2,31); +} + + +vuint32m1_t test___riscv_vwaddu_vv_tumu(vbool32_t mask,vuint32m1_t merge,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_tumu(mask,merge,op1,op2,31); +} + + +vuint32m2_t test___riscv_vwaddu_vv_tumu(vbool16_t mask,vuint32m2_t merge,vuint16m1_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_tumu(mask,merge,op1,op2,31); +} + + +vuint32m4_t test___riscv_vwaddu_vv_tumu(vbool8_t mask,vuint32m4_t merge,vuint16m2_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_tumu(mask,merge,op1,op2,31); +} + + +vuint32m8_t test___riscv_vwaddu_vv_tumu(vbool4_t mask,vuint32m8_t merge,vuint16m4_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_tumu(mask,merge,op1,op2,31); +} + + +vuint64m1_t test___riscv_vwaddu_vv_tumu(vbool64_t mask,vuint64m1_t merge,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_tumu(mask,merge,op1,op2,31); +} + + +vuint64m2_t test___riscv_vwaddu_vv_tumu(vbool32_t mask,vuint64m2_t merge,vuint32m1_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_tumu(mask,merge,op1,op2,31); +} + + +vuint64m4_t test___riscv_vwaddu_vv_tumu(vbool16_t mask,vuint64m4_t merge,vuint32m2_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_tumu(mask,merge,op1,op2,31); +} + + +vuint64m8_t test___riscv_vwaddu_vv_tumu(vbool8_t mask,vuint64m8_t merge,vuint32m4_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_tumu(mask,merge,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*mu\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*mu\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*mu\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*mu\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*mu\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*mu\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*mu\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*mu\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*mu\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*mu\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*mu\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*mu\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*mu\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*mu\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*mu\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_vv_tumu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_vv_tumu-3.C new file mode 100644 index 00000000000..2372bed84cb --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_vv_tumu-3.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwaddu_vv_tumu(vbool64_t mask,vuint16mf4_t merge,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_tumu(mask,merge,op1,op2,32); +} + + +vuint16mf2_t test___riscv_vwaddu_vv_tumu(vbool32_t mask,vuint16mf2_t merge,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_tumu(mask,merge,op1,op2,32); +} + + +vuint16m1_t test___riscv_vwaddu_vv_tumu(vbool16_t mask,vuint16m1_t merge,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_tumu(mask,merge,op1,op2,32); +} + + +vuint16m2_t test___riscv_vwaddu_vv_tumu(vbool8_t mask,vuint16m2_t merge,vuint8m1_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_tumu(mask,merge,op1,op2,32); +} + + +vuint16m4_t test___riscv_vwaddu_vv_tumu(vbool4_t mask,vuint16m4_t merge,vuint8m2_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_tumu(mask,merge,op1,op2,32); +} + + +vuint16m8_t test___riscv_vwaddu_vv_tumu(vbool2_t mask,vuint16m8_t merge,vuint8m4_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_tumu(mask,merge,op1,op2,32); +} + + +vuint32mf2_t test___riscv_vwaddu_vv_tumu(vbool64_t mask,vuint32mf2_t merge,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_tumu(mask,merge,op1,op2,32); +} + + +vuint32m1_t test___riscv_vwaddu_vv_tumu(vbool32_t mask,vuint32m1_t merge,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_tumu(mask,merge,op1,op2,32); +} + + +vuint32m2_t test___riscv_vwaddu_vv_tumu(vbool16_t mask,vuint32m2_t merge,vuint16m1_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_tumu(mask,merge,op1,op2,32); +} + + +vuint32m4_t test___riscv_vwaddu_vv_tumu(vbool8_t mask,vuint32m4_t merge,vuint16m2_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_tumu(mask,merge,op1,op2,32); +} + + +vuint32m8_t test___riscv_vwaddu_vv_tumu(vbool4_t mask,vuint32m8_t merge,vuint16m4_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_tumu(mask,merge,op1,op2,32); +} + + +vuint64m1_t test___riscv_vwaddu_vv_tumu(vbool64_t mask,vuint64m1_t merge,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_tumu(mask,merge,op1,op2,32); +} + + +vuint64m2_t test___riscv_vwaddu_vv_tumu(vbool32_t mask,vuint64m2_t merge,vuint32m1_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_tumu(mask,merge,op1,op2,32); +} + + +vuint64m4_t test___riscv_vwaddu_vv_tumu(vbool16_t mask,vuint64m4_t merge,vuint32m2_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_tumu(mask,merge,op1,op2,32); +} + + +vuint64m8_t test___riscv_vwaddu_vv_tumu(vbool8_t mask,vuint64m8_t merge,vuint32m4_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_tumu(mask,merge,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_vx-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_vx-1.C new file mode 100644 index 00000000000..6134dd54fd8 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_vx-1.C @@ -0,0 +1,216 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwaddu_vx(vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_vx(op1,op2,vl); +} + + +vuint16mf2_t test___riscv_vwaddu_vx(vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_vx(op1,op2,vl); +} + + +vuint16m1_t test___riscv_vwaddu_vx(vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_vx(op1,op2,vl); +} + + +vuint16m2_t test___riscv_vwaddu_vx(vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_vx(op1,op2,vl); +} + + +vuint16m4_t test___riscv_vwaddu_vx(vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_vx(op1,op2,vl); +} + + +vuint16m8_t test___riscv_vwaddu_vx(vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_vx(op1,op2,vl); +} + + +vuint32mf2_t test___riscv_vwaddu_vx(vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_vx(op1,op2,vl); +} + + +vuint32m1_t test___riscv_vwaddu_vx(vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_vx(op1,op2,vl); +} + + +vuint32m2_t test___riscv_vwaddu_vx(vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_vx(op1,op2,vl); +} + + +vuint32m4_t test___riscv_vwaddu_vx(vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_vx(op1,op2,vl); +} + + +vuint32m8_t test___riscv_vwaddu_vx(vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_vx(op1,op2,vl); +} + + +vuint64m1_t test___riscv_vwaddu_vx(vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_vx(op1,op2,vl); +} + + +vuint64m2_t test___riscv_vwaddu_vx(vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_vx(op1,op2,vl); +} + + +vuint64m4_t test___riscv_vwaddu_vx(vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_vx(op1,op2,vl); +} + + +vuint64m8_t test___riscv_vwaddu_vx(vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_vx(op1,op2,vl); +} + + +vuint16mf4_t test___riscv_vwaddu_vx(vbool64_t mask,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_vx(mask,op1,op2,vl); +} + + +vuint16mf2_t test___riscv_vwaddu_vx(vbool32_t mask,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_vx(mask,op1,op2,vl); +} + + +vuint16m1_t test___riscv_vwaddu_vx(vbool16_t mask,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_vx(mask,op1,op2,vl); +} + + +vuint16m2_t test___riscv_vwaddu_vx(vbool8_t mask,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_vx(mask,op1,op2,vl); +} + + +vuint16m4_t test___riscv_vwaddu_vx(vbool4_t mask,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_vx(mask,op1,op2,vl); +} + + +vuint16m8_t test___riscv_vwaddu_vx(vbool2_t mask,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_vx(mask,op1,op2,vl); +} + + +vuint32mf2_t test___riscv_vwaddu_vx(vbool64_t mask,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_vx(mask,op1,op2,vl); +} + + +vuint32m1_t test___riscv_vwaddu_vx(vbool32_t mask,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_vx(mask,op1,op2,vl); +} + + +vuint32m2_t test___riscv_vwaddu_vx(vbool16_t mask,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_vx(mask,op1,op2,vl); +} + + +vuint32m4_t test___riscv_vwaddu_vx(vbool8_t mask,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_vx(mask,op1,op2,vl); +} + + +vuint32m8_t test___riscv_vwaddu_vx(vbool4_t mask,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_vx(mask,op1,op2,vl); +} + + +vuint64m1_t test___riscv_vwaddu_vx(vbool64_t mask,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_vx(mask,op1,op2,vl); +} + + +vuint64m2_t test___riscv_vwaddu_vx(vbool32_t mask,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_vx(mask,op1,op2,vl); +} + + +vuint64m4_t test___riscv_vwaddu_vx(vbool16_t mask,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_vx(mask,op1,op2,vl); +} + + +vuint64m8_t test___riscv_vwaddu_vx(vbool8_t mask,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_vx(mask,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_vx-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_vx-2.C new file mode 100644 index 00000000000..80b5f624250 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_vx-2.C @@ -0,0 +1,216 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwaddu_vx(vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_vx(op1,op2,31); +} + + +vuint16mf2_t test___riscv_vwaddu_vx(vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_vx(op1,op2,31); +} + + +vuint16m1_t test___riscv_vwaddu_vx(vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_vx(op1,op2,31); +} + + +vuint16m2_t test___riscv_vwaddu_vx(vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_vx(op1,op2,31); +} + + +vuint16m4_t test___riscv_vwaddu_vx(vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_vx(op1,op2,31); +} + + +vuint16m8_t test___riscv_vwaddu_vx(vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_vx(op1,op2,31); +} + + +vuint32mf2_t test___riscv_vwaddu_vx(vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_vx(op1,op2,31); +} + + +vuint32m1_t test___riscv_vwaddu_vx(vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_vx(op1,op2,31); +} + + +vuint32m2_t test___riscv_vwaddu_vx(vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_vx(op1,op2,31); +} + + +vuint32m4_t test___riscv_vwaddu_vx(vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_vx(op1,op2,31); +} + + +vuint32m8_t test___riscv_vwaddu_vx(vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_vx(op1,op2,31); +} + + +vuint64m1_t test___riscv_vwaddu_vx(vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_vx(op1,op2,31); +} + + +vuint64m2_t test___riscv_vwaddu_vx(vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_vx(op1,op2,31); +} + + +vuint64m4_t test___riscv_vwaddu_vx(vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_vx(op1,op2,31); +} + + +vuint64m8_t test___riscv_vwaddu_vx(vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_vx(op1,op2,31); +} + + +vuint16mf4_t test___riscv_vwaddu_vx(vbool64_t mask,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_vx(mask,op1,op2,31); +} + + +vuint16mf2_t test___riscv_vwaddu_vx(vbool32_t mask,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_vx(mask,op1,op2,31); +} + + +vuint16m1_t test___riscv_vwaddu_vx(vbool16_t mask,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_vx(mask,op1,op2,31); +} + + +vuint16m2_t test___riscv_vwaddu_vx(vbool8_t mask,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_vx(mask,op1,op2,31); +} + + +vuint16m4_t test___riscv_vwaddu_vx(vbool4_t mask,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_vx(mask,op1,op2,31); +} + + +vuint16m8_t test___riscv_vwaddu_vx(vbool2_t mask,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_vx(mask,op1,op2,31); +} + + +vuint32mf2_t test___riscv_vwaddu_vx(vbool64_t mask,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_vx(mask,op1,op2,31); +} + + +vuint32m1_t test___riscv_vwaddu_vx(vbool32_t mask,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_vx(mask,op1,op2,31); +} + + +vuint32m2_t test___riscv_vwaddu_vx(vbool16_t mask,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_vx(mask,op1,op2,31); +} + + +vuint32m4_t test___riscv_vwaddu_vx(vbool8_t mask,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_vx(mask,op1,op2,31); +} + + +vuint32m8_t test___riscv_vwaddu_vx(vbool4_t mask,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_vx(mask,op1,op2,31); +} + + +vuint64m1_t test___riscv_vwaddu_vx(vbool64_t mask,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_vx(mask,op1,op2,31); +} + + +vuint64m2_t test___riscv_vwaddu_vx(vbool32_t mask,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_vx(mask,op1,op2,31); +} + + +vuint64m4_t test___riscv_vwaddu_vx(vbool16_t mask,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_vx(mask,op1,op2,31); +} + + +vuint64m8_t test___riscv_vwaddu_vx(vbool8_t mask,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_vx(mask,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_vx-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_vx-3.C new file mode 100644 index 00000000000..0642838576e --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_vx-3.C @@ -0,0 +1,216 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwaddu_vx(vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_vx(op1,op2,32); +} + + +vuint16mf2_t test___riscv_vwaddu_vx(vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_vx(op1,op2,32); +} + + +vuint16m1_t test___riscv_vwaddu_vx(vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_vx(op1,op2,32); +} + + +vuint16m2_t test___riscv_vwaddu_vx(vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_vx(op1,op2,32); +} + + +vuint16m4_t test___riscv_vwaddu_vx(vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_vx(op1,op2,32); +} + + +vuint16m8_t test___riscv_vwaddu_vx(vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_vx(op1,op2,32); +} + + +vuint32mf2_t test___riscv_vwaddu_vx(vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_vx(op1,op2,32); +} + + +vuint32m1_t test___riscv_vwaddu_vx(vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_vx(op1,op2,32); +} + + +vuint32m2_t test___riscv_vwaddu_vx(vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_vx(op1,op2,32); +} + + +vuint32m4_t test___riscv_vwaddu_vx(vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_vx(op1,op2,32); +} + + +vuint32m8_t test___riscv_vwaddu_vx(vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_vx(op1,op2,32); +} + + +vuint64m1_t test___riscv_vwaddu_vx(vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_vx(op1,op2,32); +} + + +vuint64m2_t test___riscv_vwaddu_vx(vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_vx(op1,op2,32); +} + + +vuint64m4_t test___riscv_vwaddu_vx(vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_vx(op1,op2,32); +} + + +vuint64m8_t test___riscv_vwaddu_vx(vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_vx(op1,op2,32); +} + + +vuint16mf4_t test___riscv_vwaddu_vx(vbool64_t mask,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_vx(mask,op1,op2,32); +} + + +vuint16mf2_t test___riscv_vwaddu_vx(vbool32_t mask,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_vx(mask,op1,op2,32); +} + + +vuint16m1_t test___riscv_vwaddu_vx(vbool16_t mask,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_vx(mask,op1,op2,32); +} + + +vuint16m2_t test___riscv_vwaddu_vx(vbool8_t mask,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_vx(mask,op1,op2,32); +} + + +vuint16m4_t test___riscv_vwaddu_vx(vbool4_t mask,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_vx(mask,op1,op2,32); +} + + +vuint16m8_t test___riscv_vwaddu_vx(vbool2_t mask,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_vx(mask,op1,op2,32); +} + + +vuint32mf2_t test___riscv_vwaddu_vx(vbool64_t mask,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_vx(mask,op1,op2,32); +} + + +vuint32m1_t test___riscv_vwaddu_vx(vbool32_t mask,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_vx(mask,op1,op2,32); +} + + +vuint32m2_t test___riscv_vwaddu_vx(vbool16_t mask,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_vx(mask,op1,op2,32); +} + + +vuint32m4_t test___riscv_vwaddu_vx(vbool8_t mask,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_vx(mask,op1,op2,32); +} + + +vuint32m8_t test___riscv_vwaddu_vx(vbool4_t mask,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_vx(mask,op1,op2,32); +} + + +vuint64m1_t test___riscv_vwaddu_vx(vbool64_t mask,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_vx(mask,op1,op2,32); +} + + +vuint64m2_t test___riscv_vwaddu_vx(vbool32_t mask,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_vx(mask,op1,op2,32); +} + + +vuint64m4_t test___riscv_vwaddu_vx(vbool16_t mask,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_vx(mask,op1,op2,32); +} + + +vuint64m8_t test___riscv_vwaddu_vx(vbool8_t mask,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_vx(mask,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_vx_mu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_vx_mu-1.C new file mode 100644 index 00000000000..5634a62daff --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_vx_mu-1.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwaddu_vx_mu(vbool64_t mask,vuint16mf4_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_mu(mask,merge,op1,op2,vl); +} + + +vuint16mf2_t test___riscv_vwaddu_vx_mu(vbool32_t mask,vuint16mf2_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_mu(mask,merge,op1,op2,vl); +} + + +vuint16m1_t test___riscv_vwaddu_vx_mu(vbool16_t mask,vuint16m1_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_mu(mask,merge,op1,op2,vl); +} + + +vuint16m2_t test___riscv_vwaddu_vx_mu(vbool8_t mask,vuint16m2_t merge,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_mu(mask,merge,op1,op2,vl); +} + + +vuint16m4_t test___riscv_vwaddu_vx_mu(vbool4_t mask,vuint16m4_t merge,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_mu(mask,merge,op1,op2,vl); +} + + +vuint16m8_t test___riscv_vwaddu_vx_mu(vbool2_t mask,vuint16m8_t merge,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_mu(mask,merge,op1,op2,vl); +} + + +vuint32mf2_t test___riscv_vwaddu_vx_mu(vbool64_t mask,vuint32mf2_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_mu(mask,merge,op1,op2,vl); +} + + +vuint32m1_t test___riscv_vwaddu_vx_mu(vbool32_t mask,vuint32m1_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_mu(mask,merge,op1,op2,vl); +} + + +vuint32m2_t test___riscv_vwaddu_vx_mu(vbool16_t mask,vuint32m2_t merge,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_mu(mask,merge,op1,op2,vl); +} + + +vuint32m4_t test___riscv_vwaddu_vx_mu(vbool8_t mask,vuint32m4_t merge,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_mu(mask,merge,op1,op2,vl); +} + + +vuint32m8_t test___riscv_vwaddu_vx_mu(vbool4_t mask,vuint32m8_t merge,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_mu(mask,merge,op1,op2,vl); +} + + +vuint64m1_t test___riscv_vwaddu_vx_mu(vbool64_t mask,vuint64m1_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_mu(mask,merge,op1,op2,vl); +} + + +vuint64m2_t test___riscv_vwaddu_vx_mu(vbool32_t mask,vuint64m2_t merge,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_mu(mask,merge,op1,op2,vl); +} + + +vuint64m4_t test___riscv_vwaddu_vx_mu(vbool16_t mask,vuint64m4_t merge,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_mu(mask,merge,op1,op2,vl); +} + + +vuint64m8_t test___riscv_vwaddu_vx_mu(vbool8_t mask,vuint64m8_t merge,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_mu(mask,merge,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_vx_mu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_vx_mu-2.C new file mode 100644 index 00000000000..54682d9e424 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_vx_mu-2.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwaddu_vx_mu(vbool64_t mask,vuint16mf4_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_mu(mask,merge,op1,op2,31); +} + + +vuint16mf2_t test___riscv_vwaddu_vx_mu(vbool32_t mask,vuint16mf2_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_mu(mask,merge,op1,op2,31); +} + + +vuint16m1_t test___riscv_vwaddu_vx_mu(vbool16_t mask,vuint16m1_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_mu(mask,merge,op1,op2,31); +} + + +vuint16m2_t test___riscv_vwaddu_vx_mu(vbool8_t mask,vuint16m2_t merge,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_mu(mask,merge,op1,op2,31); +} + + +vuint16m4_t test___riscv_vwaddu_vx_mu(vbool4_t mask,vuint16m4_t merge,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_mu(mask,merge,op1,op2,31); +} + + +vuint16m8_t test___riscv_vwaddu_vx_mu(vbool2_t mask,vuint16m8_t merge,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_mu(mask,merge,op1,op2,31); +} + + +vuint32mf2_t test___riscv_vwaddu_vx_mu(vbool64_t mask,vuint32mf2_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_mu(mask,merge,op1,op2,31); +} + + +vuint32m1_t test___riscv_vwaddu_vx_mu(vbool32_t mask,vuint32m1_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_mu(mask,merge,op1,op2,31); +} + + +vuint32m2_t test___riscv_vwaddu_vx_mu(vbool16_t mask,vuint32m2_t merge,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_mu(mask,merge,op1,op2,31); +} + + +vuint32m4_t test___riscv_vwaddu_vx_mu(vbool8_t mask,vuint32m4_t merge,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_mu(mask,merge,op1,op2,31); +} + + +vuint32m8_t test___riscv_vwaddu_vx_mu(vbool4_t mask,vuint32m8_t merge,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_mu(mask,merge,op1,op2,31); +} + + +vuint64m1_t test___riscv_vwaddu_vx_mu(vbool64_t mask,vuint64m1_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_mu(mask,merge,op1,op2,31); +} + + +vuint64m2_t test___riscv_vwaddu_vx_mu(vbool32_t mask,vuint64m2_t merge,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_mu(mask,merge,op1,op2,31); +} + + +vuint64m4_t test___riscv_vwaddu_vx_mu(vbool16_t mask,vuint64m4_t merge,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_mu(mask,merge,op1,op2,31); +} + + +vuint64m8_t test___riscv_vwaddu_vx_mu(vbool8_t mask,vuint64m8_t merge,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_mu(mask,merge,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*mu\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*mu\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*mu\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*mu\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*mu\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*mu\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*mu\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*mu\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*mu\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_vx_mu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_vx_mu-3.C new file mode 100644 index 00000000000..dbc437e67d1 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_vx_mu-3.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwaddu_vx_mu(vbool64_t mask,vuint16mf4_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_mu(mask,merge,op1,op2,32); +} + + +vuint16mf2_t test___riscv_vwaddu_vx_mu(vbool32_t mask,vuint16mf2_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_mu(mask,merge,op1,op2,32); +} + + +vuint16m1_t test___riscv_vwaddu_vx_mu(vbool16_t mask,vuint16m1_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_mu(mask,merge,op1,op2,32); +} + + +vuint16m2_t test___riscv_vwaddu_vx_mu(vbool8_t mask,vuint16m2_t merge,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_mu(mask,merge,op1,op2,32); +} + + +vuint16m4_t test___riscv_vwaddu_vx_mu(vbool4_t mask,vuint16m4_t merge,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_mu(mask,merge,op1,op2,32); +} + + +vuint16m8_t test___riscv_vwaddu_vx_mu(vbool2_t mask,vuint16m8_t merge,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_mu(mask,merge,op1,op2,32); +} + + +vuint32mf2_t test___riscv_vwaddu_vx_mu(vbool64_t mask,vuint32mf2_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_mu(mask,merge,op1,op2,32); +} + + +vuint32m1_t test___riscv_vwaddu_vx_mu(vbool32_t mask,vuint32m1_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_mu(mask,merge,op1,op2,32); +} + + +vuint32m2_t test___riscv_vwaddu_vx_mu(vbool16_t mask,vuint32m2_t merge,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_mu(mask,merge,op1,op2,32); +} + + +vuint32m4_t test___riscv_vwaddu_vx_mu(vbool8_t mask,vuint32m4_t merge,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_mu(mask,merge,op1,op2,32); +} + + +vuint32m8_t test___riscv_vwaddu_vx_mu(vbool4_t mask,vuint32m8_t merge,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_mu(mask,merge,op1,op2,32); +} + + +vuint64m1_t test___riscv_vwaddu_vx_mu(vbool64_t mask,vuint64m1_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_mu(mask,merge,op1,op2,32); +} + + +vuint64m2_t test___riscv_vwaddu_vx_mu(vbool32_t mask,vuint64m2_t merge,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_mu(mask,merge,op1,op2,32); +} + + +vuint64m4_t test___riscv_vwaddu_vx_mu(vbool16_t mask,vuint64m4_t merge,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_mu(mask,merge,op1,op2,32); +} + + +vuint64m8_t test___riscv_vwaddu_vx_mu(vbool8_t mask,vuint64m8_t merge,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_mu(mask,merge,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_vx_tu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_vx_tu-1.C new file mode 100644 index 00000000000..44fe3c3cee2 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_vx_tu-1.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwaddu_vx_tu(vuint16mf4_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_tu(merge,op1,op2,vl); +} + + +vuint16mf2_t test___riscv_vwaddu_vx_tu(vuint16mf2_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_tu(merge,op1,op2,vl); +} + + +vuint16m1_t test___riscv_vwaddu_vx_tu(vuint16m1_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_tu(merge,op1,op2,vl); +} + + +vuint16m2_t test___riscv_vwaddu_vx_tu(vuint16m2_t merge,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_tu(merge,op1,op2,vl); +} + + +vuint16m4_t test___riscv_vwaddu_vx_tu(vuint16m4_t merge,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_tu(merge,op1,op2,vl); +} + + +vuint16m8_t test___riscv_vwaddu_vx_tu(vuint16m8_t merge,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_tu(merge,op1,op2,vl); +} + + +vuint32mf2_t test___riscv_vwaddu_vx_tu(vuint32mf2_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_tu(merge,op1,op2,vl); +} + + +vuint32m1_t test___riscv_vwaddu_vx_tu(vuint32m1_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_tu(merge,op1,op2,vl); +} + + +vuint32m2_t test___riscv_vwaddu_vx_tu(vuint32m2_t merge,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_tu(merge,op1,op2,vl); +} + + +vuint32m4_t test___riscv_vwaddu_vx_tu(vuint32m4_t merge,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_tu(merge,op1,op2,vl); +} + + +vuint32m8_t test___riscv_vwaddu_vx_tu(vuint32m8_t merge,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_tu(merge,op1,op2,vl); +} + + +vuint64m1_t test___riscv_vwaddu_vx_tu(vuint64m1_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_tu(merge,op1,op2,vl); +} + + +vuint64m2_t test___riscv_vwaddu_vx_tu(vuint64m2_t merge,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_tu(merge,op1,op2,vl); +} + + +vuint64m4_t test___riscv_vwaddu_vx_tu(vuint64m4_t merge,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_tu(merge,op1,op2,vl); +} + + +vuint64m8_t test___riscv_vwaddu_vx_tu(vuint64m8_t merge,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_tu(merge,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_vx_tu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_vx_tu-2.C new file mode 100644 index 00000000000..9171233156a --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_vx_tu-2.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwaddu_vx_tu(vuint16mf4_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_tu(merge,op1,op2,31); +} + + +vuint16mf2_t test___riscv_vwaddu_vx_tu(vuint16mf2_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_tu(merge,op1,op2,31); +} + + +vuint16m1_t test___riscv_vwaddu_vx_tu(vuint16m1_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_tu(merge,op1,op2,31); +} + + +vuint16m2_t test___riscv_vwaddu_vx_tu(vuint16m2_t merge,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_tu(merge,op1,op2,31); +} + + +vuint16m4_t test___riscv_vwaddu_vx_tu(vuint16m4_t merge,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_tu(merge,op1,op2,31); +} + + +vuint16m8_t test___riscv_vwaddu_vx_tu(vuint16m8_t merge,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_tu(merge,op1,op2,31); +} + + +vuint32mf2_t test___riscv_vwaddu_vx_tu(vuint32mf2_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_tu(merge,op1,op2,31); +} + + +vuint32m1_t test___riscv_vwaddu_vx_tu(vuint32m1_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_tu(merge,op1,op2,31); +} + + +vuint32m2_t test___riscv_vwaddu_vx_tu(vuint32m2_t merge,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_tu(merge,op1,op2,31); +} + + +vuint32m4_t test___riscv_vwaddu_vx_tu(vuint32m4_t merge,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_tu(merge,op1,op2,31); +} + + +vuint32m8_t test___riscv_vwaddu_vx_tu(vuint32m8_t merge,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_tu(merge,op1,op2,31); +} + + +vuint64m1_t test___riscv_vwaddu_vx_tu(vuint64m1_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_tu(merge,op1,op2,31); +} + + +vuint64m2_t test___riscv_vwaddu_vx_tu(vuint64m2_t merge,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_tu(merge,op1,op2,31); +} + + +vuint64m4_t test___riscv_vwaddu_vx_tu(vuint64m4_t merge,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_tu(merge,op1,op2,31); +} + + +vuint64m8_t test___riscv_vwaddu_vx_tu(vuint64m8_t merge,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_tu(merge,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_vx_tu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_vx_tu-3.C new file mode 100644 index 00000000000..1a7fa17f764 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_vx_tu-3.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwaddu_vx_tu(vuint16mf4_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_tu(merge,op1,op2,32); +} + + +vuint16mf2_t test___riscv_vwaddu_vx_tu(vuint16mf2_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_tu(merge,op1,op2,32); +} + + +vuint16m1_t test___riscv_vwaddu_vx_tu(vuint16m1_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_tu(merge,op1,op2,32); +} + + +vuint16m2_t test___riscv_vwaddu_vx_tu(vuint16m2_t merge,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_tu(merge,op1,op2,32); +} + + +vuint16m4_t test___riscv_vwaddu_vx_tu(vuint16m4_t merge,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_tu(merge,op1,op2,32); +} + + +vuint16m8_t test___riscv_vwaddu_vx_tu(vuint16m8_t merge,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_tu(merge,op1,op2,32); +} + + +vuint32mf2_t test___riscv_vwaddu_vx_tu(vuint32mf2_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_tu(merge,op1,op2,32); +} + + +vuint32m1_t test___riscv_vwaddu_vx_tu(vuint32m1_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_tu(merge,op1,op2,32); +} + + +vuint32m2_t test___riscv_vwaddu_vx_tu(vuint32m2_t merge,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_tu(merge,op1,op2,32); +} + + +vuint32m4_t test___riscv_vwaddu_vx_tu(vuint32m4_t merge,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_tu(merge,op1,op2,32); +} + + +vuint32m8_t test___riscv_vwaddu_vx_tu(vuint32m8_t merge,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_tu(merge,op1,op2,32); +} + + +vuint64m1_t test___riscv_vwaddu_vx_tu(vuint64m1_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_tu(merge,op1,op2,32); +} + + +vuint64m2_t test___riscv_vwaddu_vx_tu(vuint64m2_t merge,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_tu(merge,op1,op2,32); +} + + +vuint64m4_t test___riscv_vwaddu_vx_tu(vuint64m4_t merge,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_tu(merge,op1,op2,32); +} + + +vuint64m8_t test___riscv_vwaddu_vx_tu(vuint64m8_t merge,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_tu(merge,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_vx_tum-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_vx_tum-1.C new file mode 100644 index 00000000000..46a71709d10 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_vx_tum-1.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwaddu_vx_tum(vbool64_t mask,vuint16mf4_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_tum(mask,merge,op1,op2,vl); +} + + +vuint16mf2_t test___riscv_vwaddu_vx_tum(vbool32_t mask,vuint16mf2_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_tum(mask,merge,op1,op2,vl); +} + + +vuint16m1_t test___riscv_vwaddu_vx_tum(vbool16_t mask,vuint16m1_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_tum(mask,merge,op1,op2,vl); +} + + +vuint16m2_t test___riscv_vwaddu_vx_tum(vbool8_t mask,vuint16m2_t merge,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_tum(mask,merge,op1,op2,vl); +} + + +vuint16m4_t test___riscv_vwaddu_vx_tum(vbool4_t mask,vuint16m4_t merge,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_tum(mask,merge,op1,op2,vl); +} + + +vuint16m8_t test___riscv_vwaddu_vx_tum(vbool2_t mask,vuint16m8_t merge,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_tum(mask,merge,op1,op2,vl); +} + + +vuint32mf2_t test___riscv_vwaddu_vx_tum(vbool64_t mask,vuint32mf2_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_tum(mask,merge,op1,op2,vl); +} + + +vuint32m1_t test___riscv_vwaddu_vx_tum(vbool32_t mask,vuint32m1_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_tum(mask,merge,op1,op2,vl); +} + + +vuint32m2_t test___riscv_vwaddu_vx_tum(vbool16_t mask,vuint32m2_t merge,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_tum(mask,merge,op1,op2,vl); +} + + +vuint32m4_t test___riscv_vwaddu_vx_tum(vbool8_t mask,vuint32m4_t merge,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_tum(mask,merge,op1,op2,vl); +} + + +vuint32m8_t test___riscv_vwaddu_vx_tum(vbool4_t mask,vuint32m8_t merge,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_tum(mask,merge,op1,op2,vl); +} + + +vuint64m1_t test___riscv_vwaddu_vx_tum(vbool64_t mask,vuint64m1_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_tum(mask,merge,op1,op2,vl); +} + + +vuint64m2_t test___riscv_vwaddu_vx_tum(vbool32_t mask,vuint64m2_t merge,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_tum(mask,merge,op1,op2,vl); +} + + +vuint64m4_t test___riscv_vwaddu_vx_tum(vbool16_t mask,vuint64m4_t merge,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_tum(mask,merge,op1,op2,vl); +} + + +vuint64m8_t test___riscv_vwaddu_vx_tum(vbool8_t mask,vuint64m8_t merge,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_tum(mask,merge,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_vx_tum-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_vx_tum-2.C new file mode 100644 index 00000000000..abdb1c9a02b --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_vx_tum-2.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwaddu_vx_tum(vbool64_t mask,vuint16mf4_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_tum(mask,merge,op1,op2,31); +} + + +vuint16mf2_t test___riscv_vwaddu_vx_tum(vbool32_t mask,vuint16mf2_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_tum(mask,merge,op1,op2,31); +} + + +vuint16m1_t test___riscv_vwaddu_vx_tum(vbool16_t mask,vuint16m1_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_tum(mask,merge,op1,op2,31); +} + + +vuint16m2_t test___riscv_vwaddu_vx_tum(vbool8_t mask,vuint16m2_t merge,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_tum(mask,merge,op1,op2,31); +} + + +vuint16m4_t test___riscv_vwaddu_vx_tum(vbool4_t mask,vuint16m4_t merge,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_tum(mask,merge,op1,op2,31); +} + + +vuint16m8_t test___riscv_vwaddu_vx_tum(vbool2_t mask,vuint16m8_t merge,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_tum(mask,merge,op1,op2,31); +} + + +vuint32mf2_t test___riscv_vwaddu_vx_tum(vbool64_t mask,vuint32mf2_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_tum(mask,merge,op1,op2,31); +} + + +vuint32m1_t test___riscv_vwaddu_vx_tum(vbool32_t mask,vuint32m1_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_tum(mask,merge,op1,op2,31); +} + + +vuint32m2_t test___riscv_vwaddu_vx_tum(vbool16_t mask,vuint32m2_t merge,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_tum(mask,merge,op1,op2,31); +} + + +vuint32m4_t test___riscv_vwaddu_vx_tum(vbool8_t mask,vuint32m4_t merge,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_tum(mask,merge,op1,op2,31); +} + + +vuint32m8_t test___riscv_vwaddu_vx_tum(vbool4_t mask,vuint32m8_t merge,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_tum(mask,merge,op1,op2,31); +} + + +vuint64m1_t test___riscv_vwaddu_vx_tum(vbool64_t mask,vuint64m1_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_tum(mask,merge,op1,op2,31); +} + + +vuint64m2_t test___riscv_vwaddu_vx_tum(vbool32_t mask,vuint64m2_t merge,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_tum(mask,merge,op1,op2,31); +} + + +vuint64m4_t test___riscv_vwaddu_vx_tum(vbool16_t mask,vuint64m4_t merge,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_tum(mask,merge,op1,op2,31); +} + + +vuint64m8_t test___riscv_vwaddu_vx_tum(vbool8_t mask,vuint64m8_t merge,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_tum(mask,merge,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_vx_tum-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_vx_tum-3.C new file mode 100644 index 00000000000..f0b1c067ea4 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_vx_tum-3.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwaddu_vx_tum(vbool64_t mask,vuint16mf4_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_tum(mask,merge,op1,op2,32); +} + + +vuint16mf2_t test___riscv_vwaddu_vx_tum(vbool32_t mask,vuint16mf2_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_tum(mask,merge,op1,op2,32); +} + + +vuint16m1_t test___riscv_vwaddu_vx_tum(vbool16_t mask,vuint16m1_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_tum(mask,merge,op1,op2,32); +} + + +vuint16m2_t test___riscv_vwaddu_vx_tum(vbool8_t mask,vuint16m2_t merge,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_tum(mask,merge,op1,op2,32); +} + + +vuint16m4_t test___riscv_vwaddu_vx_tum(vbool4_t mask,vuint16m4_t merge,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_tum(mask,merge,op1,op2,32); +} + + +vuint16m8_t test___riscv_vwaddu_vx_tum(vbool2_t mask,vuint16m8_t merge,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_tum(mask,merge,op1,op2,32); +} + + +vuint32mf2_t test___riscv_vwaddu_vx_tum(vbool64_t mask,vuint32mf2_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_tum(mask,merge,op1,op2,32); +} + + +vuint32m1_t test___riscv_vwaddu_vx_tum(vbool32_t mask,vuint32m1_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_tum(mask,merge,op1,op2,32); +} + + +vuint32m2_t test___riscv_vwaddu_vx_tum(vbool16_t mask,vuint32m2_t merge,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_tum(mask,merge,op1,op2,32); +} + + +vuint32m4_t test___riscv_vwaddu_vx_tum(vbool8_t mask,vuint32m4_t merge,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_tum(mask,merge,op1,op2,32); +} + + +vuint32m8_t test___riscv_vwaddu_vx_tum(vbool4_t mask,vuint32m8_t merge,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_tum(mask,merge,op1,op2,32); +} + + +vuint64m1_t test___riscv_vwaddu_vx_tum(vbool64_t mask,vuint64m1_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_tum(mask,merge,op1,op2,32); +} + + +vuint64m2_t test___riscv_vwaddu_vx_tum(vbool32_t mask,vuint64m2_t merge,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_tum(mask,merge,op1,op2,32); +} + + +vuint64m4_t test___riscv_vwaddu_vx_tum(vbool16_t mask,vuint64m4_t merge,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_tum(mask,merge,op1,op2,32); +} + + +vuint64m8_t test___riscv_vwaddu_vx_tum(vbool8_t mask,vuint64m8_t merge,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_tum(mask,merge,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_vx_tumu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_vx_tumu-1.C new file mode 100644 index 00000000000..0ca440d9cbb --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_vx_tumu-1.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwaddu_vx_tumu(vbool64_t mask,vuint16mf4_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_tumu(mask,merge,op1,op2,vl); +} + + +vuint16mf2_t test___riscv_vwaddu_vx_tumu(vbool32_t mask,vuint16mf2_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_tumu(mask,merge,op1,op2,vl); +} + + +vuint16m1_t test___riscv_vwaddu_vx_tumu(vbool16_t mask,vuint16m1_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_tumu(mask,merge,op1,op2,vl); +} + + +vuint16m2_t test___riscv_vwaddu_vx_tumu(vbool8_t mask,vuint16m2_t merge,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_tumu(mask,merge,op1,op2,vl); +} + + +vuint16m4_t test___riscv_vwaddu_vx_tumu(vbool4_t mask,vuint16m4_t merge,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_tumu(mask,merge,op1,op2,vl); +} + + +vuint16m8_t test___riscv_vwaddu_vx_tumu(vbool2_t mask,vuint16m8_t merge,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_tumu(mask,merge,op1,op2,vl); +} + + +vuint32mf2_t test___riscv_vwaddu_vx_tumu(vbool64_t mask,vuint32mf2_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_tumu(mask,merge,op1,op2,vl); +} + + +vuint32m1_t test___riscv_vwaddu_vx_tumu(vbool32_t mask,vuint32m1_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_tumu(mask,merge,op1,op2,vl); +} + + +vuint32m2_t test___riscv_vwaddu_vx_tumu(vbool16_t mask,vuint32m2_t merge,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_tumu(mask,merge,op1,op2,vl); +} + + +vuint32m4_t test___riscv_vwaddu_vx_tumu(vbool8_t mask,vuint32m4_t merge,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_tumu(mask,merge,op1,op2,vl); +} + + +vuint32m8_t test___riscv_vwaddu_vx_tumu(vbool4_t mask,vuint32m8_t merge,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_tumu(mask,merge,op1,op2,vl); +} + + +vuint64m1_t test___riscv_vwaddu_vx_tumu(vbool64_t mask,vuint64m1_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_tumu(mask,merge,op1,op2,vl); +} + + +vuint64m2_t test___riscv_vwaddu_vx_tumu(vbool32_t mask,vuint64m2_t merge,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_tumu(mask,merge,op1,op2,vl); +} + + +vuint64m4_t test___riscv_vwaddu_vx_tumu(vbool16_t mask,vuint64m4_t merge,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_tumu(mask,merge,op1,op2,vl); +} + + +vuint64m8_t test___riscv_vwaddu_vx_tumu(vbool8_t mask,vuint64m8_t merge,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_tumu(mask,merge,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_vx_tumu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_vx_tumu-2.C new file mode 100644 index 00000000000..ca6733915a3 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_vx_tumu-2.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwaddu_vx_tumu(vbool64_t mask,vuint16mf4_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_tumu(mask,merge,op1,op2,31); +} + + +vuint16mf2_t test___riscv_vwaddu_vx_tumu(vbool32_t mask,vuint16mf2_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_tumu(mask,merge,op1,op2,31); +} + + +vuint16m1_t test___riscv_vwaddu_vx_tumu(vbool16_t mask,vuint16m1_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_tumu(mask,merge,op1,op2,31); +} + + +vuint16m2_t test___riscv_vwaddu_vx_tumu(vbool8_t mask,vuint16m2_t merge,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_tumu(mask,merge,op1,op2,31); +} + + +vuint16m4_t test___riscv_vwaddu_vx_tumu(vbool4_t mask,vuint16m4_t merge,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_tumu(mask,merge,op1,op2,31); +} + + +vuint16m8_t test___riscv_vwaddu_vx_tumu(vbool2_t mask,vuint16m8_t merge,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_tumu(mask,merge,op1,op2,31); +} + + +vuint32mf2_t test___riscv_vwaddu_vx_tumu(vbool64_t mask,vuint32mf2_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_tumu(mask,merge,op1,op2,31); +} + + +vuint32m1_t test___riscv_vwaddu_vx_tumu(vbool32_t mask,vuint32m1_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_tumu(mask,merge,op1,op2,31); +} + + +vuint32m2_t test___riscv_vwaddu_vx_tumu(vbool16_t mask,vuint32m2_t merge,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_tumu(mask,merge,op1,op2,31); +} + + +vuint32m4_t test___riscv_vwaddu_vx_tumu(vbool8_t mask,vuint32m4_t merge,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_tumu(mask,merge,op1,op2,31); +} + + +vuint32m8_t test___riscv_vwaddu_vx_tumu(vbool4_t mask,vuint32m8_t merge,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_tumu(mask,merge,op1,op2,31); +} + + +vuint64m1_t test___riscv_vwaddu_vx_tumu(vbool64_t mask,vuint64m1_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_tumu(mask,merge,op1,op2,31); +} + + +vuint64m2_t test___riscv_vwaddu_vx_tumu(vbool32_t mask,vuint64m2_t merge,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_tumu(mask,merge,op1,op2,31); +} + + +vuint64m4_t test___riscv_vwaddu_vx_tumu(vbool16_t mask,vuint64m4_t merge,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_tumu(mask,merge,op1,op2,31); +} + + +vuint64m8_t test___riscv_vwaddu_vx_tumu(vbool8_t mask,vuint64m8_t merge,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_tumu(mask,merge,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*mu\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*mu\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*mu\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*mu\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*mu\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*mu\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*mu\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*mu\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*mu\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*mu\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*mu\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*mu\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*mu\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*mu\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*mu\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_vx_tumu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_vx_tumu-3.C new file mode 100644 index 00000000000..6babdb1d7df --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_vx_tumu-3.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwaddu_vx_tumu(vbool64_t mask,vuint16mf4_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_tumu(mask,merge,op1,op2,32); +} + + +vuint16mf2_t test___riscv_vwaddu_vx_tumu(vbool32_t mask,vuint16mf2_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_tumu(mask,merge,op1,op2,32); +} + + +vuint16m1_t test___riscv_vwaddu_vx_tumu(vbool16_t mask,vuint16m1_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_tumu(mask,merge,op1,op2,32); +} + + +vuint16m2_t test___riscv_vwaddu_vx_tumu(vbool8_t mask,vuint16m2_t merge,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_tumu(mask,merge,op1,op2,32); +} + + +vuint16m4_t test___riscv_vwaddu_vx_tumu(vbool4_t mask,vuint16m4_t merge,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_tumu(mask,merge,op1,op2,32); +} + + +vuint16m8_t test___riscv_vwaddu_vx_tumu(vbool2_t mask,vuint16m8_t merge,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_tumu(mask,merge,op1,op2,32); +} + + +vuint32mf2_t test___riscv_vwaddu_vx_tumu(vbool64_t mask,vuint32mf2_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_tumu(mask,merge,op1,op2,32); +} + + +vuint32m1_t test___riscv_vwaddu_vx_tumu(vbool32_t mask,vuint32m1_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_tumu(mask,merge,op1,op2,32); +} + + +vuint32m2_t test___riscv_vwaddu_vx_tumu(vbool16_t mask,vuint32m2_t merge,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_tumu(mask,merge,op1,op2,32); +} + + +vuint32m4_t test___riscv_vwaddu_vx_tumu(vbool8_t mask,vuint32m4_t merge,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_tumu(mask,merge,op1,op2,32); +} + + +vuint32m8_t test___riscv_vwaddu_vx_tumu(vbool4_t mask,vuint32m8_t merge,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_tumu(mask,merge,op1,op2,32); +} + + +vuint64m1_t test___riscv_vwaddu_vx_tumu(vbool64_t mask,vuint64m1_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_tumu(mask,merge,op1,op2,32); +} + + +vuint64m2_t test___riscv_vwaddu_vx_tumu(vbool32_t mask,vuint64m2_t merge,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_tumu(mask,merge,op1,op2,32); +} + + +vuint64m4_t test___riscv_vwaddu_vx_tumu(vbool16_t mask,vuint64m4_t merge,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_tumu(mask,merge,op1,op2,32); +} + + +vuint64m8_t test___riscv_vwaddu_vx_tumu(vbool8_t mask,vuint64m8_t merge,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_tumu(mask,merge,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */