RISC-V: Add vwsub.v C++ API tests

Message ID 20230207064426.43100-1-juzhe.zhong@rivai.ai
State Committed
Commit c95bc128c05dc2a8ce9cef9e6764b58cf907635f
Headers
Series RISC-V: Add vwsub.v C++ API tests |

Commit Message

钟居哲 Feb. 7, 2023, 6:44 a.m. UTC
  From: Ju-Zhe Zhong <juzhe.zhong@rivai.ai>

gcc/testsuite/ChangeLog:

        * g++.target/riscv/rvv/base/vwsub_vv-1.C: New test.
        * g++.target/riscv/rvv/base/vwsub_vv-2.C: New test.
        * g++.target/riscv/rvv/base/vwsub_vv-3.C: New test.
        * g++.target/riscv/rvv/base/vwsub_vv_mu-1.C: New test.
        * g++.target/riscv/rvv/base/vwsub_vv_mu-2.C: New test.
        * g++.target/riscv/rvv/base/vwsub_vv_mu-3.C: New test.
        * g++.target/riscv/rvv/base/vwsub_vv_tu-1.C: New test.
        * g++.target/riscv/rvv/base/vwsub_vv_tu-2.C: New test.
        * g++.target/riscv/rvv/base/vwsub_vv_tu-3.C: New test.
        * g++.target/riscv/rvv/base/vwsub_vv_tum-1.C: New test.
        * g++.target/riscv/rvv/base/vwsub_vv_tum-2.C: New test.
        * g++.target/riscv/rvv/base/vwsub_vv_tum-3.C: New test.
        * g++.target/riscv/rvv/base/vwsub_vv_tumu-1.C: New test.
        * g++.target/riscv/rvv/base/vwsub_vv_tumu-2.C: New test.
        * g++.target/riscv/rvv/base/vwsub_vv_tumu-3.C: New test.
        * g++.target/riscv/rvv/base/vwsub_vx-1.C: New test.
        * g++.target/riscv/rvv/base/vwsub_vx-2.C: New test.
        * g++.target/riscv/rvv/base/vwsub_vx-3.C: New test.
        * g++.target/riscv/rvv/base/vwsub_vx_mu-1.C: New test.
        * g++.target/riscv/rvv/base/vwsub_vx_mu-2.C: New test.
        * g++.target/riscv/rvv/base/vwsub_vx_mu-3.C: New test.
        * g++.target/riscv/rvv/base/vwsub_vx_tu-1.C: New test.
        * g++.target/riscv/rvv/base/vwsub_vx_tu-2.C: New test.
        * g++.target/riscv/rvv/base/vwsub_vx_tu-3.C: New test.
        * g++.target/riscv/rvv/base/vwsub_vx_tum-1.C: New test.
        * g++.target/riscv/rvv/base/vwsub_vx_tum-2.C: New test.
        * g++.target/riscv/rvv/base/vwsub_vx_tum-3.C: New test.
        * g++.target/riscv/rvv/base/vwsub_vx_tumu-1.C: New test.
        * g++.target/riscv/rvv/base/vwsub_vx_tumu-2.C: New test.
        * g++.target/riscv/rvv/base/vwsub_vx_tumu-3.C: New test.

---
 .../g++.target/riscv/rvv/base/vwsub_vv-1.C    | 216 ++++++++++++++++++
 .../g++.target/riscv/rvv/base/vwsub_vv-2.C    | 216 ++++++++++++++++++
 .../g++.target/riscv/rvv/base/vwsub_vv-3.C    | 216 ++++++++++++++++++
 .../g++.target/riscv/rvv/base/vwsub_vv_mu-1.C | 111 +++++++++
 .../g++.target/riscv/rvv/base/vwsub_vv_mu-2.C | 111 +++++++++
 .../g++.target/riscv/rvv/base/vwsub_vv_mu-3.C | 111 +++++++++
 .../g++.target/riscv/rvv/base/vwsub_vv_tu-1.C | 111 +++++++++
 .../g++.target/riscv/rvv/base/vwsub_vv_tu-2.C | 111 +++++++++
 .../g++.target/riscv/rvv/base/vwsub_vv_tu-3.C | 111 +++++++++
 .../riscv/rvv/base/vwsub_vv_tum-1.C           | 111 +++++++++
 .../riscv/rvv/base/vwsub_vv_tum-2.C           | 111 +++++++++
 .../riscv/rvv/base/vwsub_vv_tum-3.C           | 111 +++++++++
 .../riscv/rvv/base/vwsub_vv_tumu-1.C          | 111 +++++++++
 .../riscv/rvv/base/vwsub_vv_tumu-2.C          | 111 +++++++++
 .../riscv/rvv/base/vwsub_vv_tumu-3.C          | 111 +++++++++
 .../g++.target/riscv/rvv/base/vwsub_vx-1.C    | 216 ++++++++++++++++++
 .../g++.target/riscv/rvv/base/vwsub_vx-2.C    | 216 ++++++++++++++++++
 .../g++.target/riscv/rvv/base/vwsub_vx-3.C    | 216 ++++++++++++++++++
 .../g++.target/riscv/rvv/base/vwsub_vx_mu-1.C | 111 +++++++++
 .../g++.target/riscv/rvv/base/vwsub_vx_mu-2.C | 111 +++++++++
 .../g++.target/riscv/rvv/base/vwsub_vx_mu-3.C | 111 +++++++++
 .../g++.target/riscv/rvv/base/vwsub_vx_tu-1.C | 111 +++++++++
 .../g++.target/riscv/rvv/base/vwsub_vx_tu-2.C | 111 +++++++++
 .../g++.target/riscv/rvv/base/vwsub_vx_tu-3.C | 111 +++++++++
 .../riscv/rvv/base/vwsub_vx_tum-1.C           | 111 +++++++++
 .../riscv/rvv/base/vwsub_vx_tum-2.C           | 111 +++++++++
 .../riscv/rvv/base/vwsub_vx_tum-3.C           | 111 +++++++++
 .../riscv/rvv/base/vwsub_vx_tumu-1.C          | 111 +++++++++
 .../riscv/rvv/base/vwsub_vx_tumu-2.C          | 111 +++++++++
 .../riscv/rvv/base/vwsub_vx_tumu-3.C          | 111 +++++++++
 30 files changed, 3960 insertions(+)
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsub_vv-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsub_vv-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsub_vv-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsub_vv_mu-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsub_vv_mu-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsub_vv_mu-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsub_vv_tu-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsub_vv_tu-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsub_vv_tu-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsub_vv_tum-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsub_vv_tum-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsub_vv_tum-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsub_vv_tumu-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsub_vv_tumu-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsub_vv_tumu-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsub_vx-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsub_vx-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsub_vx-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsub_vx_mu-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsub_vx_mu-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsub_vx_mu-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsub_vx_tu-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsub_vx_tu-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsub_vx_tu-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsub_vx_tum-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsub_vx_tum-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsub_vx_tum-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsub_vx_tumu-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsub_vx_tumu-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsub_vx_tumu-3.C
  

Patch

diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_vv-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_vv-1.C
new file mode 100644
index 00000000000..2f3cb84a6a7
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_vv-1.C
@@ -0,0 +1,216 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwsub_vv(vint8mf8_t op1,vint8mf8_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv(op1,op2,vl);
+}
+
+
+vint16mf2_t test___riscv_vwsub_vv(vint8mf4_t op1,vint8mf4_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv(op1,op2,vl);
+}
+
+
+vint16m1_t test___riscv_vwsub_vv(vint8mf2_t op1,vint8mf2_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv(op1,op2,vl);
+}
+
+
+vint16m2_t test___riscv_vwsub_vv(vint8m1_t op1,vint8m1_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv(op1,op2,vl);
+}
+
+
+vint16m4_t test___riscv_vwsub_vv(vint8m2_t op1,vint8m2_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv(op1,op2,vl);
+}
+
+
+vint16m8_t test___riscv_vwsub_vv(vint8m4_t op1,vint8m4_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv(op1,op2,vl);
+}
+
+
+vint32mf2_t test___riscv_vwsub_vv(vint16mf4_t op1,vint16mf4_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv(op1,op2,vl);
+}
+
+
+vint32m1_t test___riscv_vwsub_vv(vint16mf2_t op1,vint16mf2_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv(op1,op2,vl);
+}
+
+
+vint32m2_t test___riscv_vwsub_vv(vint16m1_t op1,vint16m1_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv(op1,op2,vl);
+}
+
+
+vint32m4_t test___riscv_vwsub_vv(vint16m2_t op1,vint16m2_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv(op1,op2,vl);
+}
+
+
+vint32m8_t test___riscv_vwsub_vv(vint16m4_t op1,vint16m4_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv(op1,op2,vl);
+}
+
+
+vint64m1_t test___riscv_vwsub_vv(vint32mf2_t op1,vint32mf2_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv(op1,op2,vl);
+}
+
+
+vint64m2_t test___riscv_vwsub_vv(vint32m1_t op1,vint32m1_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv(op1,op2,vl);
+}
+
+
+vint64m4_t test___riscv_vwsub_vv(vint32m2_t op1,vint32m2_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv(op1,op2,vl);
+}
+
+
+vint64m8_t test___riscv_vwsub_vv(vint32m4_t op1,vint32m4_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv(op1,op2,vl);
+}
+
+
+vint16mf4_t test___riscv_vwsub_vv(vbool64_t mask,vint8mf8_t op1,vint8mf8_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv(mask,op1,op2,vl);
+}
+
+
+vint16mf2_t test___riscv_vwsub_vv(vbool32_t mask,vint8mf4_t op1,vint8mf4_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv(mask,op1,op2,vl);
+}
+
+
+vint16m1_t test___riscv_vwsub_vv(vbool16_t mask,vint8mf2_t op1,vint8mf2_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv(mask,op1,op2,vl);
+}
+
+
+vint16m2_t test___riscv_vwsub_vv(vbool8_t mask,vint8m1_t op1,vint8m1_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv(mask,op1,op2,vl);
+}
+
+
+vint16m4_t test___riscv_vwsub_vv(vbool4_t mask,vint8m2_t op1,vint8m2_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv(mask,op1,op2,vl);
+}
+
+
+vint16m8_t test___riscv_vwsub_vv(vbool2_t mask,vint8m4_t op1,vint8m4_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv(mask,op1,op2,vl);
+}
+
+
+vint32mf2_t test___riscv_vwsub_vv(vbool64_t mask,vint16mf4_t op1,vint16mf4_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv(mask,op1,op2,vl);
+}
+
+
+vint32m1_t test___riscv_vwsub_vv(vbool32_t mask,vint16mf2_t op1,vint16mf2_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv(mask,op1,op2,vl);
+}
+
+
+vint32m2_t test___riscv_vwsub_vv(vbool16_t mask,vint16m1_t op1,vint16m1_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv(mask,op1,op2,vl);
+}
+
+
+vint32m4_t test___riscv_vwsub_vv(vbool8_t mask,vint16m2_t op1,vint16m2_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv(mask,op1,op2,vl);
+}
+
+
+vint32m8_t test___riscv_vwsub_vv(vbool4_t mask,vint16m4_t op1,vint16m4_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv(mask,op1,op2,vl);
+}
+
+
+vint64m1_t test___riscv_vwsub_vv(vbool64_t mask,vint32mf2_t op1,vint32mf2_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv(mask,op1,op2,vl);
+}
+
+
+vint64m2_t test___riscv_vwsub_vv(vbool32_t mask,vint32m1_t op1,vint32m1_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv(mask,op1,op2,vl);
+}
+
+
+vint64m4_t test___riscv_vwsub_vv(vbool16_t mask,vint32m2_t op1,vint32m2_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv(mask,op1,op2,vl);
+}
+
+
+vint64m8_t test___riscv_vwsub_vv(vbool8_t mask,vint32m4_t op1,vint32m4_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv(mask,op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_vv-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_vv-2.C
new file mode 100644
index 00000000000..08b59892d4c
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_vv-2.C
@@ -0,0 +1,216 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwsub_vv(vint8mf8_t op1,vint8mf8_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv(op1,op2,31);
+}
+
+
+vint16mf2_t test___riscv_vwsub_vv(vint8mf4_t op1,vint8mf4_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv(op1,op2,31);
+}
+
+
+vint16m1_t test___riscv_vwsub_vv(vint8mf2_t op1,vint8mf2_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv(op1,op2,31);
+}
+
+
+vint16m2_t test___riscv_vwsub_vv(vint8m1_t op1,vint8m1_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv(op1,op2,31);
+}
+
+
+vint16m4_t test___riscv_vwsub_vv(vint8m2_t op1,vint8m2_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv(op1,op2,31);
+}
+
+
+vint16m8_t test___riscv_vwsub_vv(vint8m4_t op1,vint8m4_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv(op1,op2,31);
+}
+
+
+vint32mf2_t test___riscv_vwsub_vv(vint16mf4_t op1,vint16mf4_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv(op1,op2,31);
+}
+
+
+vint32m1_t test___riscv_vwsub_vv(vint16mf2_t op1,vint16mf2_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv(op1,op2,31);
+}
+
+
+vint32m2_t test___riscv_vwsub_vv(vint16m1_t op1,vint16m1_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv(op1,op2,31);
+}
+
+
+vint32m4_t test___riscv_vwsub_vv(vint16m2_t op1,vint16m2_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv(op1,op2,31);
+}
+
+
+vint32m8_t test___riscv_vwsub_vv(vint16m4_t op1,vint16m4_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv(op1,op2,31);
+}
+
+
+vint64m1_t test___riscv_vwsub_vv(vint32mf2_t op1,vint32mf2_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv(op1,op2,31);
+}
+
+
+vint64m2_t test___riscv_vwsub_vv(vint32m1_t op1,vint32m1_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv(op1,op2,31);
+}
+
+
+vint64m4_t test___riscv_vwsub_vv(vint32m2_t op1,vint32m2_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv(op1,op2,31);
+}
+
+
+vint64m8_t test___riscv_vwsub_vv(vint32m4_t op1,vint32m4_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv(op1,op2,31);
+}
+
+
+vint16mf4_t test___riscv_vwsub_vv(vbool64_t mask,vint8mf8_t op1,vint8mf8_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv(mask,op1,op2,31);
+}
+
+
+vint16mf2_t test___riscv_vwsub_vv(vbool32_t mask,vint8mf4_t op1,vint8mf4_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv(mask,op1,op2,31);
+}
+
+
+vint16m1_t test___riscv_vwsub_vv(vbool16_t mask,vint8mf2_t op1,vint8mf2_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv(mask,op1,op2,31);
+}
+
+
+vint16m2_t test___riscv_vwsub_vv(vbool8_t mask,vint8m1_t op1,vint8m1_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv(mask,op1,op2,31);
+}
+
+
+vint16m4_t test___riscv_vwsub_vv(vbool4_t mask,vint8m2_t op1,vint8m2_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv(mask,op1,op2,31);
+}
+
+
+vint16m8_t test___riscv_vwsub_vv(vbool2_t mask,vint8m4_t op1,vint8m4_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv(mask,op1,op2,31);
+}
+
+
+vint32mf2_t test___riscv_vwsub_vv(vbool64_t mask,vint16mf4_t op1,vint16mf4_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv(mask,op1,op2,31);
+}
+
+
+vint32m1_t test___riscv_vwsub_vv(vbool32_t mask,vint16mf2_t op1,vint16mf2_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv(mask,op1,op2,31);
+}
+
+
+vint32m2_t test___riscv_vwsub_vv(vbool16_t mask,vint16m1_t op1,vint16m1_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv(mask,op1,op2,31);
+}
+
+
+vint32m4_t test___riscv_vwsub_vv(vbool8_t mask,vint16m2_t op1,vint16m2_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv(mask,op1,op2,31);
+}
+
+
+vint32m8_t test___riscv_vwsub_vv(vbool4_t mask,vint16m4_t op1,vint16m4_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv(mask,op1,op2,31);
+}
+
+
+vint64m1_t test___riscv_vwsub_vv(vbool64_t mask,vint32mf2_t op1,vint32mf2_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv(mask,op1,op2,31);
+}
+
+
+vint64m2_t test___riscv_vwsub_vv(vbool32_t mask,vint32m1_t op1,vint32m1_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv(mask,op1,op2,31);
+}
+
+
+vint64m4_t test___riscv_vwsub_vv(vbool16_t mask,vint32m2_t op1,vint32m2_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv(mask,op1,op2,31);
+}
+
+
+vint64m8_t test___riscv_vwsub_vv(vbool8_t mask,vint32m4_t op1,vint32m4_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv(mask,op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_vv-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_vv-3.C
new file mode 100644
index 00000000000..5d0fb287e6a
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_vv-3.C
@@ -0,0 +1,216 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwsub_vv(vint8mf8_t op1,vint8mf8_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv(op1,op2,32);
+}
+
+
+vint16mf2_t test___riscv_vwsub_vv(vint8mf4_t op1,vint8mf4_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv(op1,op2,32);
+}
+
+
+vint16m1_t test___riscv_vwsub_vv(vint8mf2_t op1,vint8mf2_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv(op1,op2,32);
+}
+
+
+vint16m2_t test___riscv_vwsub_vv(vint8m1_t op1,vint8m1_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv(op1,op2,32);
+}
+
+
+vint16m4_t test___riscv_vwsub_vv(vint8m2_t op1,vint8m2_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv(op1,op2,32);
+}
+
+
+vint16m8_t test___riscv_vwsub_vv(vint8m4_t op1,vint8m4_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv(op1,op2,32);
+}
+
+
+vint32mf2_t test___riscv_vwsub_vv(vint16mf4_t op1,vint16mf4_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv(op1,op2,32);
+}
+
+
+vint32m1_t test___riscv_vwsub_vv(vint16mf2_t op1,vint16mf2_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv(op1,op2,32);
+}
+
+
+vint32m2_t test___riscv_vwsub_vv(vint16m1_t op1,vint16m1_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv(op1,op2,32);
+}
+
+
+vint32m4_t test___riscv_vwsub_vv(vint16m2_t op1,vint16m2_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv(op1,op2,32);
+}
+
+
+vint32m8_t test___riscv_vwsub_vv(vint16m4_t op1,vint16m4_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv(op1,op2,32);
+}
+
+
+vint64m1_t test___riscv_vwsub_vv(vint32mf2_t op1,vint32mf2_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv(op1,op2,32);
+}
+
+
+vint64m2_t test___riscv_vwsub_vv(vint32m1_t op1,vint32m1_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv(op1,op2,32);
+}
+
+
+vint64m4_t test___riscv_vwsub_vv(vint32m2_t op1,vint32m2_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv(op1,op2,32);
+}
+
+
+vint64m8_t test___riscv_vwsub_vv(vint32m4_t op1,vint32m4_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv(op1,op2,32);
+}
+
+
+vint16mf4_t test___riscv_vwsub_vv(vbool64_t mask,vint8mf8_t op1,vint8mf8_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv(mask,op1,op2,32);
+}
+
+
+vint16mf2_t test___riscv_vwsub_vv(vbool32_t mask,vint8mf4_t op1,vint8mf4_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv(mask,op1,op2,32);
+}
+
+
+vint16m1_t test___riscv_vwsub_vv(vbool16_t mask,vint8mf2_t op1,vint8mf2_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv(mask,op1,op2,32);
+}
+
+
+vint16m2_t test___riscv_vwsub_vv(vbool8_t mask,vint8m1_t op1,vint8m1_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv(mask,op1,op2,32);
+}
+
+
+vint16m4_t test___riscv_vwsub_vv(vbool4_t mask,vint8m2_t op1,vint8m2_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv(mask,op1,op2,32);
+}
+
+
+vint16m8_t test___riscv_vwsub_vv(vbool2_t mask,vint8m4_t op1,vint8m4_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv(mask,op1,op2,32);
+}
+
+
+vint32mf2_t test___riscv_vwsub_vv(vbool64_t mask,vint16mf4_t op1,vint16mf4_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv(mask,op1,op2,32);
+}
+
+
+vint32m1_t test___riscv_vwsub_vv(vbool32_t mask,vint16mf2_t op1,vint16mf2_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv(mask,op1,op2,32);
+}
+
+
+vint32m2_t test___riscv_vwsub_vv(vbool16_t mask,vint16m1_t op1,vint16m1_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv(mask,op1,op2,32);
+}
+
+
+vint32m4_t test___riscv_vwsub_vv(vbool8_t mask,vint16m2_t op1,vint16m2_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv(mask,op1,op2,32);
+}
+
+
+vint32m8_t test___riscv_vwsub_vv(vbool4_t mask,vint16m4_t op1,vint16m4_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv(mask,op1,op2,32);
+}
+
+
+vint64m1_t test___riscv_vwsub_vv(vbool64_t mask,vint32mf2_t op1,vint32mf2_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv(mask,op1,op2,32);
+}
+
+
+vint64m2_t test___riscv_vwsub_vv(vbool32_t mask,vint32m1_t op1,vint32m1_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv(mask,op1,op2,32);
+}
+
+
+vint64m4_t test___riscv_vwsub_vv(vbool16_t mask,vint32m2_t op1,vint32m2_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv(mask,op1,op2,32);
+}
+
+
+vint64m8_t test___riscv_vwsub_vv(vbool8_t mask,vint32m4_t op1,vint32m4_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv(mask,op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_vv_mu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_vv_mu-1.C
new file mode 100644
index 00000000000..a69e51f1b49
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_vv_mu-1.C
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwsub_vv_mu(vbool64_t mask,vint16mf4_t merge,vint8mf8_t op1,vint8mf8_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint16mf2_t test___riscv_vwsub_vv_mu(vbool32_t mask,vint16mf2_t merge,vint8mf4_t op1,vint8mf4_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint16m1_t test___riscv_vwsub_vv_mu(vbool16_t mask,vint16m1_t merge,vint8mf2_t op1,vint8mf2_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint16m2_t test___riscv_vwsub_vv_mu(vbool8_t mask,vint16m2_t merge,vint8m1_t op1,vint8m1_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint16m4_t test___riscv_vwsub_vv_mu(vbool4_t mask,vint16m4_t merge,vint8m2_t op1,vint8m2_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint16m8_t test___riscv_vwsub_vv_mu(vbool2_t mask,vint16m8_t merge,vint8m4_t op1,vint8m4_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint32mf2_t test___riscv_vwsub_vv_mu(vbool64_t mask,vint32mf2_t merge,vint16mf4_t op1,vint16mf4_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint32m1_t test___riscv_vwsub_vv_mu(vbool32_t mask,vint32m1_t merge,vint16mf2_t op1,vint16mf2_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint32m2_t test___riscv_vwsub_vv_mu(vbool16_t mask,vint32m2_t merge,vint16m1_t op1,vint16m1_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint32m4_t test___riscv_vwsub_vv_mu(vbool8_t mask,vint32m4_t merge,vint16m2_t op1,vint16m2_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint32m8_t test___riscv_vwsub_vv_mu(vbool4_t mask,vint32m8_t merge,vint16m4_t op1,vint16m4_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint64m1_t test___riscv_vwsub_vv_mu(vbool64_t mask,vint64m1_t merge,vint32mf2_t op1,vint32mf2_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint64m2_t test___riscv_vwsub_vv_mu(vbool32_t mask,vint64m2_t merge,vint32m1_t op1,vint32m1_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint64m4_t test___riscv_vwsub_vv_mu(vbool16_t mask,vint64m4_t merge,vint32m2_t op1,vint32m2_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint64m8_t test___riscv_vwsub_vv_mu(vbool8_t mask,vint64m8_t merge,vint32m4_t op1,vint32m4_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv_mu(mask,merge,op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_vv_mu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_vv_mu-2.C
new file mode 100644
index 00000000000..d6421a08cfe
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_vv_mu-2.C
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwsub_vv_mu(vbool64_t mask,vint16mf4_t merge,vint8mf8_t op1,vint8mf8_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv_mu(mask,merge,op1,op2,31);
+}
+
+
+vint16mf2_t test___riscv_vwsub_vv_mu(vbool32_t mask,vint16mf2_t merge,vint8mf4_t op1,vint8mf4_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv_mu(mask,merge,op1,op2,31);
+}
+
+
+vint16m1_t test___riscv_vwsub_vv_mu(vbool16_t mask,vint16m1_t merge,vint8mf2_t op1,vint8mf2_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv_mu(mask,merge,op1,op2,31);
+}
+
+
+vint16m2_t test___riscv_vwsub_vv_mu(vbool8_t mask,vint16m2_t merge,vint8m1_t op1,vint8m1_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv_mu(mask,merge,op1,op2,31);
+}
+
+
+vint16m4_t test___riscv_vwsub_vv_mu(vbool4_t mask,vint16m4_t merge,vint8m2_t op1,vint8m2_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv_mu(mask,merge,op1,op2,31);
+}
+
+
+vint16m8_t test___riscv_vwsub_vv_mu(vbool2_t mask,vint16m8_t merge,vint8m4_t op1,vint8m4_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv_mu(mask,merge,op1,op2,31);
+}
+
+
+vint32mf2_t test___riscv_vwsub_vv_mu(vbool64_t mask,vint32mf2_t merge,vint16mf4_t op1,vint16mf4_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv_mu(mask,merge,op1,op2,31);
+}
+
+
+vint32m1_t test___riscv_vwsub_vv_mu(vbool32_t mask,vint32m1_t merge,vint16mf2_t op1,vint16mf2_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv_mu(mask,merge,op1,op2,31);
+}
+
+
+vint32m2_t test___riscv_vwsub_vv_mu(vbool16_t mask,vint32m2_t merge,vint16m1_t op1,vint16m1_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv_mu(mask,merge,op1,op2,31);
+}
+
+
+vint32m4_t test___riscv_vwsub_vv_mu(vbool8_t mask,vint32m4_t merge,vint16m2_t op1,vint16m2_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv_mu(mask,merge,op1,op2,31);
+}
+
+
+vint32m8_t test___riscv_vwsub_vv_mu(vbool4_t mask,vint32m8_t merge,vint16m4_t op1,vint16m4_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv_mu(mask,merge,op1,op2,31);
+}
+
+
+vint64m1_t test___riscv_vwsub_vv_mu(vbool64_t mask,vint64m1_t merge,vint32mf2_t op1,vint32mf2_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv_mu(mask,merge,op1,op2,31);
+}
+
+
+vint64m2_t test___riscv_vwsub_vv_mu(vbool32_t mask,vint64m2_t merge,vint32m1_t op1,vint32m1_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv_mu(mask,merge,op1,op2,31);
+}
+
+
+vint64m4_t test___riscv_vwsub_vv_mu(vbool16_t mask,vint64m4_t merge,vint32m2_t op1,vint32m2_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv_mu(mask,merge,op1,op2,31);
+}
+
+
+vint64m8_t test___riscv_vwsub_vv_mu(vbool8_t mask,vint64m8_t merge,vint32m4_t op1,vint32m4_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv_mu(mask,merge,op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*mu\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*mu\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*mu\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*mu\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*mu\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*mu\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*mu\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*mu\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*mu\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_vv_mu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_vv_mu-3.C
new file mode 100644
index 00000000000..1a5478c1ba6
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_vv_mu-3.C
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwsub_vv_mu(vbool64_t mask,vint16mf4_t merge,vint8mf8_t op1,vint8mf8_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv_mu(mask,merge,op1,op2,32);
+}
+
+
+vint16mf2_t test___riscv_vwsub_vv_mu(vbool32_t mask,vint16mf2_t merge,vint8mf4_t op1,vint8mf4_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv_mu(mask,merge,op1,op2,32);
+}
+
+
+vint16m1_t test___riscv_vwsub_vv_mu(vbool16_t mask,vint16m1_t merge,vint8mf2_t op1,vint8mf2_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv_mu(mask,merge,op1,op2,32);
+}
+
+
+vint16m2_t test___riscv_vwsub_vv_mu(vbool8_t mask,vint16m2_t merge,vint8m1_t op1,vint8m1_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv_mu(mask,merge,op1,op2,32);
+}
+
+
+vint16m4_t test___riscv_vwsub_vv_mu(vbool4_t mask,vint16m4_t merge,vint8m2_t op1,vint8m2_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv_mu(mask,merge,op1,op2,32);
+}
+
+
+vint16m8_t test___riscv_vwsub_vv_mu(vbool2_t mask,vint16m8_t merge,vint8m4_t op1,vint8m4_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv_mu(mask,merge,op1,op2,32);
+}
+
+
+vint32mf2_t test___riscv_vwsub_vv_mu(vbool64_t mask,vint32mf2_t merge,vint16mf4_t op1,vint16mf4_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv_mu(mask,merge,op1,op2,32);
+}
+
+
+vint32m1_t test___riscv_vwsub_vv_mu(vbool32_t mask,vint32m1_t merge,vint16mf2_t op1,vint16mf2_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv_mu(mask,merge,op1,op2,32);
+}
+
+
+vint32m2_t test___riscv_vwsub_vv_mu(vbool16_t mask,vint32m2_t merge,vint16m1_t op1,vint16m1_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv_mu(mask,merge,op1,op2,32);
+}
+
+
+vint32m4_t test___riscv_vwsub_vv_mu(vbool8_t mask,vint32m4_t merge,vint16m2_t op1,vint16m2_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv_mu(mask,merge,op1,op2,32);
+}
+
+
+vint32m8_t test___riscv_vwsub_vv_mu(vbool4_t mask,vint32m8_t merge,vint16m4_t op1,vint16m4_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv_mu(mask,merge,op1,op2,32);
+}
+
+
+vint64m1_t test___riscv_vwsub_vv_mu(vbool64_t mask,vint64m1_t merge,vint32mf2_t op1,vint32mf2_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv_mu(mask,merge,op1,op2,32);
+}
+
+
+vint64m2_t test___riscv_vwsub_vv_mu(vbool32_t mask,vint64m2_t merge,vint32m1_t op1,vint32m1_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv_mu(mask,merge,op1,op2,32);
+}
+
+
+vint64m4_t test___riscv_vwsub_vv_mu(vbool16_t mask,vint64m4_t merge,vint32m2_t op1,vint32m2_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv_mu(mask,merge,op1,op2,32);
+}
+
+
+vint64m8_t test___riscv_vwsub_vv_mu(vbool8_t mask,vint64m8_t merge,vint32m4_t op1,vint32m4_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv_mu(mask,merge,op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_vv_tu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_vv_tu-1.C
new file mode 100644
index 00000000000..56c3b4dfa39
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_vv_tu-1.C
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwsub_vv_tu(vint16mf4_t merge,vint8mf8_t op1,vint8mf8_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv_tu(merge,op1,op2,vl);
+}
+
+
+vint16mf2_t test___riscv_vwsub_vv_tu(vint16mf2_t merge,vint8mf4_t op1,vint8mf4_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv_tu(merge,op1,op2,vl);
+}
+
+
+vint16m1_t test___riscv_vwsub_vv_tu(vint16m1_t merge,vint8mf2_t op1,vint8mf2_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv_tu(merge,op1,op2,vl);
+}
+
+
+vint16m2_t test___riscv_vwsub_vv_tu(vint16m2_t merge,vint8m1_t op1,vint8m1_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv_tu(merge,op1,op2,vl);
+}
+
+
+vint16m4_t test___riscv_vwsub_vv_tu(vint16m4_t merge,vint8m2_t op1,vint8m2_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv_tu(merge,op1,op2,vl);
+}
+
+
+vint16m8_t test___riscv_vwsub_vv_tu(vint16m8_t merge,vint8m4_t op1,vint8m4_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv_tu(merge,op1,op2,vl);
+}
+
+
+vint32mf2_t test___riscv_vwsub_vv_tu(vint32mf2_t merge,vint16mf4_t op1,vint16mf4_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv_tu(merge,op1,op2,vl);
+}
+
+
+vint32m1_t test___riscv_vwsub_vv_tu(vint32m1_t merge,vint16mf2_t op1,vint16mf2_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv_tu(merge,op1,op2,vl);
+}
+
+
+vint32m2_t test___riscv_vwsub_vv_tu(vint32m2_t merge,vint16m1_t op1,vint16m1_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv_tu(merge,op1,op2,vl);
+}
+
+
+vint32m4_t test___riscv_vwsub_vv_tu(vint32m4_t merge,vint16m2_t op1,vint16m2_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv_tu(merge,op1,op2,vl);
+}
+
+
+vint32m8_t test___riscv_vwsub_vv_tu(vint32m8_t merge,vint16m4_t op1,vint16m4_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv_tu(merge,op1,op2,vl);
+}
+
+
+vint64m1_t test___riscv_vwsub_vv_tu(vint64m1_t merge,vint32mf2_t op1,vint32mf2_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv_tu(merge,op1,op2,vl);
+}
+
+
+vint64m2_t test___riscv_vwsub_vv_tu(vint64m2_t merge,vint32m1_t op1,vint32m1_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv_tu(merge,op1,op2,vl);
+}
+
+
+vint64m4_t test___riscv_vwsub_vv_tu(vint64m4_t merge,vint32m2_t op1,vint32m2_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv_tu(merge,op1,op2,vl);
+}
+
+
+vint64m8_t test___riscv_vwsub_vv_tu(vint64m8_t merge,vint32m4_t op1,vint32m4_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv_tu(merge,op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_vv_tu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_vv_tu-2.C
new file mode 100644
index 00000000000..0e328d4ea9b
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_vv_tu-2.C
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwsub_vv_tu(vint16mf4_t merge,vint8mf8_t op1,vint8mf8_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv_tu(merge,op1,op2,31);
+}
+
+
+vint16mf2_t test___riscv_vwsub_vv_tu(vint16mf2_t merge,vint8mf4_t op1,vint8mf4_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv_tu(merge,op1,op2,31);
+}
+
+
+vint16m1_t test___riscv_vwsub_vv_tu(vint16m1_t merge,vint8mf2_t op1,vint8mf2_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv_tu(merge,op1,op2,31);
+}
+
+
+vint16m2_t test___riscv_vwsub_vv_tu(vint16m2_t merge,vint8m1_t op1,vint8m1_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv_tu(merge,op1,op2,31);
+}
+
+
+vint16m4_t test___riscv_vwsub_vv_tu(vint16m4_t merge,vint8m2_t op1,vint8m2_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv_tu(merge,op1,op2,31);
+}
+
+
+vint16m8_t test___riscv_vwsub_vv_tu(vint16m8_t merge,vint8m4_t op1,vint8m4_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv_tu(merge,op1,op2,31);
+}
+
+
+vint32mf2_t test___riscv_vwsub_vv_tu(vint32mf2_t merge,vint16mf4_t op1,vint16mf4_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv_tu(merge,op1,op2,31);
+}
+
+
+vint32m1_t test___riscv_vwsub_vv_tu(vint32m1_t merge,vint16mf2_t op1,vint16mf2_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv_tu(merge,op1,op2,31);
+}
+
+
+vint32m2_t test___riscv_vwsub_vv_tu(vint32m2_t merge,vint16m1_t op1,vint16m1_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv_tu(merge,op1,op2,31);
+}
+
+
+vint32m4_t test___riscv_vwsub_vv_tu(vint32m4_t merge,vint16m2_t op1,vint16m2_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv_tu(merge,op1,op2,31);
+}
+
+
+vint32m8_t test___riscv_vwsub_vv_tu(vint32m8_t merge,vint16m4_t op1,vint16m4_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv_tu(merge,op1,op2,31);
+}
+
+
+vint64m1_t test___riscv_vwsub_vv_tu(vint64m1_t merge,vint32mf2_t op1,vint32mf2_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv_tu(merge,op1,op2,31);
+}
+
+
+vint64m2_t test___riscv_vwsub_vv_tu(vint64m2_t merge,vint32m1_t op1,vint32m1_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv_tu(merge,op1,op2,31);
+}
+
+
+vint64m4_t test___riscv_vwsub_vv_tu(vint64m4_t merge,vint32m2_t op1,vint32m2_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv_tu(merge,op1,op2,31);
+}
+
+
+vint64m8_t test___riscv_vwsub_vv_tu(vint64m8_t merge,vint32m4_t op1,vint32m4_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv_tu(merge,op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_vv_tu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_vv_tu-3.C
new file mode 100644
index 00000000000..54d4262f4e0
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_vv_tu-3.C
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwsub_vv_tu(vint16mf4_t merge,vint8mf8_t op1,vint8mf8_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv_tu(merge,op1,op2,32);
+}
+
+
+vint16mf2_t test___riscv_vwsub_vv_tu(vint16mf2_t merge,vint8mf4_t op1,vint8mf4_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv_tu(merge,op1,op2,32);
+}
+
+
+vint16m1_t test___riscv_vwsub_vv_tu(vint16m1_t merge,vint8mf2_t op1,vint8mf2_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv_tu(merge,op1,op2,32);
+}
+
+
+vint16m2_t test___riscv_vwsub_vv_tu(vint16m2_t merge,vint8m1_t op1,vint8m1_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv_tu(merge,op1,op2,32);
+}
+
+
+vint16m4_t test___riscv_vwsub_vv_tu(vint16m4_t merge,vint8m2_t op1,vint8m2_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv_tu(merge,op1,op2,32);
+}
+
+
+vint16m8_t test___riscv_vwsub_vv_tu(vint16m8_t merge,vint8m4_t op1,vint8m4_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv_tu(merge,op1,op2,32);
+}
+
+
+vint32mf2_t test___riscv_vwsub_vv_tu(vint32mf2_t merge,vint16mf4_t op1,vint16mf4_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv_tu(merge,op1,op2,32);
+}
+
+
+vint32m1_t test___riscv_vwsub_vv_tu(vint32m1_t merge,vint16mf2_t op1,vint16mf2_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv_tu(merge,op1,op2,32);
+}
+
+
+vint32m2_t test___riscv_vwsub_vv_tu(vint32m2_t merge,vint16m1_t op1,vint16m1_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv_tu(merge,op1,op2,32);
+}
+
+
+vint32m4_t test___riscv_vwsub_vv_tu(vint32m4_t merge,vint16m2_t op1,vint16m2_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv_tu(merge,op1,op2,32);
+}
+
+
+vint32m8_t test___riscv_vwsub_vv_tu(vint32m8_t merge,vint16m4_t op1,vint16m4_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv_tu(merge,op1,op2,32);
+}
+
+
+vint64m1_t test___riscv_vwsub_vv_tu(vint64m1_t merge,vint32mf2_t op1,vint32mf2_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv_tu(merge,op1,op2,32);
+}
+
+
+vint64m2_t test___riscv_vwsub_vv_tu(vint64m2_t merge,vint32m1_t op1,vint32m1_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv_tu(merge,op1,op2,32);
+}
+
+
+vint64m4_t test___riscv_vwsub_vv_tu(vint64m4_t merge,vint32m2_t op1,vint32m2_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv_tu(merge,op1,op2,32);
+}
+
+
+vint64m8_t test___riscv_vwsub_vv_tu(vint64m8_t merge,vint32m4_t op1,vint32m4_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv_tu(merge,op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_vv_tum-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_vv_tum-1.C
new file mode 100644
index 00000000000..13ec4b09752
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_vv_tum-1.C
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwsub_vv_tum(vbool64_t mask,vint16mf4_t merge,vint8mf8_t op1,vint8mf8_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint16mf2_t test___riscv_vwsub_vv_tum(vbool32_t mask,vint16mf2_t merge,vint8mf4_t op1,vint8mf4_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint16m1_t test___riscv_vwsub_vv_tum(vbool16_t mask,vint16m1_t merge,vint8mf2_t op1,vint8mf2_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint16m2_t test___riscv_vwsub_vv_tum(vbool8_t mask,vint16m2_t merge,vint8m1_t op1,vint8m1_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint16m4_t test___riscv_vwsub_vv_tum(vbool4_t mask,vint16m4_t merge,vint8m2_t op1,vint8m2_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint16m8_t test___riscv_vwsub_vv_tum(vbool2_t mask,vint16m8_t merge,vint8m4_t op1,vint8m4_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint32mf2_t test___riscv_vwsub_vv_tum(vbool64_t mask,vint32mf2_t merge,vint16mf4_t op1,vint16mf4_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint32m1_t test___riscv_vwsub_vv_tum(vbool32_t mask,vint32m1_t merge,vint16mf2_t op1,vint16mf2_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint32m2_t test___riscv_vwsub_vv_tum(vbool16_t mask,vint32m2_t merge,vint16m1_t op1,vint16m1_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint32m4_t test___riscv_vwsub_vv_tum(vbool8_t mask,vint32m4_t merge,vint16m2_t op1,vint16m2_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint32m8_t test___riscv_vwsub_vv_tum(vbool4_t mask,vint32m8_t merge,vint16m4_t op1,vint16m4_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint64m1_t test___riscv_vwsub_vv_tum(vbool64_t mask,vint64m1_t merge,vint32mf2_t op1,vint32mf2_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint64m2_t test___riscv_vwsub_vv_tum(vbool32_t mask,vint64m2_t merge,vint32m1_t op1,vint32m1_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint64m4_t test___riscv_vwsub_vv_tum(vbool16_t mask,vint64m4_t merge,vint32m2_t op1,vint32m2_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint64m8_t test___riscv_vwsub_vv_tum(vbool8_t mask,vint64m8_t merge,vint32m4_t op1,vint32m4_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv_tum(mask,merge,op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_vv_tum-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_vv_tum-2.C
new file mode 100644
index 00000000000..da0afa937fe
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_vv_tum-2.C
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwsub_vv_tum(vbool64_t mask,vint16mf4_t merge,vint8mf8_t op1,vint8mf8_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv_tum(mask,merge,op1,op2,31);
+}
+
+
+vint16mf2_t test___riscv_vwsub_vv_tum(vbool32_t mask,vint16mf2_t merge,vint8mf4_t op1,vint8mf4_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv_tum(mask,merge,op1,op2,31);
+}
+
+
+vint16m1_t test___riscv_vwsub_vv_tum(vbool16_t mask,vint16m1_t merge,vint8mf2_t op1,vint8mf2_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv_tum(mask,merge,op1,op2,31);
+}
+
+
+vint16m2_t test___riscv_vwsub_vv_tum(vbool8_t mask,vint16m2_t merge,vint8m1_t op1,vint8m1_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv_tum(mask,merge,op1,op2,31);
+}
+
+
+vint16m4_t test___riscv_vwsub_vv_tum(vbool4_t mask,vint16m4_t merge,vint8m2_t op1,vint8m2_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv_tum(mask,merge,op1,op2,31);
+}
+
+
+vint16m8_t test___riscv_vwsub_vv_tum(vbool2_t mask,vint16m8_t merge,vint8m4_t op1,vint8m4_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv_tum(mask,merge,op1,op2,31);
+}
+
+
+vint32mf2_t test___riscv_vwsub_vv_tum(vbool64_t mask,vint32mf2_t merge,vint16mf4_t op1,vint16mf4_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv_tum(mask,merge,op1,op2,31);
+}
+
+
+vint32m1_t test___riscv_vwsub_vv_tum(vbool32_t mask,vint32m1_t merge,vint16mf2_t op1,vint16mf2_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv_tum(mask,merge,op1,op2,31);
+}
+
+
+vint32m2_t test___riscv_vwsub_vv_tum(vbool16_t mask,vint32m2_t merge,vint16m1_t op1,vint16m1_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv_tum(mask,merge,op1,op2,31);
+}
+
+
+vint32m4_t test___riscv_vwsub_vv_tum(vbool8_t mask,vint32m4_t merge,vint16m2_t op1,vint16m2_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv_tum(mask,merge,op1,op2,31);
+}
+
+
+vint32m8_t test___riscv_vwsub_vv_tum(vbool4_t mask,vint32m8_t merge,vint16m4_t op1,vint16m4_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv_tum(mask,merge,op1,op2,31);
+}
+
+
+vint64m1_t test___riscv_vwsub_vv_tum(vbool64_t mask,vint64m1_t merge,vint32mf2_t op1,vint32mf2_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv_tum(mask,merge,op1,op2,31);
+}
+
+
+vint64m2_t test___riscv_vwsub_vv_tum(vbool32_t mask,vint64m2_t merge,vint32m1_t op1,vint32m1_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv_tum(mask,merge,op1,op2,31);
+}
+
+
+vint64m4_t test___riscv_vwsub_vv_tum(vbool16_t mask,vint64m4_t merge,vint32m2_t op1,vint32m2_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv_tum(mask,merge,op1,op2,31);
+}
+
+
+vint64m8_t test___riscv_vwsub_vv_tum(vbool8_t mask,vint64m8_t merge,vint32m4_t op1,vint32m4_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv_tum(mask,merge,op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_vv_tum-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_vv_tum-3.C
new file mode 100644
index 00000000000..158e65c6748
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_vv_tum-3.C
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwsub_vv_tum(vbool64_t mask,vint16mf4_t merge,vint8mf8_t op1,vint8mf8_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv_tum(mask,merge,op1,op2,32);
+}
+
+
+vint16mf2_t test___riscv_vwsub_vv_tum(vbool32_t mask,vint16mf2_t merge,vint8mf4_t op1,vint8mf4_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv_tum(mask,merge,op1,op2,32);
+}
+
+
+vint16m1_t test___riscv_vwsub_vv_tum(vbool16_t mask,vint16m1_t merge,vint8mf2_t op1,vint8mf2_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv_tum(mask,merge,op1,op2,32);
+}
+
+
+vint16m2_t test___riscv_vwsub_vv_tum(vbool8_t mask,vint16m2_t merge,vint8m1_t op1,vint8m1_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv_tum(mask,merge,op1,op2,32);
+}
+
+
+vint16m4_t test___riscv_vwsub_vv_tum(vbool4_t mask,vint16m4_t merge,vint8m2_t op1,vint8m2_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv_tum(mask,merge,op1,op2,32);
+}
+
+
+vint16m8_t test___riscv_vwsub_vv_tum(vbool2_t mask,vint16m8_t merge,vint8m4_t op1,vint8m4_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv_tum(mask,merge,op1,op2,32);
+}
+
+
+vint32mf2_t test___riscv_vwsub_vv_tum(vbool64_t mask,vint32mf2_t merge,vint16mf4_t op1,vint16mf4_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv_tum(mask,merge,op1,op2,32);
+}
+
+
+vint32m1_t test___riscv_vwsub_vv_tum(vbool32_t mask,vint32m1_t merge,vint16mf2_t op1,vint16mf2_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv_tum(mask,merge,op1,op2,32);
+}
+
+
+vint32m2_t test___riscv_vwsub_vv_tum(vbool16_t mask,vint32m2_t merge,vint16m1_t op1,vint16m1_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv_tum(mask,merge,op1,op2,32);
+}
+
+
+vint32m4_t test___riscv_vwsub_vv_tum(vbool8_t mask,vint32m4_t merge,vint16m2_t op1,vint16m2_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv_tum(mask,merge,op1,op2,32);
+}
+
+
+vint32m8_t test___riscv_vwsub_vv_tum(vbool4_t mask,vint32m8_t merge,vint16m4_t op1,vint16m4_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv_tum(mask,merge,op1,op2,32);
+}
+
+
+vint64m1_t test___riscv_vwsub_vv_tum(vbool64_t mask,vint64m1_t merge,vint32mf2_t op1,vint32mf2_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv_tum(mask,merge,op1,op2,32);
+}
+
+
+vint64m2_t test___riscv_vwsub_vv_tum(vbool32_t mask,vint64m2_t merge,vint32m1_t op1,vint32m1_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv_tum(mask,merge,op1,op2,32);
+}
+
+
+vint64m4_t test___riscv_vwsub_vv_tum(vbool16_t mask,vint64m4_t merge,vint32m2_t op1,vint32m2_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv_tum(mask,merge,op1,op2,32);
+}
+
+
+vint64m8_t test___riscv_vwsub_vv_tum(vbool8_t mask,vint64m8_t merge,vint32m4_t op1,vint32m4_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv_tum(mask,merge,op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_vv_tumu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_vv_tumu-1.C
new file mode 100644
index 00000000000..401cfa7619a
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_vv_tumu-1.C
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwsub_vv_tumu(vbool64_t mask,vint16mf4_t merge,vint8mf8_t op1,vint8mf8_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint16mf2_t test___riscv_vwsub_vv_tumu(vbool32_t mask,vint16mf2_t merge,vint8mf4_t op1,vint8mf4_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint16m1_t test___riscv_vwsub_vv_tumu(vbool16_t mask,vint16m1_t merge,vint8mf2_t op1,vint8mf2_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint16m2_t test___riscv_vwsub_vv_tumu(vbool8_t mask,vint16m2_t merge,vint8m1_t op1,vint8m1_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint16m4_t test___riscv_vwsub_vv_tumu(vbool4_t mask,vint16m4_t merge,vint8m2_t op1,vint8m2_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint16m8_t test___riscv_vwsub_vv_tumu(vbool2_t mask,vint16m8_t merge,vint8m4_t op1,vint8m4_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint32mf2_t test___riscv_vwsub_vv_tumu(vbool64_t mask,vint32mf2_t merge,vint16mf4_t op1,vint16mf4_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint32m1_t test___riscv_vwsub_vv_tumu(vbool32_t mask,vint32m1_t merge,vint16mf2_t op1,vint16mf2_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint32m2_t test___riscv_vwsub_vv_tumu(vbool16_t mask,vint32m2_t merge,vint16m1_t op1,vint16m1_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint32m4_t test___riscv_vwsub_vv_tumu(vbool8_t mask,vint32m4_t merge,vint16m2_t op1,vint16m2_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint32m8_t test___riscv_vwsub_vv_tumu(vbool4_t mask,vint32m8_t merge,vint16m4_t op1,vint16m4_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint64m1_t test___riscv_vwsub_vv_tumu(vbool64_t mask,vint64m1_t merge,vint32mf2_t op1,vint32mf2_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint64m2_t test___riscv_vwsub_vv_tumu(vbool32_t mask,vint64m2_t merge,vint32m1_t op1,vint32m1_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint64m4_t test___riscv_vwsub_vv_tumu(vbool16_t mask,vint64m4_t merge,vint32m2_t op1,vint32m2_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint64m8_t test___riscv_vwsub_vv_tumu(vbool8_t mask,vint64m8_t merge,vint32m4_t op1,vint32m4_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv_tumu(mask,merge,op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_vv_tumu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_vv_tumu-2.C
new file mode 100644
index 00000000000..40b6b55dd23
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_vv_tumu-2.C
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwsub_vv_tumu(vbool64_t mask,vint16mf4_t merge,vint8mf8_t op1,vint8mf8_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint16mf2_t test___riscv_vwsub_vv_tumu(vbool32_t mask,vint16mf2_t merge,vint8mf4_t op1,vint8mf4_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint16m1_t test___riscv_vwsub_vv_tumu(vbool16_t mask,vint16m1_t merge,vint8mf2_t op1,vint8mf2_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint16m2_t test___riscv_vwsub_vv_tumu(vbool8_t mask,vint16m2_t merge,vint8m1_t op1,vint8m1_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint16m4_t test___riscv_vwsub_vv_tumu(vbool4_t mask,vint16m4_t merge,vint8m2_t op1,vint8m2_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint16m8_t test___riscv_vwsub_vv_tumu(vbool2_t mask,vint16m8_t merge,vint8m4_t op1,vint8m4_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint32mf2_t test___riscv_vwsub_vv_tumu(vbool64_t mask,vint32mf2_t merge,vint16mf4_t op1,vint16mf4_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint32m1_t test___riscv_vwsub_vv_tumu(vbool32_t mask,vint32m1_t merge,vint16mf2_t op1,vint16mf2_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint32m2_t test___riscv_vwsub_vv_tumu(vbool16_t mask,vint32m2_t merge,vint16m1_t op1,vint16m1_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint32m4_t test___riscv_vwsub_vv_tumu(vbool8_t mask,vint32m4_t merge,vint16m2_t op1,vint16m2_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint32m8_t test___riscv_vwsub_vv_tumu(vbool4_t mask,vint32m8_t merge,vint16m4_t op1,vint16m4_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint64m1_t test___riscv_vwsub_vv_tumu(vbool64_t mask,vint64m1_t merge,vint32mf2_t op1,vint32mf2_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint64m2_t test___riscv_vwsub_vv_tumu(vbool32_t mask,vint64m2_t merge,vint32m1_t op1,vint32m1_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint64m4_t test___riscv_vwsub_vv_tumu(vbool16_t mask,vint64m4_t merge,vint32m2_t op1,vint32m2_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint64m8_t test___riscv_vwsub_vv_tumu(vbool8_t mask,vint64m8_t merge,vint32m4_t op1,vint32m4_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv_tumu(mask,merge,op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*mu\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*mu\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*mu\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*mu\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*mu\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*mu\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*mu\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*mu\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*mu\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*mu\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*mu\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*mu\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*mu\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*mu\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*mu\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_vv_tumu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_vv_tumu-3.C
new file mode 100644
index 00000000000..eaa859ae95b
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_vv_tumu-3.C
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwsub_vv_tumu(vbool64_t mask,vint16mf4_t merge,vint8mf8_t op1,vint8mf8_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint16mf2_t test___riscv_vwsub_vv_tumu(vbool32_t mask,vint16mf2_t merge,vint8mf4_t op1,vint8mf4_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint16m1_t test___riscv_vwsub_vv_tumu(vbool16_t mask,vint16m1_t merge,vint8mf2_t op1,vint8mf2_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint16m2_t test___riscv_vwsub_vv_tumu(vbool8_t mask,vint16m2_t merge,vint8m1_t op1,vint8m1_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint16m4_t test___riscv_vwsub_vv_tumu(vbool4_t mask,vint16m4_t merge,vint8m2_t op1,vint8m2_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint16m8_t test___riscv_vwsub_vv_tumu(vbool2_t mask,vint16m8_t merge,vint8m4_t op1,vint8m4_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint32mf2_t test___riscv_vwsub_vv_tumu(vbool64_t mask,vint32mf2_t merge,vint16mf4_t op1,vint16mf4_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint32m1_t test___riscv_vwsub_vv_tumu(vbool32_t mask,vint32m1_t merge,vint16mf2_t op1,vint16mf2_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint32m2_t test___riscv_vwsub_vv_tumu(vbool16_t mask,vint32m2_t merge,vint16m1_t op1,vint16m1_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint32m4_t test___riscv_vwsub_vv_tumu(vbool8_t mask,vint32m4_t merge,vint16m2_t op1,vint16m2_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint32m8_t test___riscv_vwsub_vv_tumu(vbool4_t mask,vint32m8_t merge,vint16m4_t op1,vint16m4_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint64m1_t test___riscv_vwsub_vv_tumu(vbool64_t mask,vint64m1_t merge,vint32mf2_t op1,vint32mf2_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint64m2_t test___riscv_vwsub_vv_tumu(vbool32_t mask,vint64m2_t merge,vint32m1_t op1,vint32m1_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint64m4_t test___riscv_vwsub_vv_tumu(vbool16_t mask,vint64m4_t merge,vint32m2_t op1,vint32m2_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint64m8_t test___riscv_vwsub_vv_tumu(vbool8_t mask,vint64m8_t merge,vint32m4_t op1,vint32m4_t op2,size_t vl)
+{
+    return __riscv_vwsub_vv_tumu(mask,merge,op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_vx-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_vx-1.C
new file mode 100644
index 00000000000..e4a2c784d96
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_vx-1.C
@@ -0,0 +1,216 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwsub_vx(vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx(op1,op2,vl);
+}
+
+
+vint16mf2_t test___riscv_vwsub_vx(vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx(op1,op2,vl);
+}
+
+
+vint16m1_t test___riscv_vwsub_vx(vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx(op1,op2,vl);
+}
+
+
+vint16m2_t test___riscv_vwsub_vx(vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx(op1,op2,vl);
+}
+
+
+vint16m4_t test___riscv_vwsub_vx(vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx(op1,op2,vl);
+}
+
+
+vint16m8_t test___riscv_vwsub_vx(vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx(op1,op2,vl);
+}
+
+
+vint32mf2_t test___riscv_vwsub_vx(vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx(op1,op2,vl);
+}
+
+
+vint32m1_t test___riscv_vwsub_vx(vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx(op1,op2,vl);
+}
+
+
+vint32m2_t test___riscv_vwsub_vx(vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx(op1,op2,vl);
+}
+
+
+vint32m4_t test___riscv_vwsub_vx(vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx(op1,op2,vl);
+}
+
+
+vint32m8_t test___riscv_vwsub_vx(vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx(op1,op2,vl);
+}
+
+
+vint64m1_t test___riscv_vwsub_vx(vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx(op1,op2,vl);
+}
+
+
+vint64m2_t test___riscv_vwsub_vx(vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx(op1,op2,vl);
+}
+
+
+vint64m4_t test___riscv_vwsub_vx(vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx(op1,op2,vl);
+}
+
+
+vint64m8_t test___riscv_vwsub_vx(vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx(op1,op2,vl);
+}
+
+
+vint16mf4_t test___riscv_vwsub_vx(vbool64_t mask,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx(mask,op1,op2,vl);
+}
+
+
+vint16mf2_t test___riscv_vwsub_vx(vbool32_t mask,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx(mask,op1,op2,vl);
+}
+
+
+vint16m1_t test___riscv_vwsub_vx(vbool16_t mask,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx(mask,op1,op2,vl);
+}
+
+
+vint16m2_t test___riscv_vwsub_vx(vbool8_t mask,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx(mask,op1,op2,vl);
+}
+
+
+vint16m4_t test___riscv_vwsub_vx(vbool4_t mask,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx(mask,op1,op2,vl);
+}
+
+
+vint16m8_t test___riscv_vwsub_vx(vbool2_t mask,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx(mask,op1,op2,vl);
+}
+
+
+vint32mf2_t test___riscv_vwsub_vx(vbool64_t mask,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx(mask,op1,op2,vl);
+}
+
+
+vint32m1_t test___riscv_vwsub_vx(vbool32_t mask,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx(mask,op1,op2,vl);
+}
+
+
+vint32m2_t test___riscv_vwsub_vx(vbool16_t mask,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx(mask,op1,op2,vl);
+}
+
+
+vint32m4_t test___riscv_vwsub_vx(vbool8_t mask,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx(mask,op1,op2,vl);
+}
+
+
+vint32m8_t test___riscv_vwsub_vx(vbool4_t mask,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx(mask,op1,op2,vl);
+}
+
+
+vint64m1_t test___riscv_vwsub_vx(vbool64_t mask,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx(mask,op1,op2,vl);
+}
+
+
+vint64m2_t test___riscv_vwsub_vx(vbool32_t mask,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx(mask,op1,op2,vl);
+}
+
+
+vint64m4_t test___riscv_vwsub_vx(vbool16_t mask,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx(mask,op1,op2,vl);
+}
+
+
+vint64m8_t test___riscv_vwsub_vx(vbool8_t mask,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx(mask,op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_vx-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_vx-2.C
new file mode 100644
index 00000000000..2f3d2351ae2
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_vx-2.C
@@ -0,0 +1,216 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwsub_vx(vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx(op1,op2,31);
+}
+
+
+vint16mf2_t test___riscv_vwsub_vx(vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx(op1,op2,31);
+}
+
+
+vint16m1_t test___riscv_vwsub_vx(vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx(op1,op2,31);
+}
+
+
+vint16m2_t test___riscv_vwsub_vx(vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx(op1,op2,31);
+}
+
+
+vint16m4_t test___riscv_vwsub_vx(vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx(op1,op2,31);
+}
+
+
+vint16m8_t test___riscv_vwsub_vx(vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx(op1,op2,31);
+}
+
+
+vint32mf2_t test___riscv_vwsub_vx(vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx(op1,op2,31);
+}
+
+
+vint32m1_t test___riscv_vwsub_vx(vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx(op1,op2,31);
+}
+
+
+vint32m2_t test___riscv_vwsub_vx(vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx(op1,op2,31);
+}
+
+
+vint32m4_t test___riscv_vwsub_vx(vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx(op1,op2,31);
+}
+
+
+vint32m8_t test___riscv_vwsub_vx(vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx(op1,op2,31);
+}
+
+
+vint64m1_t test___riscv_vwsub_vx(vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx(op1,op2,31);
+}
+
+
+vint64m2_t test___riscv_vwsub_vx(vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx(op1,op2,31);
+}
+
+
+vint64m4_t test___riscv_vwsub_vx(vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx(op1,op2,31);
+}
+
+
+vint64m8_t test___riscv_vwsub_vx(vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx(op1,op2,31);
+}
+
+
+vint16mf4_t test___riscv_vwsub_vx(vbool64_t mask,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx(mask,op1,op2,31);
+}
+
+
+vint16mf2_t test___riscv_vwsub_vx(vbool32_t mask,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx(mask,op1,op2,31);
+}
+
+
+vint16m1_t test___riscv_vwsub_vx(vbool16_t mask,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx(mask,op1,op2,31);
+}
+
+
+vint16m2_t test___riscv_vwsub_vx(vbool8_t mask,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx(mask,op1,op2,31);
+}
+
+
+vint16m4_t test___riscv_vwsub_vx(vbool4_t mask,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx(mask,op1,op2,31);
+}
+
+
+vint16m8_t test___riscv_vwsub_vx(vbool2_t mask,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx(mask,op1,op2,31);
+}
+
+
+vint32mf2_t test___riscv_vwsub_vx(vbool64_t mask,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx(mask,op1,op2,31);
+}
+
+
+vint32m1_t test___riscv_vwsub_vx(vbool32_t mask,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx(mask,op1,op2,31);
+}
+
+
+vint32m2_t test___riscv_vwsub_vx(vbool16_t mask,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx(mask,op1,op2,31);
+}
+
+
+vint32m4_t test___riscv_vwsub_vx(vbool8_t mask,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx(mask,op1,op2,31);
+}
+
+
+vint32m8_t test___riscv_vwsub_vx(vbool4_t mask,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx(mask,op1,op2,31);
+}
+
+
+vint64m1_t test___riscv_vwsub_vx(vbool64_t mask,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx(mask,op1,op2,31);
+}
+
+
+vint64m2_t test___riscv_vwsub_vx(vbool32_t mask,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx(mask,op1,op2,31);
+}
+
+
+vint64m4_t test___riscv_vwsub_vx(vbool16_t mask,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx(mask,op1,op2,31);
+}
+
+
+vint64m8_t test___riscv_vwsub_vx(vbool8_t mask,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx(mask,op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_vx-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_vx-3.C
new file mode 100644
index 00000000000..547801c9fa1
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_vx-3.C
@@ -0,0 +1,216 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwsub_vx(vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx(op1,op2,32);
+}
+
+
+vint16mf2_t test___riscv_vwsub_vx(vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx(op1,op2,32);
+}
+
+
+vint16m1_t test___riscv_vwsub_vx(vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx(op1,op2,32);
+}
+
+
+vint16m2_t test___riscv_vwsub_vx(vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx(op1,op2,32);
+}
+
+
+vint16m4_t test___riscv_vwsub_vx(vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx(op1,op2,32);
+}
+
+
+vint16m8_t test___riscv_vwsub_vx(vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx(op1,op2,32);
+}
+
+
+vint32mf2_t test___riscv_vwsub_vx(vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx(op1,op2,32);
+}
+
+
+vint32m1_t test___riscv_vwsub_vx(vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx(op1,op2,32);
+}
+
+
+vint32m2_t test___riscv_vwsub_vx(vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx(op1,op2,32);
+}
+
+
+vint32m4_t test___riscv_vwsub_vx(vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx(op1,op2,32);
+}
+
+
+vint32m8_t test___riscv_vwsub_vx(vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx(op1,op2,32);
+}
+
+
+vint64m1_t test___riscv_vwsub_vx(vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx(op1,op2,32);
+}
+
+
+vint64m2_t test___riscv_vwsub_vx(vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx(op1,op2,32);
+}
+
+
+vint64m4_t test___riscv_vwsub_vx(vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx(op1,op2,32);
+}
+
+
+vint64m8_t test___riscv_vwsub_vx(vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx(op1,op2,32);
+}
+
+
+vint16mf4_t test___riscv_vwsub_vx(vbool64_t mask,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx(mask,op1,op2,32);
+}
+
+
+vint16mf2_t test___riscv_vwsub_vx(vbool32_t mask,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx(mask,op1,op2,32);
+}
+
+
+vint16m1_t test___riscv_vwsub_vx(vbool16_t mask,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx(mask,op1,op2,32);
+}
+
+
+vint16m2_t test___riscv_vwsub_vx(vbool8_t mask,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx(mask,op1,op2,32);
+}
+
+
+vint16m4_t test___riscv_vwsub_vx(vbool4_t mask,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx(mask,op1,op2,32);
+}
+
+
+vint16m8_t test___riscv_vwsub_vx(vbool2_t mask,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx(mask,op1,op2,32);
+}
+
+
+vint32mf2_t test___riscv_vwsub_vx(vbool64_t mask,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx(mask,op1,op2,32);
+}
+
+
+vint32m1_t test___riscv_vwsub_vx(vbool32_t mask,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx(mask,op1,op2,32);
+}
+
+
+vint32m2_t test___riscv_vwsub_vx(vbool16_t mask,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx(mask,op1,op2,32);
+}
+
+
+vint32m4_t test___riscv_vwsub_vx(vbool8_t mask,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx(mask,op1,op2,32);
+}
+
+
+vint32m8_t test___riscv_vwsub_vx(vbool4_t mask,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx(mask,op1,op2,32);
+}
+
+
+vint64m1_t test___riscv_vwsub_vx(vbool64_t mask,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx(mask,op1,op2,32);
+}
+
+
+vint64m2_t test___riscv_vwsub_vx(vbool32_t mask,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx(mask,op1,op2,32);
+}
+
+
+vint64m4_t test___riscv_vwsub_vx(vbool16_t mask,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx(mask,op1,op2,32);
+}
+
+
+vint64m8_t test___riscv_vwsub_vx(vbool8_t mask,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx(mask,op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_vx_mu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_vx_mu-1.C
new file mode 100644
index 00000000000..83978cebda3
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_vx_mu-1.C
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwsub_vx_mu(vbool64_t mask,vint16mf4_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint16mf2_t test___riscv_vwsub_vx_mu(vbool32_t mask,vint16mf2_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint16m1_t test___riscv_vwsub_vx_mu(vbool16_t mask,vint16m1_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint16m2_t test___riscv_vwsub_vx_mu(vbool8_t mask,vint16m2_t merge,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint16m4_t test___riscv_vwsub_vx_mu(vbool4_t mask,vint16m4_t merge,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint16m8_t test___riscv_vwsub_vx_mu(vbool2_t mask,vint16m8_t merge,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint32mf2_t test___riscv_vwsub_vx_mu(vbool64_t mask,vint32mf2_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint32m1_t test___riscv_vwsub_vx_mu(vbool32_t mask,vint32m1_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint32m2_t test___riscv_vwsub_vx_mu(vbool16_t mask,vint32m2_t merge,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint32m4_t test___riscv_vwsub_vx_mu(vbool8_t mask,vint32m4_t merge,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint32m8_t test___riscv_vwsub_vx_mu(vbool4_t mask,vint32m8_t merge,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint64m1_t test___riscv_vwsub_vx_mu(vbool64_t mask,vint64m1_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint64m2_t test___riscv_vwsub_vx_mu(vbool32_t mask,vint64m2_t merge,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint64m4_t test___riscv_vwsub_vx_mu(vbool16_t mask,vint64m4_t merge,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint64m8_t test___riscv_vwsub_vx_mu(vbool8_t mask,vint64m8_t merge,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx_mu(mask,merge,op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_vx_mu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_vx_mu-2.C
new file mode 100644
index 00000000000..52154c08c86
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_vx_mu-2.C
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwsub_vx_mu(vbool64_t mask,vint16mf4_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx_mu(mask,merge,op1,op2,31);
+}
+
+
+vint16mf2_t test___riscv_vwsub_vx_mu(vbool32_t mask,vint16mf2_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx_mu(mask,merge,op1,op2,31);
+}
+
+
+vint16m1_t test___riscv_vwsub_vx_mu(vbool16_t mask,vint16m1_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx_mu(mask,merge,op1,op2,31);
+}
+
+
+vint16m2_t test___riscv_vwsub_vx_mu(vbool8_t mask,vint16m2_t merge,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx_mu(mask,merge,op1,op2,31);
+}
+
+
+vint16m4_t test___riscv_vwsub_vx_mu(vbool4_t mask,vint16m4_t merge,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx_mu(mask,merge,op1,op2,31);
+}
+
+
+vint16m8_t test___riscv_vwsub_vx_mu(vbool2_t mask,vint16m8_t merge,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx_mu(mask,merge,op1,op2,31);
+}
+
+
+vint32mf2_t test___riscv_vwsub_vx_mu(vbool64_t mask,vint32mf2_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx_mu(mask,merge,op1,op2,31);
+}
+
+
+vint32m1_t test___riscv_vwsub_vx_mu(vbool32_t mask,vint32m1_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx_mu(mask,merge,op1,op2,31);
+}
+
+
+vint32m2_t test___riscv_vwsub_vx_mu(vbool16_t mask,vint32m2_t merge,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx_mu(mask,merge,op1,op2,31);
+}
+
+
+vint32m4_t test___riscv_vwsub_vx_mu(vbool8_t mask,vint32m4_t merge,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx_mu(mask,merge,op1,op2,31);
+}
+
+
+vint32m8_t test___riscv_vwsub_vx_mu(vbool4_t mask,vint32m8_t merge,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx_mu(mask,merge,op1,op2,31);
+}
+
+
+vint64m1_t test___riscv_vwsub_vx_mu(vbool64_t mask,vint64m1_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx_mu(mask,merge,op1,op2,31);
+}
+
+
+vint64m2_t test___riscv_vwsub_vx_mu(vbool32_t mask,vint64m2_t merge,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx_mu(mask,merge,op1,op2,31);
+}
+
+
+vint64m4_t test___riscv_vwsub_vx_mu(vbool16_t mask,vint64m4_t merge,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx_mu(mask,merge,op1,op2,31);
+}
+
+
+vint64m8_t test___riscv_vwsub_vx_mu(vbool8_t mask,vint64m8_t merge,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx_mu(mask,merge,op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*mu\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*mu\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*mu\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*mu\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*mu\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*mu\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*mu\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*mu\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*mu\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_vx_mu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_vx_mu-3.C
new file mode 100644
index 00000000000..13dc7ad42b1
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_vx_mu-3.C
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwsub_vx_mu(vbool64_t mask,vint16mf4_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx_mu(mask,merge,op1,op2,32);
+}
+
+
+vint16mf2_t test___riscv_vwsub_vx_mu(vbool32_t mask,vint16mf2_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx_mu(mask,merge,op1,op2,32);
+}
+
+
+vint16m1_t test___riscv_vwsub_vx_mu(vbool16_t mask,vint16m1_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx_mu(mask,merge,op1,op2,32);
+}
+
+
+vint16m2_t test___riscv_vwsub_vx_mu(vbool8_t mask,vint16m2_t merge,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx_mu(mask,merge,op1,op2,32);
+}
+
+
+vint16m4_t test___riscv_vwsub_vx_mu(vbool4_t mask,vint16m4_t merge,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx_mu(mask,merge,op1,op2,32);
+}
+
+
+vint16m8_t test___riscv_vwsub_vx_mu(vbool2_t mask,vint16m8_t merge,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx_mu(mask,merge,op1,op2,32);
+}
+
+
+vint32mf2_t test___riscv_vwsub_vx_mu(vbool64_t mask,vint32mf2_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx_mu(mask,merge,op1,op2,32);
+}
+
+
+vint32m1_t test___riscv_vwsub_vx_mu(vbool32_t mask,vint32m1_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx_mu(mask,merge,op1,op2,32);
+}
+
+
+vint32m2_t test___riscv_vwsub_vx_mu(vbool16_t mask,vint32m2_t merge,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx_mu(mask,merge,op1,op2,32);
+}
+
+
+vint32m4_t test___riscv_vwsub_vx_mu(vbool8_t mask,vint32m4_t merge,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx_mu(mask,merge,op1,op2,32);
+}
+
+
+vint32m8_t test___riscv_vwsub_vx_mu(vbool4_t mask,vint32m8_t merge,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx_mu(mask,merge,op1,op2,32);
+}
+
+
+vint64m1_t test___riscv_vwsub_vx_mu(vbool64_t mask,vint64m1_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx_mu(mask,merge,op1,op2,32);
+}
+
+
+vint64m2_t test___riscv_vwsub_vx_mu(vbool32_t mask,vint64m2_t merge,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx_mu(mask,merge,op1,op2,32);
+}
+
+
+vint64m4_t test___riscv_vwsub_vx_mu(vbool16_t mask,vint64m4_t merge,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx_mu(mask,merge,op1,op2,32);
+}
+
+
+vint64m8_t test___riscv_vwsub_vx_mu(vbool8_t mask,vint64m8_t merge,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx_mu(mask,merge,op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_vx_tu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_vx_tu-1.C
new file mode 100644
index 00000000000..71063c558de
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_vx_tu-1.C
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwsub_vx_tu(vint16mf4_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx_tu(merge,op1,op2,vl);
+}
+
+
+vint16mf2_t test___riscv_vwsub_vx_tu(vint16mf2_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx_tu(merge,op1,op2,vl);
+}
+
+
+vint16m1_t test___riscv_vwsub_vx_tu(vint16m1_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx_tu(merge,op1,op2,vl);
+}
+
+
+vint16m2_t test___riscv_vwsub_vx_tu(vint16m2_t merge,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx_tu(merge,op1,op2,vl);
+}
+
+
+vint16m4_t test___riscv_vwsub_vx_tu(vint16m4_t merge,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx_tu(merge,op1,op2,vl);
+}
+
+
+vint16m8_t test___riscv_vwsub_vx_tu(vint16m8_t merge,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx_tu(merge,op1,op2,vl);
+}
+
+
+vint32mf2_t test___riscv_vwsub_vx_tu(vint32mf2_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx_tu(merge,op1,op2,vl);
+}
+
+
+vint32m1_t test___riscv_vwsub_vx_tu(vint32m1_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx_tu(merge,op1,op2,vl);
+}
+
+
+vint32m2_t test___riscv_vwsub_vx_tu(vint32m2_t merge,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx_tu(merge,op1,op2,vl);
+}
+
+
+vint32m4_t test___riscv_vwsub_vx_tu(vint32m4_t merge,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx_tu(merge,op1,op2,vl);
+}
+
+
+vint32m8_t test___riscv_vwsub_vx_tu(vint32m8_t merge,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx_tu(merge,op1,op2,vl);
+}
+
+
+vint64m1_t test___riscv_vwsub_vx_tu(vint64m1_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx_tu(merge,op1,op2,vl);
+}
+
+
+vint64m2_t test___riscv_vwsub_vx_tu(vint64m2_t merge,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx_tu(merge,op1,op2,vl);
+}
+
+
+vint64m4_t test___riscv_vwsub_vx_tu(vint64m4_t merge,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx_tu(merge,op1,op2,vl);
+}
+
+
+vint64m8_t test___riscv_vwsub_vx_tu(vint64m8_t merge,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx_tu(merge,op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_vx_tu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_vx_tu-2.C
new file mode 100644
index 00000000000..74becc1ce09
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_vx_tu-2.C
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwsub_vx_tu(vint16mf4_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx_tu(merge,op1,op2,31);
+}
+
+
+vint16mf2_t test___riscv_vwsub_vx_tu(vint16mf2_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx_tu(merge,op1,op2,31);
+}
+
+
+vint16m1_t test___riscv_vwsub_vx_tu(vint16m1_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx_tu(merge,op1,op2,31);
+}
+
+
+vint16m2_t test___riscv_vwsub_vx_tu(vint16m2_t merge,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx_tu(merge,op1,op2,31);
+}
+
+
+vint16m4_t test___riscv_vwsub_vx_tu(vint16m4_t merge,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx_tu(merge,op1,op2,31);
+}
+
+
+vint16m8_t test___riscv_vwsub_vx_tu(vint16m8_t merge,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx_tu(merge,op1,op2,31);
+}
+
+
+vint32mf2_t test___riscv_vwsub_vx_tu(vint32mf2_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx_tu(merge,op1,op2,31);
+}
+
+
+vint32m1_t test___riscv_vwsub_vx_tu(vint32m1_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx_tu(merge,op1,op2,31);
+}
+
+
+vint32m2_t test___riscv_vwsub_vx_tu(vint32m2_t merge,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx_tu(merge,op1,op2,31);
+}
+
+
+vint32m4_t test___riscv_vwsub_vx_tu(vint32m4_t merge,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx_tu(merge,op1,op2,31);
+}
+
+
+vint32m8_t test___riscv_vwsub_vx_tu(vint32m8_t merge,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx_tu(merge,op1,op2,31);
+}
+
+
+vint64m1_t test___riscv_vwsub_vx_tu(vint64m1_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx_tu(merge,op1,op2,31);
+}
+
+
+vint64m2_t test___riscv_vwsub_vx_tu(vint64m2_t merge,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx_tu(merge,op1,op2,31);
+}
+
+
+vint64m4_t test___riscv_vwsub_vx_tu(vint64m4_t merge,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx_tu(merge,op1,op2,31);
+}
+
+
+vint64m8_t test___riscv_vwsub_vx_tu(vint64m8_t merge,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx_tu(merge,op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_vx_tu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_vx_tu-3.C
new file mode 100644
index 00000000000..da809e37bfc
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_vx_tu-3.C
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwsub_vx_tu(vint16mf4_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx_tu(merge,op1,op2,32);
+}
+
+
+vint16mf2_t test___riscv_vwsub_vx_tu(vint16mf2_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx_tu(merge,op1,op2,32);
+}
+
+
+vint16m1_t test___riscv_vwsub_vx_tu(vint16m1_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx_tu(merge,op1,op2,32);
+}
+
+
+vint16m2_t test___riscv_vwsub_vx_tu(vint16m2_t merge,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx_tu(merge,op1,op2,32);
+}
+
+
+vint16m4_t test___riscv_vwsub_vx_tu(vint16m4_t merge,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx_tu(merge,op1,op2,32);
+}
+
+
+vint16m8_t test___riscv_vwsub_vx_tu(vint16m8_t merge,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx_tu(merge,op1,op2,32);
+}
+
+
+vint32mf2_t test___riscv_vwsub_vx_tu(vint32mf2_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx_tu(merge,op1,op2,32);
+}
+
+
+vint32m1_t test___riscv_vwsub_vx_tu(vint32m1_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx_tu(merge,op1,op2,32);
+}
+
+
+vint32m2_t test___riscv_vwsub_vx_tu(vint32m2_t merge,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx_tu(merge,op1,op2,32);
+}
+
+
+vint32m4_t test___riscv_vwsub_vx_tu(vint32m4_t merge,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx_tu(merge,op1,op2,32);
+}
+
+
+vint32m8_t test___riscv_vwsub_vx_tu(vint32m8_t merge,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx_tu(merge,op1,op2,32);
+}
+
+
+vint64m1_t test___riscv_vwsub_vx_tu(vint64m1_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx_tu(merge,op1,op2,32);
+}
+
+
+vint64m2_t test___riscv_vwsub_vx_tu(vint64m2_t merge,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx_tu(merge,op1,op2,32);
+}
+
+
+vint64m4_t test___riscv_vwsub_vx_tu(vint64m4_t merge,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx_tu(merge,op1,op2,32);
+}
+
+
+vint64m8_t test___riscv_vwsub_vx_tu(vint64m8_t merge,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx_tu(merge,op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_vx_tum-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_vx_tum-1.C
new file mode 100644
index 00000000000..9af54e2c7e4
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_vx_tum-1.C
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwsub_vx_tum(vbool64_t mask,vint16mf4_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint16mf2_t test___riscv_vwsub_vx_tum(vbool32_t mask,vint16mf2_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint16m1_t test___riscv_vwsub_vx_tum(vbool16_t mask,vint16m1_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint16m2_t test___riscv_vwsub_vx_tum(vbool8_t mask,vint16m2_t merge,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint16m4_t test___riscv_vwsub_vx_tum(vbool4_t mask,vint16m4_t merge,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint16m8_t test___riscv_vwsub_vx_tum(vbool2_t mask,vint16m8_t merge,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint32mf2_t test___riscv_vwsub_vx_tum(vbool64_t mask,vint32mf2_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint32m1_t test___riscv_vwsub_vx_tum(vbool32_t mask,vint32m1_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint32m2_t test___riscv_vwsub_vx_tum(vbool16_t mask,vint32m2_t merge,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint32m4_t test___riscv_vwsub_vx_tum(vbool8_t mask,vint32m4_t merge,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint32m8_t test___riscv_vwsub_vx_tum(vbool4_t mask,vint32m8_t merge,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint64m1_t test___riscv_vwsub_vx_tum(vbool64_t mask,vint64m1_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint64m2_t test___riscv_vwsub_vx_tum(vbool32_t mask,vint64m2_t merge,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint64m4_t test___riscv_vwsub_vx_tum(vbool16_t mask,vint64m4_t merge,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint64m8_t test___riscv_vwsub_vx_tum(vbool8_t mask,vint64m8_t merge,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx_tum(mask,merge,op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_vx_tum-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_vx_tum-2.C
new file mode 100644
index 00000000000..6f193491b86
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_vx_tum-2.C
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwsub_vx_tum(vbool64_t mask,vint16mf4_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx_tum(mask,merge,op1,op2,31);
+}
+
+
+vint16mf2_t test___riscv_vwsub_vx_tum(vbool32_t mask,vint16mf2_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx_tum(mask,merge,op1,op2,31);
+}
+
+
+vint16m1_t test___riscv_vwsub_vx_tum(vbool16_t mask,vint16m1_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx_tum(mask,merge,op1,op2,31);
+}
+
+
+vint16m2_t test___riscv_vwsub_vx_tum(vbool8_t mask,vint16m2_t merge,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx_tum(mask,merge,op1,op2,31);
+}
+
+
+vint16m4_t test___riscv_vwsub_vx_tum(vbool4_t mask,vint16m4_t merge,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx_tum(mask,merge,op1,op2,31);
+}
+
+
+vint16m8_t test___riscv_vwsub_vx_tum(vbool2_t mask,vint16m8_t merge,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx_tum(mask,merge,op1,op2,31);
+}
+
+
+vint32mf2_t test___riscv_vwsub_vx_tum(vbool64_t mask,vint32mf2_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx_tum(mask,merge,op1,op2,31);
+}
+
+
+vint32m1_t test___riscv_vwsub_vx_tum(vbool32_t mask,vint32m1_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx_tum(mask,merge,op1,op2,31);
+}
+
+
+vint32m2_t test___riscv_vwsub_vx_tum(vbool16_t mask,vint32m2_t merge,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx_tum(mask,merge,op1,op2,31);
+}
+
+
+vint32m4_t test___riscv_vwsub_vx_tum(vbool8_t mask,vint32m4_t merge,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx_tum(mask,merge,op1,op2,31);
+}
+
+
+vint32m8_t test___riscv_vwsub_vx_tum(vbool4_t mask,vint32m8_t merge,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx_tum(mask,merge,op1,op2,31);
+}
+
+
+vint64m1_t test___riscv_vwsub_vx_tum(vbool64_t mask,vint64m1_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx_tum(mask,merge,op1,op2,31);
+}
+
+
+vint64m2_t test___riscv_vwsub_vx_tum(vbool32_t mask,vint64m2_t merge,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx_tum(mask,merge,op1,op2,31);
+}
+
+
+vint64m4_t test___riscv_vwsub_vx_tum(vbool16_t mask,vint64m4_t merge,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx_tum(mask,merge,op1,op2,31);
+}
+
+
+vint64m8_t test___riscv_vwsub_vx_tum(vbool8_t mask,vint64m8_t merge,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx_tum(mask,merge,op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_vx_tum-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_vx_tum-3.C
new file mode 100644
index 00000000000..9a8dee5579a
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_vx_tum-3.C
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwsub_vx_tum(vbool64_t mask,vint16mf4_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx_tum(mask,merge,op1,op2,32);
+}
+
+
+vint16mf2_t test___riscv_vwsub_vx_tum(vbool32_t mask,vint16mf2_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx_tum(mask,merge,op1,op2,32);
+}
+
+
+vint16m1_t test___riscv_vwsub_vx_tum(vbool16_t mask,vint16m1_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx_tum(mask,merge,op1,op2,32);
+}
+
+
+vint16m2_t test___riscv_vwsub_vx_tum(vbool8_t mask,vint16m2_t merge,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx_tum(mask,merge,op1,op2,32);
+}
+
+
+vint16m4_t test___riscv_vwsub_vx_tum(vbool4_t mask,vint16m4_t merge,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx_tum(mask,merge,op1,op2,32);
+}
+
+
+vint16m8_t test___riscv_vwsub_vx_tum(vbool2_t mask,vint16m8_t merge,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx_tum(mask,merge,op1,op2,32);
+}
+
+
+vint32mf2_t test___riscv_vwsub_vx_tum(vbool64_t mask,vint32mf2_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx_tum(mask,merge,op1,op2,32);
+}
+
+
+vint32m1_t test___riscv_vwsub_vx_tum(vbool32_t mask,vint32m1_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx_tum(mask,merge,op1,op2,32);
+}
+
+
+vint32m2_t test___riscv_vwsub_vx_tum(vbool16_t mask,vint32m2_t merge,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx_tum(mask,merge,op1,op2,32);
+}
+
+
+vint32m4_t test___riscv_vwsub_vx_tum(vbool8_t mask,vint32m4_t merge,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx_tum(mask,merge,op1,op2,32);
+}
+
+
+vint32m8_t test___riscv_vwsub_vx_tum(vbool4_t mask,vint32m8_t merge,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx_tum(mask,merge,op1,op2,32);
+}
+
+
+vint64m1_t test___riscv_vwsub_vx_tum(vbool64_t mask,vint64m1_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx_tum(mask,merge,op1,op2,32);
+}
+
+
+vint64m2_t test___riscv_vwsub_vx_tum(vbool32_t mask,vint64m2_t merge,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx_tum(mask,merge,op1,op2,32);
+}
+
+
+vint64m4_t test___riscv_vwsub_vx_tum(vbool16_t mask,vint64m4_t merge,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx_tum(mask,merge,op1,op2,32);
+}
+
+
+vint64m8_t test___riscv_vwsub_vx_tum(vbool8_t mask,vint64m8_t merge,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx_tum(mask,merge,op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_vx_tumu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_vx_tumu-1.C
new file mode 100644
index 00000000000..1df9a1c81ad
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_vx_tumu-1.C
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwsub_vx_tumu(vbool64_t mask,vint16mf4_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint16mf2_t test___riscv_vwsub_vx_tumu(vbool32_t mask,vint16mf2_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint16m1_t test___riscv_vwsub_vx_tumu(vbool16_t mask,vint16m1_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint16m2_t test___riscv_vwsub_vx_tumu(vbool8_t mask,vint16m2_t merge,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint16m4_t test___riscv_vwsub_vx_tumu(vbool4_t mask,vint16m4_t merge,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint16m8_t test___riscv_vwsub_vx_tumu(vbool2_t mask,vint16m8_t merge,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint32mf2_t test___riscv_vwsub_vx_tumu(vbool64_t mask,vint32mf2_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint32m1_t test___riscv_vwsub_vx_tumu(vbool32_t mask,vint32m1_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint32m2_t test___riscv_vwsub_vx_tumu(vbool16_t mask,vint32m2_t merge,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint32m4_t test___riscv_vwsub_vx_tumu(vbool8_t mask,vint32m4_t merge,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint32m8_t test___riscv_vwsub_vx_tumu(vbool4_t mask,vint32m8_t merge,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint64m1_t test___riscv_vwsub_vx_tumu(vbool64_t mask,vint64m1_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint64m2_t test___riscv_vwsub_vx_tumu(vbool32_t mask,vint64m2_t merge,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint64m4_t test___riscv_vwsub_vx_tumu(vbool16_t mask,vint64m4_t merge,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint64m8_t test___riscv_vwsub_vx_tumu(vbool8_t mask,vint64m8_t merge,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx_tumu(mask,merge,op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_vx_tumu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_vx_tumu-2.C
new file mode 100644
index 00000000000..434660d5812
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_vx_tumu-2.C
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwsub_vx_tumu(vbool64_t mask,vint16mf4_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint16mf2_t test___riscv_vwsub_vx_tumu(vbool32_t mask,vint16mf2_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint16m1_t test___riscv_vwsub_vx_tumu(vbool16_t mask,vint16m1_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint16m2_t test___riscv_vwsub_vx_tumu(vbool8_t mask,vint16m2_t merge,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint16m4_t test___riscv_vwsub_vx_tumu(vbool4_t mask,vint16m4_t merge,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint16m8_t test___riscv_vwsub_vx_tumu(vbool2_t mask,vint16m8_t merge,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint32mf2_t test___riscv_vwsub_vx_tumu(vbool64_t mask,vint32mf2_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint32m1_t test___riscv_vwsub_vx_tumu(vbool32_t mask,vint32m1_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint32m2_t test___riscv_vwsub_vx_tumu(vbool16_t mask,vint32m2_t merge,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint32m4_t test___riscv_vwsub_vx_tumu(vbool8_t mask,vint32m4_t merge,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint32m8_t test___riscv_vwsub_vx_tumu(vbool4_t mask,vint32m8_t merge,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint64m1_t test___riscv_vwsub_vx_tumu(vbool64_t mask,vint64m1_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint64m2_t test___riscv_vwsub_vx_tumu(vbool32_t mask,vint64m2_t merge,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint64m4_t test___riscv_vwsub_vx_tumu(vbool16_t mask,vint64m4_t merge,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint64m8_t test___riscv_vwsub_vx_tumu(vbool8_t mask,vint64m8_t merge,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx_tumu(mask,merge,op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*mu\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*mu\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*mu\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*mu\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*mu\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*mu\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*mu\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*mu\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*mu\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*mu\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*mu\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*mu\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*mu\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*mu\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*mu\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_vx_tumu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_vx_tumu-3.C
new file mode 100644
index 00000000000..9e189fb3ca5
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_vx_tumu-3.C
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwsub_vx_tumu(vbool64_t mask,vint16mf4_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint16mf2_t test___riscv_vwsub_vx_tumu(vbool32_t mask,vint16mf2_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint16m1_t test___riscv_vwsub_vx_tumu(vbool16_t mask,vint16m1_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint16m2_t test___riscv_vwsub_vx_tumu(vbool8_t mask,vint16m2_t merge,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint16m4_t test___riscv_vwsub_vx_tumu(vbool4_t mask,vint16m4_t merge,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint16m8_t test___riscv_vwsub_vx_tumu(vbool2_t mask,vint16m8_t merge,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint32mf2_t test___riscv_vwsub_vx_tumu(vbool64_t mask,vint32mf2_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint32m1_t test___riscv_vwsub_vx_tumu(vbool32_t mask,vint32m1_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint32m2_t test___riscv_vwsub_vx_tumu(vbool16_t mask,vint32m2_t merge,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint32m4_t test___riscv_vwsub_vx_tumu(vbool8_t mask,vint32m4_t merge,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint32m8_t test___riscv_vwsub_vx_tumu(vbool4_t mask,vint32m8_t merge,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint64m1_t test___riscv_vwsub_vx_tumu(vbool64_t mask,vint64m1_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint64m2_t test___riscv_vwsub_vx_tumu(vbool32_t mask,vint64m2_t merge,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint64m4_t test___riscv_vwsub_vx_tumu(vbool16_t mask,vint64m4_t merge,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint64m8_t test___riscv_vwsub_vx_tumu(vbool8_t mask,vint64m8_t merge,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vwsub_vx_tumu(mask,merge,op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vwsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */