diff mbox series

RISC-V: Add vwsub.w C++ api TESTS

Message ID 20230207064305.41749-1-juzhe.zhong@rivai.ai
State Committed
Commit b406b86cad2330df2973692ae4d3a2e897cb1de3
Headers
Series RISC-V: Add vwsub.w C++ api TESTS |

Commit Message

juzhe.zhong@rivai.ai Feb. 7, 2023, 6:43 a.m. UTC 
  From: Ju-Zhe Zhong <juzhe.zhong@rivai.ai>

gcc/testsuite/ChangeLog:

        * g++.target/riscv/rvv/base/vwsub_wv-1.C: New test.
        * g++.target/riscv/rvv/base/vwsub_wv-2.C: New test.
        * g++.target/riscv/rvv/base/vwsub_wv-3.C: New test.
        * g++.target/riscv/rvv/base/vwsub_wv_mu-1.C: New test.
        * g++.target/riscv/rvv/base/vwsub_wv_mu-2.C: New test.
        * g++.target/riscv/rvv/base/vwsub_wv_mu-3.C: New test.
        * g++.target/riscv/rvv/base/vwsub_wv_tu-1.C: New test.
        * g++.target/riscv/rvv/base/vwsub_wv_tu-2.C: New test.
        * g++.target/riscv/rvv/base/vwsub_wv_tu-3.C: New test.
        * g++.target/riscv/rvv/base/vwsub_wv_tum-1.C: New test.
        * g++.target/riscv/rvv/base/vwsub_wv_tum-2.C: New test.
        * g++.target/riscv/rvv/base/vwsub_wv_tum-3.C: New test.
        * g++.target/riscv/rvv/base/vwsub_wv_tumu-1.C: New test.
        * g++.target/riscv/rvv/base/vwsub_wv_tumu-2.C: New test.
        * g++.target/riscv/rvv/base/vwsub_wv_tumu-3.C: New test.
        * g++.target/riscv/rvv/base/vwsub_wx-1.C: New test.
        * g++.target/riscv/rvv/base/vwsub_wx-2.C: New test.
        * g++.target/riscv/rvv/base/vwsub_wx-3.C: New test.
        * g++.target/riscv/rvv/base/vwsub_wx_mu-1.C: New test.
        * g++.target/riscv/rvv/base/vwsub_wx_mu-2.C: New test.
        * g++.target/riscv/rvv/base/vwsub_wx_mu-3.C: New test.
        * g++.target/riscv/rvv/base/vwsub_wx_tu-1.C: New test.
        * g++.target/riscv/rvv/base/vwsub_wx_tu-2.C: New test.
        * g++.target/riscv/rvv/base/vwsub_wx_tu-3.C: New test.
        * g++.target/riscv/rvv/base/vwsub_wx_tum-1.C: New test.
        * g++.target/riscv/rvv/base/vwsub_wx_tum-2.C: New test.
        * g++.target/riscv/rvv/base/vwsub_wx_tum-3.C: New test.
        * g++.target/riscv/rvv/base/vwsub_wx_tumu-1.C: New test.
        * g++.target/riscv/rvv/base/vwsub_wx_tumu-2.C: New test.
        * g++.target/riscv/rvv/base/vwsub_wx_tumu-3.C: New test.

---
 .../g++.target/riscv/rvv/base/vwsub_wv-1.C    | 216 ++++++++++++++++++
 .../g++.target/riscv/rvv/base/vwsub_wv-2.C    | 216 ++++++++++++++++++
 .../g++.target/riscv/rvv/base/vwsub_wv-3.C    | 216 ++++++++++++++++++
 .../g++.target/riscv/rvv/base/vwsub_wv_mu-1.C | 111 +++++++++
 .../g++.target/riscv/rvv/base/vwsub_wv_mu-2.C | 111 +++++++++
 .../g++.target/riscv/rvv/base/vwsub_wv_mu-3.C | 111 +++++++++
 .../g++.target/riscv/rvv/base/vwsub_wv_tu-1.C | 111 +++++++++
 .../g++.target/riscv/rvv/base/vwsub_wv_tu-2.C | 111 +++++++++
 .../g++.target/riscv/rvv/base/vwsub_wv_tu-3.C | 111 +++++++++
 .../riscv/rvv/base/vwsub_wv_tum-1.C           | 111 +++++++++
 .../riscv/rvv/base/vwsub_wv_tum-2.C           | 111 +++++++++
 .../riscv/rvv/base/vwsub_wv_tum-3.C           | 111 +++++++++
 .../riscv/rvv/base/vwsub_wv_tumu-1.C          | 111 +++++++++
 .../riscv/rvv/base/vwsub_wv_tumu-2.C          | 111 +++++++++
 .../riscv/rvv/base/vwsub_wv_tumu-3.C          | 111 +++++++++
 .../g++.target/riscv/rvv/base/vwsub_wx-1.C    | 216 ++++++++++++++++++
 .../g++.target/riscv/rvv/base/vwsub_wx-2.C    | 216 ++++++++++++++++++
 .../g++.target/riscv/rvv/base/vwsub_wx-3.C    | 216 ++++++++++++++++++
 .../g++.target/riscv/rvv/base/vwsub_wx_mu-1.C | 111 +++++++++
 .../g++.target/riscv/rvv/base/vwsub_wx_mu-2.C | 111 +++++++++
 .../g++.target/riscv/rvv/base/vwsub_wx_mu-3.C | 111 +++++++++
 .../g++.target/riscv/rvv/base/vwsub_wx_tu-1.C | 111 +++++++++
 .../g++.target/riscv/rvv/base/vwsub_wx_tu-2.C | 111 +++++++++
 .../g++.target/riscv/rvv/base/vwsub_wx_tu-3.C | 111 +++++++++
 .../riscv/rvv/base/vwsub_wx_tum-1.C           | 111 +++++++++
 .../riscv/rvv/base/vwsub_wx_tum-2.C           | 111 +++++++++
 .../riscv/rvv/base/vwsub_wx_tum-3.C           | 111 +++++++++
 .../riscv/rvv/base/vwsub_wx_tumu-1.C          | 111 +++++++++
 .../riscv/rvv/base/vwsub_wx_tumu-2.C          | 111 +++++++++
 .../riscv/rvv/base/vwsub_wx_tumu-3.C          | 111 +++++++++
 30 files changed, 3960 insertions(+)
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wv-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wv-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wv-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wv_mu-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wv_mu-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wv_mu-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wv_tu-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wv_tu-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wv_tu-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wv_tum-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wv_tum-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wv_tum-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wv_tumu-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wv_tumu-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wv_tumu-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wx-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wx-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wx-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wx_mu-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wx_mu-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wx_mu-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wx_tu-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wx_tu-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wx_tu-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wx_tum-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wx_tum-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wx_tum-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wx_tumu-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wx_tumu-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wx_tumu-3.C
diff mbox series

Patch

diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wv-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wv-1.C
new file mode 100644
index 00000000000..73c3f53d8dc
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wv-1.C
@@ -0,0 +1,216 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwsub_wv(vint16mf4_t op1,vint8mf8_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv(op1,op2,vl);
+}
+
+
+vint16mf2_t test___riscv_vwsub_wv(vint16mf2_t op1,vint8mf4_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv(op1,op2,vl);
+}
+
+
+vint16m1_t test___riscv_vwsub_wv(vint16m1_t op1,vint8mf2_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv(op1,op2,vl);
+}
+
+
+vint16m2_t test___riscv_vwsub_wv(vint16m2_t op1,vint8m1_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv(op1,op2,vl);
+}
+
+
+vint16m4_t test___riscv_vwsub_wv(vint16m4_t op1,vint8m2_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv(op1,op2,vl);
+}
+
+
+vint16m8_t test___riscv_vwsub_wv(vint16m8_t op1,vint8m4_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv(op1,op2,vl);
+}
+
+
+vint32mf2_t test___riscv_vwsub_wv(vint32mf2_t op1,vint16mf4_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv(op1,op2,vl);
+}
+
+
+vint32m1_t test___riscv_vwsub_wv(vint32m1_t op1,vint16mf2_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv(op1,op2,vl);
+}
+
+
+vint32m2_t test___riscv_vwsub_wv(vint32m2_t op1,vint16m1_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv(op1,op2,vl);
+}
+
+
+vint32m4_t test___riscv_vwsub_wv(vint32m4_t op1,vint16m2_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv(op1,op2,vl);
+}
+
+
+vint32m8_t test___riscv_vwsub_wv(vint32m8_t op1,vint16m4_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv(op1,op2,vl);
+}
+
+
+vint64m1_t test___riscv_vwsub_wv(vint64m1_t op1,vint32mf2_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv(op1,op2,vl);
+}
+
+
+vint64m2_t test___riscv_vwsub_wv(vint64m2_t op1,vint32m1_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv(op1,op2,vl);
+}
+
+
+vint64m4_t test___riscv_vwsub_wv(vint64m4_t op1,vint32m2_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv(op1,op2,vl);
+}
+
+
+vint64m8_t test___riscv_vwsub_wv(vint64m8_t op1,vint32m4_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv(op1,op2,vl);
+}
+
+
+vint16mf4_t test___riscv_vwsub_wv(vbool64_t mask,vint16mf4_t op1,vint8mf8_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv(mask,op1,op2,vl);
+}
+
+
+vint16mf2_t test___riscv_vwsub_wv(vbool32_t mask,vint16mf2_t op1,vint8mf4_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv(mask,op1,op2,vl);
+}
+
+
+vint16m1_t test___riscv_vwsub_wv(vbool16_t mask,vint16m1_t op1,vint8mf2_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv(mask,op1,op2,vl);
+}
+
+
+vint16m2_t test___riscv_vwsub_wv(vbool8_t mask,vint16m2_t op1,vint8m1_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv(mask,op1,op2,vl);
+}
+
+
+vint16m4_t test___riscv_vwsub_wv(vbool4_t mask,vint16m4_t op1,vint8m2_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv(mask,op1,op2,vl);
+}
+
+
+vint16m8_t test___riscv_vwsub_wv(vbool2_t mask,vint16m8_t op1,vint8m4_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv(mask,op1,op2,vl);
+}
+
+
+vint32mf2_t test___riscv_vwsub_wv(vbool64_t mask,vint32mf2_t op1,vint16mf4_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv(mask,op1,op2,vl);
+}
+
+
+vint32m1_t test___riscv_vwsub_wv(vbool32_t mask,vint32m1_t op1,vint16mf2_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv(mask,op1,op2,vl);
+}
+
+
+vint32m2_t test___riscv_vwsub_wv(vbool16_t mask,vint32m2_t op1,vint16m1_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv(mask,op1,op2,vl);
+}
+
+
+vint32m4_t test___riscv_vwsub_wv(vbool8_t mask,vint32m4_t op1,vint16m2_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv(mask,op1,op2,vl);
+}
+
+
+vint32m8_t test___riscv_vwsub_wv(vbool4_t mask,vint32m8_t op1,vint16m4_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv(mask,op1,op2,vl);
+}
+
+
+vint64m1_t test___riscv_vwsub_wv(vbool64_t mask,vint64m1_t op1,vint32mf2_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv(mask,op1,op2,vl);
+}
+
+
+vint64m2_t test___riscv_vwsub_wv(vbool32_t mask,vint64m2_t op1,vint32m1_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv(mask,op1,op2,vl);
+}
+
+
+vint64m4_t test___riscv_vwsub_wv(vbool16_t mask,vint64m4_t op1,vint32m2_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv(mask,op1,op2,vl);
+}
+
+
+vint64m8_t test___riscv_vwsub_wv(vbool8_t mask,vint64m8_t op1,vint32m4_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv(mask,op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wv-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wv-2.C
new file mode 100644
index 00000000000..1ef2c56fd27
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wv-2.C
@@ -0,0 +1,216 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwsub_wv(vint16mf4_t op1,vint8mf8_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv(op1,op2,31);
+}
+
+
+vint16mf2_t test___riscv_vwsub_wv(vint16mf2_t op1,vint8mf4_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv(op1,op2,31);
+}
+
+
+vint16m1_t test___riscv_vwsub_wv(vint16m1_t op1,vint8mf2_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv(op1,op2,31);
+}
+
+
+vint16m2_t test___riscv_vwsub_wv(vint16m2_t op1,vint8m1_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv(op1,op2,31);
+}
+
+
+vint16m4_t test___riscv_vwsub_wv(vint16m4_t op1,vint8m2_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv(op1,op2,31);
+}
+
+
+vint16m8_t test___riscv_vwsub_wv(vint16m8_t op1,vint8m4_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv(op1,op2,31);
+}
+
+
+vint32mf2_t test___riscv_vwsub_wv(vint32mf2_t op1,vint16mf4_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv(op1,op2,31);
+}
+
+
+vint32m1_t test___riscv_vwsub_wv(vint32m1_t op1,vint16mf2_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv(op1,op2,31);
+}
+
+
+vint32m2_t test___riscv_vwsub_wv(vint32m2_t op1,vint16m1_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv(op1,op2,31);
+}
+
+
+vint32m4_t test___riscv_vwsub_wv(vint32m4_t op1,vint16m2_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv(op1,op2,31);
+}
+
+
+vint32m8_t test___riscv_vwsub_wv(vint32m8_t op1,vint16m4_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv(op1,op2,31);
+}
+
+
+vint64m1_t test___riscv_vwsub_wv(vint64m1_t op1,vint32mf2_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv(op1,op2,31);
+}
+
+
+vint64m2_t test___riscv_vwsub_wv(vint64m2_t op1,vint32m1_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv(op1,op2,31);
+}
+
+
+vint64m4_t test___riscv_vwsub_wv(vint64m4_t op1,vint32m2_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv(op1,op2,31);
+}
+
+
+vint64m8_t test___riscv_vwsub_wv(vint64m8_t op1,vint32m4_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv(op1,op2,31);
+}
+
+
+vint16mf4_t test___riscv_vwsub_wv(vbool64_t mask,vint16mf4_t op1,vint8mf8_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv(mask,op1,op2,31);
+}
+
+
+vint16mf2_t test___riscv_vwsub_wv(vbool32_t mask,vint16mf2_t op1,vint8mf4_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv(mask,op1,op2,31);
+}
+
+
+vint16m1_t test___riscv_vwsub_wv(vbool16_t mask,vint16m1_t op1,vint8mf2_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv(mask,op1,op2,31);
+}
+
+
+vint16m2_t test___riscv_vwsub_wv(vbool8_t mask,vint16m2_t op1,vint8m1_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv(mask,op1,op2,31);
+}
+
+
+vint16m4_t test___riscv_vwsub_wv(vbool4_t mask,vint16m4_t op1,vint8m2_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv(mask,op1,op2,31);
+}
+
+
+vint16m8_t test___riscv_vwsub_wv(vbool2_t mask,vint16m8_t op1,vint8m4_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv(mask,op1,op2,31);
+}
+
+
+vint32mf2_t test___riscv_vwsub_wv(vbool64_t mask,vint32mf2_t op1,vint16mf4_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv(mask,op1,op2,31);
+}
+
+
+vint32m1_t test___riscv_vwsub_wv(vbool32_t mask,vint32m1_t op1,vint16mf2_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv(mask,op1,op2,31);
+}
+
+
+vint32m2_t test___riscv_vwsub_wv(vbool16_t mask,vint32m2_t op1,vint16m1_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv(mask,op1,op2,31);
+}
+
+
+vint32m4_t test___riscv_vwsub_wv(vbool8_t mask,vint32m4_t op1,vint16m2_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv(mask,op1,op2,31);
+}
+
+
+vint32m8_t test___riscv_vwsub_wv(vbool4_t mask,vint32m8_t op1,vint16m4_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv(mask,op1,op2,31);
+}
+
+
+vint64m1_t test___riscv_vwsub_wv(vbool64_t mask,vint64m1_t op1,vint32mf2_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv(mask,op1,op2,31);
+}
+
+
+vint64m2_t test___riscv_vwsub_wv(vbool32_t mask,vint64m2_t op1,vint32m1_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv(mask,op1,op2,31);
+}
+
+
+vint64m4_t test___riscv_vwsub_wv(vbool16_t mask,vint64m4_t op1,vint32m2_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv(mask,op1,op2,31);
+}
+
+
+vint64m8_t test___riscv_vwsub_wv(vbool8_t mask,vint64m8_t op1,vint32m4_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv(mask,op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wv-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wv-3.C
new file mode 100644
index 00000000000..3231000a07f
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wv-3.C
@@ -0,0 +1,216 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwsub_wv(vint16mf4_t op1,vint8mf8_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv(op1,op2,32);
+}
+
+
+vint16mf2_t test___riscv_vwsub_wv(vint16mf2_t op1,vint8mf4_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv(op1,op2,32);
+}
+
+
+vint16m1_t test___riscv_vwsub_wv(vint16m1_t op1,vint8mf2_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv(op1,op2,32);
+}
+
+
+vint16m2_t test___riscv_vwsub_wv(vint16m2_t op1,vint8m1_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv(op1,op2,32);
+}
+
+
+vint16m4_t test___riscv_vwsub_wv(vint16m4_t op1,vint8m2_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv(op1,op2,32);
+}
+
+
+vint16m8_t test___riscv_vwsub_wv(vint16m8_t op1,vint8m4_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv(op1,op2,32);
+}
+
+
+vint32mf2_t test___riscv_vwsub_wv(vint32mf2_t op1,vint16mf4_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv(op1,op2,32);
+}
+
+
+vint32m1_t test___riscv_vwsub_wv(vint32m1_t op1,vint16mf2_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv(op1,op2,32);
+}
+
+
+vint32m2_t test___riscv_vwsub_wv(vint32m2_t op1,vint16m1_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv(op1,op2,32);
+}
+
+
+vint32m4_t test___riscv_vwsub_wv(vint32m4_t op1,vint16m2_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv(op1,op2,32);
+}
+
+
+vint32m8_t test___riscv_vwsub_wv(vint32m8_t op1,vint16m4_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv(op1,op2,32);
+}
+
+
+vint64m1_t test___riscv_vwsub_wv(vint64m1_t op1,vint32mf2_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv(op1,op2,32);
+}
+
+
+vint64m2_t test___riscv_vwsub_wv(vint64m2_t op1,vint32m1_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv(op1,op2,32);
+}
+
+
+vint64m4_t test___riscv_vwsub_wv(vint64m4_t op1,vint32m2_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv(op1,op2,32);
+}
+
+
+vint64m8_t test___riscv_vwsub_wv(vint64m8_t op1,vint32m4_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv(op1,op2,32);
+}
+
+
+vint16mf4_t test___riscv_vwsub_wv(vbool64_t mask,vint16mf4_t op1,vint8mf8_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv(mask,op1,op2,32);
+}
+
+
+vint16mf2_t test___riscv_vwsub_wv(vbool32_t mask,vint16mf2_t op1,vint8mf4_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv(mask,op1,op2,32);
+}
+
+
+vint16m1_t test___riscv_vwsub_wv(vbool16_t mask,vint16m1_t op1,vint8mf2_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv(mask,op1,op2,32);
+}
+
+
+vint16m2_t test___riscv_vwsub_wv(vbool8_t mask,vint16m2_t op1,vint8m1_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv(mask,op1,op2,32);
+}
+
+
+vint16m4_t test___riscv_vwsub_wv(vbool4_t mask,vint16m4_t op1,vint8m2_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv(mask,op1,op2,32);
+}
+
+
+vint16m8_t test___riscv_vwsub_wv(vbool2_t mask,vint16m8_t op1,vint8m4_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv(mask,op1,op2,32);
+}
+
+
+vint32mf2_t test___riscv_vwsub_wv(vbool64_t mask,vint32mf2_t op1,vint16mf4_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv(mask,op1,op2,32);
+}
+
+
+vint32m1_t test___riscv_vwsub_wv(vbool32_t mask,vint32m1_t op1,vint16mf2_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv(mask,op1,op2,32);
+}
+
+
+vint32m2_t test___riscv_vwsub_wv(vbool16_t mask,vint32m2_t op1,vint16m1_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv(mask,op1,op2,32);
+}
+
+
+vint32m4_t test___riscv_vwsub_wv(vbool8_t mask,vint32m4_t op1,vint16m2_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv(mask,op1,op2,32);
+}
+
+
+vint32m8_t test___riscv_vwsub_wv(vbool4_t mask,vint32m8_t op1,vint16m4_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv(mask,op1,op2,32);
+}
+
+
+vint64m1_t test___riscv_vwsub_wv(vbool64_t mask,vint64m1_t op1,vint32mf2_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv(mask,op1,op2,32);
+}
+
+
+vint64m2_t test___riscv_vwsub_wv(vbool32_t mask,vint64m2_t op1,vint32m1_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv(mask,op1,op2,32);
+}
+
+
+vint64m4_t test___riscv_vwsub_wv(vbool16_t mask,vint64m4_t op1,vint32m2_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv(mask,op1,op2,32);
+}
+
+
+vint64m8_t test___riscv_vwsub_wv(vbool8_t mask,vint64m8_t op1,vint32m4_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv(mask,op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wv_mu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wv_mu-1.C
new file mode 100644
index 00000000000..d637d17eb07
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wv_mu-1.C
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwsub_wv_mu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,vint8mf8_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint16mf2_t test___riscv_vwsub_wv_mu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,vint8mf4_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint16m1_t test___riscv_vwsub_wv_mu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,vint8mf2_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint16m2_t test___riscv_vwsub_wv_mu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,vint8m1_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint16m4_t test___riscv_vwsub_wv_mu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,vint8m2_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint16m8_t test___riscv_vwsub_wv_mu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,vint8m4_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint32mf2_t test___riscv_vwsub_wv_mu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,vint16mf4_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint32m1_t test___riscv_vwsub_wv_mu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,vint16mf2_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint32m2_t test___riscv_vwsub_wv_mu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,vint16m1_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint32m4_t test___riscv_vwsub_wv_mu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,vint16m2_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint32m8_t test___riscv_vwsub_wv_mu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,vint16m4_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint64m1_t test___riscv_vwsub_wv_mu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,vint32mf2_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint64m2_t test___riscv_vwsub_wv_mu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,vint32m1_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint64m4_t test___riscv_vwsub_wv_mu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,vint32m2_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint64m8_t test___riscv_vwsub_wv_mu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,vint32m4_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_mu(mask,merge,op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wv_mu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wv_mu-2.C
new file mode 100644
index 00000000000..ef94215b6db
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wv_mu-2.C
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwsub_wv_mu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,vint8mf8_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_mu(mask,merge,op1,op2,31);
+}
+
+
+vint16mf2_t test___riscv_vwsub_wv_mu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,vint8mf4_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_mu(mask,merge,op1,op2,31);
+}
+
+
+vint16m1_t test___riscv_vwsub_wv_mu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,vint8mf2_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_mu(mask,merge,op1,op2,31);
+}
+
+
+vint16m2_t test___riscv_vwsub_wv_mu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,vint8m1_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_mu(mask,merge,op1,op2,31);
+}
+
+
+vint16m4_t test___riscv_vwsub_wv_mu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,vint8m2_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_mu(mask,merge,op1,op2,31);
+}
+
+
+vint16m8_t test___riscv_vwsub_wv_mu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,vint8m4_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_mu(mask,merge,op1,op2,31);
+}
+
+
+vint32mf2_t test___riscv_vwsub_wv_mu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,vint16mf4_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_mu(mask,merge,op1,op2,31);
+}
+
+
+vint32m1_t test___riscv_vwsub_wv_mu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,vint16mf2_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_mu(mask,merge,op1,op2,31);
+}
+
+
+vint32m2_t test___riscv_vwsub_wv_mu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,vint16m1_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_mu(mask,merge,op1,op2,31);
+}
+
+
+vint32m4_t test___riscv_vwsub_wv_mu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,vint16m2_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_mu(mask,merge,op1,op2,31);
+}
+
+
+vint32m8_t test___riscv_vwsub_wv_mu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,vint16m4_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_mu(mask,merge,op1,op2,31);
+}
+
+
+vint64m1_t test___riscv_vwsub_wv_mu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,vint32mf2_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_mu(mask,merge,op1,op2,31);
+}
+
+
+vint64m2_t test___riscv_vwsub_wv_mu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,vint32m1_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_mu(mask,merge,op1,op2,31);
+}
+
+
+vint64m4_t test___riscv_vwsub_wv_mu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,vint32m2_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_mu(mask,merge,op1,op2,31);
+}
+
+
+vint64m8_t test___riscv_vwsub_wv_mu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,vint32m4_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_mu(mask,merge,op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wv_mu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wv_mu-3.C
new file mode 100644
index 00000000000..1c6f91edab7
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wv_mu-3.C
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwsub_wv_mu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,vint8mf8_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_mu(mask,merge,op1,op2,32);
+}
+
+
+vint16mf2_t test___riscv_vwsub_wv_mu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,vint8mf4_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_mu(mask,merge,op1,op2,32);
+}
+
+
+vint16m1_t test___riscv_vwsub_wv_mu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,vint8mf2_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_mu(mask,merge,op1,op2,32);
+}
+
+
+vint16m2_t test___riscv_vwsub_wv_mu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,vint8m1_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_mu(mask,merge,op1,op2,32);
+}
+
+
+vint16m4_t test___riscv_vwsub_wv_mu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,vint8m2_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_mu(mask,merge,op1,op2,32);
+}
+
+
+vint16m8_t test___riscv_vwsub_wv_mu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,vint8m4_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_mu(mask,merge,op1,op2,32);
+}
+
+
+vint32mf2_t test___riscv_vwsub_wv_mu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,vint16mf4_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_mu(mask,merge,op1,op2,32);
+}
+
+
+vint32m1_t test___riscv_vwsub_wv_mu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,vint16mf2_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_mu(mask,merge,op1,op2,32);
+}
+
+
+vint32m2_t test___riscv_vwsub_wv_mu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,vint16m1_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_mu(mask,merge,op1,op2,32);
+}
+
+
+vint32m4_t test___riscv_vwsub_wv_mu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,vint16m2_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_mu(mask,merge,op1,op2,32);
+}
+
+
+vint32m8_t test___riscv_vwsub_wv_mu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,vint16m4_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_mu(mask,merge,op1,op2,32);
+}
+
+
+vint64m1_t test___riscv_vwsub_wv_mu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,vint32mf2_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_mu(mask,merge,op1,op2,32);
+}
+
+
+vint64m2_t test___riscv_vwsub_wv_mu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,vint32m1_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_mu(mask,merge,op1,op2,32);
+}
+
+
+vint64m4_t test___riscv_vwsub_wv_mu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,vint32m2_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_mu(mask,merge,op1,op2,32);
+}
+
+
+vint64m8_t test___riscv_vwsub_wv_mu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,vint32m4_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_mu(mask,merge,op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wv_tu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wv_tu-1.C
new file mode 100644
index 00000000000..d77477e129a
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wv_tu-1.C
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwsub_wv_tu(vint16mf4_t merge,vint16mf4_t op1,vint8mf8_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_tu(merge,op1,op2,vl);
+}
+
+
+vint16mf2_t test___riscv_vwsub_wv_tu(vint16mf2_t merge,vint16mf2_t op1,vint8mf4_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_tu(merge,op1,op2,vl);
+}
+
+
+vint16m1_t test___riscv_vwsub_wv_tu(vint16m1_t merge,vint16m1_t op1,vint8mf2_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_tu(merge,op1,op2,vl);
+}
+
+
+vint16m2_t test___riscv_vwsub_wv_tu(vint16m2_t merge,vint16m2_t op1,vint8m1_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_tu(merge,op1,op2,vl);
+}
+
+
+vint16m4_t test___riscv_vwsub_wv_tu(vint16m4_t merge,vint16m4_t op1,vint8m2_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_tu(merge,op1,op2,vl);
+}
+
+
+vint16m8_t test___riscv_vwsub_wv_tu(vint16m8_t merge,vint16m8_t op1,vint8m4_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_tu(merge,op1,op2,vl);
+}
+
+
+vint32mf2_t test___riscv_vwsub_wv_tu(vint32mf2_t merge,vint32mf2_t op1,vint16mf4_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_tu(merge,op1,op2,vl);
+}
+
+
+vint32m1_t test___riscv_vwsub_wv_tu(vint32m1_t merge,vint32m1_t op1,vint16mf2_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_tu(merge,op1,op2,vl);
+}
+
+
+vint32m2_t test___riscv_vwsub_wv_tu(vint32m2_t merge,vint32m2_t op1,vint16m1_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_tu(merge,op1,op2,vl);
+}
+
+
+vint32m4_t test___riscv_vwsub_wv_tu(vint32m4_t merge,vint32m4_t op1,vint16m2_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_tu(merge,op1,op2,vl);
+}
+
+
+vint32m8_t test___riscv_vwsub_wv_tu(vint32m8_t merge,vint32m8_t op1,vint16m4_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_tu(merge,op1,op2,vl);
+}
+
+
+vint64m1_t test___riscv_vwsub_wv_tu(vint64m1_t merge,vint64m1_t op1,vint32mf2_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_tu(merge,op1,op2,vl);
+}
+
+
+vint64m2_t test___riscv_vwsub_wv_tu(vint64m2_t merge,vint64m2_t op1,vint32m1_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_tu(merge,op1,op2,vl);
+}
+
+
+vint64m4_t test___riscv_vwsub_wv_tu(vint64m4_t merge,vint64m4_t op1,vint32m2_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_tu(merge,op1,op2,vl);
+}
+
+
+vint64m8_t test___riscv_vwsub_wv_tu(vint64m8_t merge,vint64m8_t op1,vint32m4_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_tu(merge,op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wv_tu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wv_tu-2.C
new file mode 100644
index 00000000000..80fe4106ae5
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wv_tu-2.C
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwsub_wv_tu(vint16mf4_t merge,vint16mf4_t op1,vint8mf8_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_tu(merge,op1,op2,31);
+}
+
+
+vint16mf2_t test___riscv_vwsub_wv_tu(vint16mf2_t merge,vint16mf2_t op1,vint8mf4_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_tu(merge,op1,op2,31);
+}
+
+
+vint16m1_t test___riscv_vwsub_wv_tu(vint16m1_t merge,vint16m1_t op1,vint8mf2_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_tu(merge,op1,op2,31);
+}
+
+
+vint16m2_t test___riscv_vwsub_wv_tu(vint16m2_t merge,vint16m2_t op1,vint8m1_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_tu(merge,op1,op2,31);
+}
+
+
+vint16m4_t test___riscv_vwsub_wv_tu(vint16m4_t merge,vint16m4_t op1,vint8m2_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_tu(merge,op1,op2,31);
+}
+
+
+vint16m8_t test___riscv_vwsub_wv_tu(vint16m8_t merge,vint16m8_t op1,vint8m4_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_tu(merge,op1,op2,31);
+}
+
+
+vint32mf2_t test___riscv_vwsub_wv_tu(vint32mf2_t merge,vint32mf2_t op1,vint16mf4_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_tu(merge,op1,op2,31);
+}
+
+
+vint32m1_t test___riscv_vwsub_wv_tu(vint32m1_t merge,vint32m1_t op1,vint16mf2_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_tu(merge,op1,op2,31);
+}
+
+
+vint32m2_t test___riscv_vwsub_wv_tu(vint32m2_t merge,vint32m2_t op1,vint16m1_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_tu(merge,op1,op2,31);
+}
+
+
+vint32m4_t test___riscv_vwsub_wv_tu(vint32m4_t merge,vint32m4_t op1,vint16m2_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_tu(merge,op1,op2,31);
+}
+
+
+vint32m8_t test___riscv_vwsub_wv_tu(vint32m8_t merge,vint32m8_t op1,vint16m4_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_tu(merge,op1,op2,31);
+}
+
+
+vint64m1_t test___riscv_vwsub_wv_tu(vint64m1_t merge,vint64m1_t op1,vint32mf2_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_tu(merge,op1,op2,31);
+}
+
+
+vint64m2_t test___riscv_vwsub_wv_tu(vint64m2_t merge,vint64m2_t op1,vint32m1_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_tu(merge,op1,op2,31);
+}
+
+
+vint64m4_t test___riscv_vwsub_wv_tu(vint64m4_t merge,vint64m4_t op1,vint32m2_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_tu(merge,op1,op2,31);
+}
+
+
+vint64m8_t test___riscv_vwsub_wv_tu(vint64m8_t merge,vint64m8_t op1,vint32m4_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_tu(merge,op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wv_tu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wv_tu-3.C
new file mode 100644
index 00000000000..d557f91de59
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wv_tu-3.C
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwsub_wv_tu(vint16mf4_t merge,vint16mf4_t op1,vint8mf8_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_tu(merge,op1,op2,32);
+}
+
+
+vint16mf2_t test___riscv_vwsub_wv_tu(vint16mf2_t merge,vint16mf2_t op1,vint8mf4_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_tu(merge,op1,op2,32);
+}
+
+
+vint16m1_t test___riscv_vwsub_wv_tu(vint16m1_t merge,vint16m1_t op1,vint8mf2_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_tu(merge,op1,op2,32);
+}
+
+
+vint16m2_t test___riscv_vwsub_wv_tu(vint16m2_t merge,vint16m2_t op1,vint8m1_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_tu(merge,op1,op2,32);
+}
+
+
+vint16m4_t test___riscv_vwsub_wv_tu(vint16m4_t merge,vint16m4_t op1,vint8m2_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_tu(merge,op1,op2,32);
+}
+
+
+vint16m8_t test___riscv_vwsub_wv_tu(vint16m8_t merge,vint16m8_t op1,vint8m4_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_tu(merge,op1,op2,32);
+}
+
+
+vint32mf2_t test___riscv_vwsub_wv_tu(vint32mf2_t merge,vint32mf2_t op1,vint16mf4_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_tu(merge,op1,op2,32);
+}
+
+
+vint32m1_t test___riscv_vwsub_wv_tu(vint32m1_t merge,vint32m1_t op1,vint16mf2_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_tu(merge,op1,op2,32);
+}
+
+
+vint32m2_t test___riscv_vwsub_wv_tu(vint32m2_t merge,vint32m2_t op1,vint16m1_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_tu(merge,op1,op2,32);
+}
+
+
+vint32m4_t test___riscv_vwsub_wv_tu(vint32m4_t merge,vint32m4_t op1,vint16m2_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_tu(merge,op1,op2,32);
+}
+
+
+vint32m8_t test___riscv_vwsub_wv_tu(vint32m8_t merge,vint32m8_t op1,vint16m4_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_tu(merge,op1,op2,32);
+}
+
+
+vint64m1_t test___riscv_vwsub_wv_tu(vint64m1_t merge,vint64m1_t op1,vint32mf2_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_tu(merge,op1,op2,32);
+}
+
+
+vint64m2_t test___riscv_vwsub_wv_tu(vint64m2_t merge,vint64m2_t op1,vint32m1_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_tu(merge,op1,op2,32);
+}
+
+
+vint64m4_t test___riscv_vwsub_wv_tu(vint64m4_t merge,vint64m4_t op1,vint32m2_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_tu(merge,op1,op2,32);
+}
+
+
+vint64m8_t test___riscv_vwsub_wv_tu(vint64m8_t merge,vint64m8_t op1,vint32m4_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_tu(merge,op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wv_tum-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wv_tum-1.C
new file mode 100644
index 00000000000..74591889ac2
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wv_tum-1.C
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwsub_wv_tum(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,vint8mf8_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint16mf2_t test___riscv_vwsub_wv_tum(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,vint8mf4_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint16m1_t test___riscv_vwsub_wv_tum(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,vint8mf2_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint16m2_t test___riscv_vwsub_wv_tum(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,vint8m1_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint16m4_t test___riscv_vwsub_wv_tum(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,vint8m2_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint16m8_t test___riscv_vwsub_wv_tum(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,vint8m4_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint32mf2_t test___riscv_vwsub_wv_tum(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,vint16mf4_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint32m1_t test___riscv_vwsub_wv_tum(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,vint16mf2_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint32m2_t test___riscv_vwsub_wv_tum(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,vint16m1_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint32m4_t test___riscv_vwsub_wv_tum(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,vint16m2_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint32m8_t test___riscv_vwsub_wv_tum(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,vint16m4_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint64m1_t test___riscv_vwsub_wv_tum(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,vint32mf2_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint64m2_t test___riscv_vwsub_wv_tum(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,vint32m1_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint64m4_t test___riscv_vwsub_wv_tum(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,vint32m2_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint64m8_t test___riscv_vwsub_wv_tum(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,vint32m4_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_tum(mask,merge,op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wv_tum-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wv_tum-2.C
new file mode 100644
index 00000000000..e3e9340a6aa
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wv_tum-2.C
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwsub_wv_tum(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,vint8mf8_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_tum(mask,merge,op1,op2,31);
+}
+
+
+vint16mf2_t test___riscv_vwsub_wv_tum(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,vint8mf4_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_tum(mask,merge,op1,op2,31);
+}
+
+
+vint16m1_t test___riscv_vwsub_wv_tum(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,vint8mf2_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_tum(mask,merge,op1,op2,31);
+}
+
+
+vint16m2_t test___riscv_vwsub_wv_tum(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,vint8m1_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_tum(mask,merge,op1,op2,31);
+}
+
+
+vint16m4_t test___riscv_vwsub_wv_tum(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,vint8m2_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_tum(mask,merge,op1,op2,31);
+}
+
+
+vint16m8_t test___riscv_vwsub_wv_tum(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,vint8m4_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_tum(mask,merge,op1,op2,31);
+}
+
+
+vint32mf2_t test___riscv_vwsub_wv_tum(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,vint16mf4_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_tum(mask,merge,op1,op2,31);
+}
+
+
+vint32m1_t test___riscv_vwsub_wv_tum(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,vint16mf2_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_tum(mask,merge,op1,op2,31);
+}
+
+
+vint32m2_t test___riscv_vwsub_wv_tum(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,vint16m1_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_tum(mask,merge,op1,op2,31);
+}
+
+
+vint32m4_t test___riscv_vwsub_wv_tum(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,vint16m2_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_tum(mask,merge,op1,op2,31);
+}
+
+
+vint32m8_t test___riscv_vwsub_wv_tum(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,vint16m4_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_tum(mask,merge,op1,op2,31);
+}
+
+
+vint64m1_t test___riscv_vwsub_wv_tum(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,vint32mf2_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_tum(mask,merge,op1,op2,31);
+}
+
+
+vint64m2_t test___riscv_vwsub_wv_tum(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,vint32m1_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_tum(mask,merge,op1,op2,31);
+}
+
+
+vint64m4_t test___riscv_vwsub_wv_tum(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,vint32m2_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_tum(mask,merge,op1,op2,31);
+}
+
+
+vint64m8_t test___riscv_vwsub_wv_tum(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,vint32m4_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_tum(mask,merge,op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wv_tum-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wv_tum-3.C
new file mode 100644
index 00000000000..41f134f14e5
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wv_tum-3.C
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwsub_wv_tum(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,vint8mf8_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_tum(mask,merge,op1,op2,32);
+}
+
+
+vint16mf2_t test___riscv_vwsub_wv_tum(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,vint8mf4_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_tum(mask,merge,op1,op2,32);
+}
+
+
+vint16m1_t test___riscv_vwsub_wv_tum(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,vint8mf2_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_tum(mask,merge,op1,op2,32);
+}
+
+
+vint16m2_t test___riscv_vwsub_wv_tum(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,vint8m1_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_tum(mask,merge,op1,op2,32);
+}
+
+
+vint16m4_t test___riscv_vwsub_wv_tum(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,vint8m2_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_tum(mask,merge,op1,op2,32);
+}
+
+
+vint16m8_t test___riscv_vwsub_wv_tum(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,vint8m4_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_tum(mask,merge,op1,op2,32);
+}
+
+
+vint32mf2_t test___riscv_vwsub_wv_tum(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,vint16mf4_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_tum(mask,merge,op1,op2,32);
+}
+
+
+vint32m1_t test___riscv_vwsub_wv_tum(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,vint16mf2_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_tum(mask,merge,op1,op2,32);
+}
+
+
+vint32m2_t test___riscv_vwsub_wv_tum(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,vint16m1_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_tum(mask,merge,op1,op2,32);
+}
+
+
+vint32m4_t test___riscv_vwsub_wv_tum(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,vint16m2_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_tum(mask,merge,op1,op2,32);
+}
+
+
+vint32m8_t test___riscv_vwsub_wv_tum(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,vint16m4_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_tum(mask,merge,op1,op2,32);
+}
+
+
+vint64m1_t test___riscv_vwsub_wv_tum(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,vint32mf2_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_tum(mask,merge,op1,op2,32);
+}
+
+
+vint64m2_t test___riscv_vwsub_wv_tum(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,vint32m1_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_tum(mask,merge,op1,op2,32);
+}
+
+
+vint64m4_t test___riscv_vwsub_wv_tum(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,vint32m2_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_tum(mask,merge,op1,op2,32);
+}
+
+
+vint64m8_t test___riscv_vwsub_wv_tum(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,vint32m4_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_tum(mask,merge,op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wv_tumu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wv_tumu-1.C
new file mode 100644
index 00000000000..aee6c23342e
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wv_tumu-1.C
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwsub_wv_tumu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,vint8mf8_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint16mf2_t test___riscv_vwsub_wv_tumu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,vint8mf4_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint16m1_t test___riscv_vwsub_wv_tumu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,vint8mf2_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint16m2_t test___riscv_vwsub_wv_tumu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,vint8m1_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint16m4_t test___riscv_vwsub_wv_tumu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,vint8m2_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint16m8_t test___riscv_vwsub_wv_tumu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,vint8m4_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint32mf2_t test___riscv_vwsub_wv_tumu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,vint16mf4_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint32m1_t test___riscv_vwsub_wv_tumu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,vint16mf2_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint32m2_t test___riscv_vwsub_wv_tumu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,vint16m1_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint32m4_t test___riscv_vwsub_wv_tumu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,vint16m2_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint32m8_t test___riscv_vwsub_wv_tumu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,vint16m4_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint64m1_t test___riscv_vwsub_wv_tumu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,vint32mf2_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint64m2_t test___riscv_vwsub_wv_tumu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,vint32m1_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint64m4_t test___riscv_vwsub_wv_tumu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,vint32m2_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint64m8_t test___riscv_vwsub_wv_tumu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,vint32m4_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_tumu(mask,merge,op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wv_tumu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wv_tumu-2.C
new file mode 100644
index 00000000000..c9e833a65a4
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wv_tumu-2.C
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwsub_wv_tumu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,vint8mf8_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint16mf2_t test___riscv_vwsub_wv_tumu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,vint8mf4_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint16m1_t test___riscv_vwsub_wv_tumu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,vint8mf2_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint16m2_t test___riscv_vwsub_wv_tumu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,vint8m1_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint16m4_t test___riscv_vwsub_wv_tumu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,vint8m2_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint16m8_t test___riscv_vwsub_wv_tumu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,vint8m4_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint32mf2_t test___riscv_vwsub_wv_tumu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,vint16mf4_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint32m1_t test___riscv_vwsub_wv_tumu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,vint16mf2_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint32m2_t test___riscv_vwsub_wv_tumu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,vint16m1_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint32m4_t test___riscv_vwsub_wv_tumu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,vint16m2_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint32m8_t test___riscv_vwsub_wv_tumu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,vint16m4_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint64m1_t test___riscv_vwsub_wv_tumu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,vint32mf2_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint64m2_t test___riscv_vwsub_wv_tumu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,vint32m1_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint64m4_t test___riscv_vwsub_wv_tumu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,vint32m2_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint64m8_t test___riscv_vwsub_wv_tumu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,vint32m4_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_tumu(mask,merge,op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wv_tumu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wv_tumu-3.C
new file mode 100644
index 00000000000..02d72987c3b
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wv_tumu-3.C
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwsub_wv_tumu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,vint8mf8_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint16mf2_t test___riscv_vwsub_wv_tumu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,vint8mf4_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint16m1_t test___riscv_vwsub_wv_tumu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,vint8mf2_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint16m2_t test___riscv_vwsub_wv_tumu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,vint8m1_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint16m4_t test___riscv_vwsub_wv_tumu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,vint8m2_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint16m8_t test___riscv_vwsub_wv_tumu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,vint8m4_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint32mf2_t test___riscv_vwsub_wv_tumu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,vint16mf4_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint32m1_t test___riscv_vwsub_wv_tumu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,vint16mf2_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint32m2_t test___riscv_vwsub_wv_tumu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,vint16m1_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint32m4_t test___riscv_vwsub_wv_tumu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,vint16m2_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint32m8_t test___riscv_vwsub_wv_tumu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,vint16m4_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint64m1_t test___riscv_vwsub_wv_tumu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,vint32mf2_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint64m2_t test___riscv_vwsub_wv_tumu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,vint32m1_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint64m4_t test___riscv_vwsub_wv_tumu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,vint32m2_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint64m8_t test___riscv_vwsub_wv_tumu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,vint32m4_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_tumu(mask,merge,op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wx-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wx-1.C
new file mode 100644
index 00000000000..2a09333658e
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wx-1.C
@@ -0,0 +1,216 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwsub_wx(vint16mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx(op1,0xAA,vl);
+}
+
+
+vint16mf2_t test___riscv_vwsub_wx(vint16mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx(op1,0xAA,vl);
+}
+
+
+vint16m1_t test___riscv_vwsub_wx(vint16m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx(op1,0xAA,vl);
+}
+
+
+vint16m2_t test___riscv_vwsub_wx(vint16m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx(op1,0xAA,vl);
+}
+
+
+vint16m4_t test___riscv_vwsub_wx(vint16m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx(op1,0xAA,vl);
+}
+
+
+vint16m8_t test___riscv_vwsub_wx(vint16m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx(op1,0xAA,vl);
+}
+
+
+vint32mf2_t test___riscv_vwsub_wx(vint32mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx(op1,0xAA,vl);
+}
+
+
+vint32m1_t test___riscv_vwsub_wx(vint32m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx(op1,0xAA,vl);
+}
+
+
+vint32m2_t test___riscv_vwsub_wx(vint32m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx(op1,0xAA,vl);
+}
+
+
+vint32m4_t test___riscv_vwsub_wx(vint32m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx(op1,0xAA,vl);
+}
+
+
+vint32m8_t test___riscv_vwsub_wx(vint32m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx(op1,0xAA,vl);
+}
+
+
+vint64m1_t test___riscv_vwsub_wx(vint64m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx(op1,0xAA,vl);
+}
+
+
+vint64m2_t test___riscv_vwsub_wx(vint64m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx(op1,0xAA,vl);
+}
+
+
+vint64m4_t test___riscv_vwsub_wx(vint64m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx(op1,0xAA,vl);
+}
+
+
+vint64m8_t test___riscv_vwsub_wx(vint64m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx(op1,0xAA,vl);
+}
+
+
+vint16mf4_t test___riscv_vwsub_wx(vbool64_t mask,vint16mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx(mask,op1,0xAA,vl);
+}
+
+
+vint16mf2_t test___riscv_vwsub_wx(vbool32_t mask,vint16mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx(mask,op1,0xAA,vl);
+}
+
+
+vint16m1_t test___riscv_vwsub_wx(vbool16_t mask,vint16m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx(mask,op1,0xAA,vl);
+}
+
+
+vint16m2_t test___riscv_vwsub_wx(vbool8_t mask,vint16m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx(mask,op1,0xAA,vl);
+}
+
+
+vint16m4_t test___riscv_vwsub_wx(vbool4_t mask,vint16m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx(mask,op1,0xAA,vl);
+}
+
+
+vint16m8_t test___riscv_vwsub_wx(vbool2_t mask,vint16m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx(mask,op1,0xAA,vl);
+}
+
+
+vint32mf2_t test___riscv_vwsub_wx(vbool64_t mask,vint32mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx(mask,op1,0xAA,vl);
+}
+
+
+vint32m1_t test___riscv_vwsub_wx(vbool32_t mask,vint32m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx(mask,op1,0xAA,vl);
+}
+
+
+vint32m2_t test___riscv_vwsub_wx(vbool16_t mask,vint32m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx(mask,op1,0xAA,vl);
+}
+
+
+vint32m4_t test___riscv_vwsub_wx(vbool8_t mask,vint32m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx(mask,op1,0xAA,vl);
+}
+
+
+vint32m8_t test___riscv_vwsub_wx(vbool4_t mask,vint32m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx(mask,op1,0xAA,vl);
+}
+
+
+vint64m1_t test___riscv_vwsub_wx(vbool64_t mask,vint64m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx(mask,op1,0xAA,vl);
+}
+
+
+vint64m2_t test___riscv_vwsub_wx(vbool32_t mask,vint64m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx(mask,op1,0xAA,vl);
+}
+
+
+vint64m4_t test___riscv_vwsub_wx(vbool16_t mask,vint64m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx(mask,op1,0xAA,vl);
+}
+
+
+vint64m8_t test___riscv_vwsub_wx(vbool8_t mask,vint64m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx(mask,op1,0xAA,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wx-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wx-2.C
new file mode 100644
index 00000000000..d223690df53
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wx-2.C
@@ -0,0 +1,216 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwsub_wx(vint16mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx(op1,0xAA,31);
+}
+
+
+vint16mf2_t test___riscv_vwsub_wx(vint16mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx(op1,0xAA,31);
+}
+
+
+vint16m1_t test___riscv_vwsub_wx(vint16m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx(op1,0xAA,31);
+}
+
+
+vint16m2_t test___riscv_vwsub_wx(vint16m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx(op1,0xAA,31);
+}
+
+
+vint16m4_t test___riscv_vwsub_wx(vint16m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx(op1,0xAA,31);
+}
+
+
+vint16m8_t test___riscv_vwsub_wx(vint16m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx(op1,0xAA,31);
+}
+
+
+vint32mf2_t test___riscv_vwsub_wx(vint32mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx(op1,0xAA,31);
+}
+
+
+vint32m1_t test___riscv_vwsub_wx(vint32m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx(op1,0xAA,31);
+}
+
+
+vint32m2_t test___riscv_vwsub_wx(vint32m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx(op1,0xAA,31);
+}
+
+
+vint32m4_t test___riscv_vwsub_wx(vint32m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx(op1,0xAA,31);
+}
+
+
+vint32m8_t test___riscv_vwsub_wx(vint32m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx(op1,0xAA,31);
+}
+
+
+vint64m1_t test___riscv_vwsub_wx(vint64m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx(op1,0xAA,31);
+}
+
+
+vint64m2_t test___riscv_vwsub_wx(vint64m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx(op1,0xAA,31);
+}
+
+
+vint64m4_t test___riscv_vwsub_wx(vint64m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx(op1,0xAA,31);
+}
+
+
+vint64m8_t test___riscv_vwsub_wx(vint64m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx(op1,0xAA,31);
+}
+
+
+vint16mf4_t test___riscv_vwsub_wx(vbool64_t mask,vint16mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx(mask,op1,0xAA,31);
+}
+
+
+vint16mf2_t test___riscv_vwsub_wx(vbool32_t mask,vint16mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx(mask,op1,0xAA,31);
+}
+
+
+vint16m1_t test___riscv_vwsub_wx(vbool16_t mask,vint16m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx(mask,op1,0xAA,31);
+}
+
+
+vint16m2_t test___riscv_vwsub_wx(vbool8_t mask,vint16m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx(mask,op1,0xAA,31);
+}
+
+
+vint16m4_t test___riscv_vwsub_wx(vbool4_t mask,vint16m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx(mask,op1,0xAA,31);
+}
+
+
+vint16m8_t test___riscv_vwsub_wx(vbool2_t mask,vint16m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx(mask,op1,0xAA,31);
+}
+
+
+vint32mf2_t test___riscv_vwsub_wx(vbool64_t mask,vint32mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx(mask,op1,0xAA,31);
+}
+
+
+vint32m1_t test___riscv_vwsub_wx(vbool32_t mask,vint32m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx(mask,op1,0xAA,31);
+}
+
+
+vint32m2_t test___riscv_vwsub_wx(vbool16_t mask,vint32m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx(mask,op1,0xAA,31);
+}
+
+
+vint32m4_t test___riscv_vwsub_wx(vbool8_t mask,vint32m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx(mask,op1,0xAA,31);
+}
+
+
+vint32m8_t test___riscv_vwsub_wx(vbool4_t mask,vint32m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx(mask,op1,0xAA,31);
+}
+
+
+vint64m1_t test___riscv_vwsub_wx(vbool64_t mask,vint64m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx(mask,op1,0xAA,31);
+}
+
+
+vint64m2_t test___riscv_vwsub_wx(vbool32_t mask,vint64m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx(mask,op1,0xAA,31);
+}
+
+
+vint64m4_t test___riscv_vwsub_wx(vbool16_t mask,vint64m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx(mask,op1,0xAA,31);
+}
+
+
+vint64m8_t test___riscv_vwsub_wx(vbool8_t mask,vint64m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx(mask,op1,0xAA,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wx-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wx-3.C
new file mode 100644
index 00000000000..45279a394a8
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wx-3.C
@@ -0,0 +1,216 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwsub_wx(vint16mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx(op1,0xAA,32);
+}
+
+
+vint16mf2_t test___riscv_vwsub_wx(vint16mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx(op1,0xAA,32);
+}
+
+
+vint16m1_t test___riscv_vwsub_wx(vint16m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx(op1,0xAA,32);
+}
+
+
+vint16m2_t test___riscv_vwsub_wx(vint16m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx(op1,0xAA,32);
+}
+
+
+vint16m4_t test___riscv_vwsub_wx(vint16m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx(op1,0xAA,32);
+}
+
+
+vint16m8_t test___riscv_vwsub_wx(vint16m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx(op1,0xAA,32);
+}
+
+
+vint32mf2_t test___riscv_vwsub_wx(vint32mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx(op1,0xAA,32);
+}
+
+
+vint32m1_t test___riscv_vwsub_wx(vint32m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx(op1,0xAA,32);
+}
+
+
+vint32m2_t test___riscv_vwsub_wx(vint32m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx(op1,0xAA,32);
+}
+
+
+vint32m4_t test___riscv_vwsub_wx(vint32m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx(op1,0xAA,32);
+}
+
+
+vint32m8_t test___riscv_vwsub_wx(vint32m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx(op1,0xAA,32);
+}
+
+
+vint64m1_t test___riscv_vwsub_wx(vint64m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx(op1,0xAA,32);
+}
+
+
+vint64m2_t test___riscv_vwsub_wx(vint64m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx(op1,0xAA,32);
+}
+
+
+vint64m4_t test___riscv_vwsub_wx(vint64m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx(op1,0xAA,32);
+}
+
+
+vint64m8_t test___riscv_vwsub_wx(vint64m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx(op1,0xAA,32);
+}
+
+
+vint16mf4_t test___riscv_vwsub_wx(vbool64_t mask,vint16mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx(mask,op1,0xAA,32);
+}
+
+
+vint16mf2_t test___riscv_vwsub_wx(vbool32_t mask,vint16mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx(mask,op1,0xAA,32);
+}
+
+
+vint16m1_t test___riscv_vwsub_wx(vbool16_t mask,vint16m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx(mask,op1,0xAA,32);
+}
+
+
+vint16m2_t test___riscv_vwsub_wx(vbool8_t mask,vint16m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx(mask,op1,0xAA,32);
+}
+
+
+vint16m4_t test___riscv_vwsub_wx(vbool4_t mask,vint16m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx(mask,op1,0xAA,32);
+}
+
+
+vint16m8_t test___riscv_vwsub_wx(vbool2_t mask,vint16m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx(mask,op1,0xAA,32);
+}
+
+
+vint32mf2_t test___riscv_vwsub_wx(vbool64_t mask,vint32mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx(mask,op1,0xAA,32);
+}
+
+
+vint32m1_t test___riscv_vwsub_wx(vbool32_t mask,vint32m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx(mask,op1,0xAA,32);
+}
+
+
+vint32m2_t test___riscv_vwsub_wx(vbool16_t mask,vint32m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx(mask,op1,0xAA,32);
+}
+
+
+vint32m4_t test___riscv_vwsub_wx(vbool8_t mask,vint32m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx(mask,op1,0xAA,32);
+}
+
+
+vint32m8_t test___riscv_vwsub_wx(vbool4_t mask,vint32m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx(mask,op1,0xAA,32);
+}
+
+
+vint64m1_t test___riscv_vwsub_wx(vbool64_t mask,vint64m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx(mask,op1,0xAA,32);
+}
+
+
+vint64m2_t test___riscv_vwsub_wx(vbool32_t mask,vint64m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx(mask,op1,0xAA,32);
+}
+
+
+vint64m4_t test___riscv_vwsub_wx(vbool16_t mask,vint64m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx(mask,op1,0xAA,32);
+}
+
+
+vint64m8_t test___riscv_vwsub_wx(vbool8_t mask,vint64m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx(mask,op1,0xAA,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wx_mu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wx_mu-1.C
new file mode 100644
index 00000000000..39fd99e18ad
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wx_mu-1.C
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwsub_wx_mu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx_mu(mask,merge,op1,0xAA,vl);
+}
+
+
+vint16mf2_t test___riscv_vwsub_wx_mu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx_mu(mask,merge,op1,0xAA,vl);
+}
+
+
+vint16m1_t test___riscv_vwsub_wx_mu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx_mu(mask,merge,op1,0xAA,vl);
+}
+
+
+vint16m2_t test___riscv_vwsub_wx_mu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx_mu(mask,merge,op1,0xAA,vl);
+}
+
+
+vint16m4_t test___riscv_vwsub_wx_mu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx_mu(mask,merge,op1,0xAA,vl);
+}
+
+
+vint16m8_t test___riscv_vwsub_wx_mu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx_mu(mask,merge,op1,0xAA,vl);
+}
+
+
+vint32mf2_t test___riscv_vwsub_wx_mu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx_mu(mask,merge,op1,0xAA,vl);
+}
+
+
+vint32m1_t test___riscv_vwsub_wx_mu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx_mu(mask,merge,op1,0xAA,vl);
+}
+
+
+vint32m2_t test___riscv_vwsub_wx_mu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx_mu(mask,merge,op1,0xAA,vl);
+}
+
+
+vint32m4_t test___riscv_vwsub_wx_mu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx_mu(mask,merge,op1,0xAA,vl);
+}
+
+
+vint32m8_t test___riscv_vwsub_wx_mu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx_mu(mask,merge,op1,0xAA,vl);
+}
+
+
+vint64m1_t test___riscv_vwsub_wx_mu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx_mu(mask,merge,op1,0xAA,vl);
+}
+
+
+vint64m2_t test___riscv_vwsub_wx_mu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx_mu(mask,merge,op1,0xAA,vl);
+}
+
+
+vint64m4_t test___riscv_vwsub_wx_mu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx_mu(mask,merge,op1,0xAA,vl);
+}
+
+
+vint64m8_t test___riscv_vwsub_wx_mu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx_mu(mask,merge,op1,0xAA,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wx_mu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wx_mu-2.C
new file mode 100644
index 00000000000..d8e26c0f7d7
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wx_mu-2.C
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwsub_wx_mu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx_mu(mask,merge,op1,0xAA,31);
+}
+
+
+vint16mf2_t test___riscv_vwsub_wx_mu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx_mu(mask,merge,op1,0xAA,31);
+}
+
+
+vint16m1_t test___riscv_vwsub_wx_mu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx_mu(mask,merge,op1,0xAA,31);
+}
+
+
+vint16m2_t test___riscv_vwsub_wx_mu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx_mu(mask,merge,op1,0xAA,31);
+}
+
+
+vint16m4_t test___riscv_vwsub_wx_mu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx_mu(mask,merge,op1,0xAA,31);
+}
+
+
+vint16m8_t test___riscv_vwsub_wx_mu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx_mu(mask,merge,op1,0xAA,31);
+}
+
+
+vint32mf2_t test___riscv_vwsub_wx_mu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx_mu(mask,merge,op1,0xAA,31);
+}
+
+
+vint32m1_t test___riscv_vwsub_wx_mu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx_mu(mask,merge,op1,0xAA,31);
+}
+
+
+vint32m2_t test___riscv_vwsub_wx_mu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx_mu(mask,merge,op1,0xAA,31);
+}
+
+
+vint32m4_t test___riscv_vwsub_wx_mu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx_mu(mask,merge,op1,0xAA,31);
+}
+
+
+vint32m8_t test___riscv_vwsub_wx_mu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx_mu(mask,merge,op1,0xAA,31);
+}
+
+
+vint64m1_t test___riscv_vwsub_wx_mu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx_mu(mask,merge,op1,0xAA,31);
+}
+
+
+vint64m2_t test___riscv_vwsub_wx_mu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx_mu(mask,merge,op1,0xAA,31);
+}
+
+
+vint64m4_t test___riscv_vwsub_wx_mu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx_mu(mask,merge,op1,0xAA,31);
+}
+
+
+vint64m8_t test___riscv_vwsub_wx_mu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx_mu(mask,merge,op1,0xAA,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*mu\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*mu\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*mu\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*mu\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*mu\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*mu\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*mu\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*mu\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*mu\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wx_mu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wx_mu-3.C
new file mode 100644
index 00000000000..0e361d52e62
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wx_mu-3.C
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwsub_wx_mu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx_mu(mask,merge,op1,0xAA,32);
+}
+
+
+vint16mf2_t test___riscv_vwsub_wx_mu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx_mu(mask,merge,op1,0xAA,32);
+}
+
+
+vint16m1_t test___riscv_vwsub_wx_mu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx_mu(mask,merge,op1,0xAA,32);
+}
+
+
+vint16m2_t test___riscv_vwsub_wx_mu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx_mu(mask,merge,op1,0xAA,32);
+}
+
+
+vint16m4_t test___riscv_vwsub_wx_mu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx_mu(mask,merge,op1,0xAA,32);
+}
+
+
+vint16m8_t test___riscv_vwsub_wx_mu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx_mu(mask,merge,op1,0xAA,32);
+}
+
+
+vint32mf2_t test___riscv_vwsub_wx_mu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx_mu(mask,merge,op1,0xAA,32);
+}
+
+
+vint32m1_t test___riscv_vwsub_wx_mu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx_mu(mask,merge,op1,0xAA,32);
+}
+
+
+vint32m2_t test___riscv_vwsub_wx_mu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx_mu(mask,merge,op1,0xAA,32);
+}
+
+
+vint32m4_t test___riscv_vwsub_wx_mu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx_mu(mask,merge,op1,0xAA,32);
+}
+
+
+vint32m8_t test___riscv_vwsub_wx_mu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx_mu(mask,merge,op1,0xAA,32);
+}
+
+
+vint64m1_t test___riscv_vwsub_wx_mu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx_mu(mask,merge,op1,0xAA,32);
+}
+
+
+vint64m2_t test___riscv_vwsub_wx_mu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx_mu(mask,merge,op1,0xAA,32);
+}
+
+
+vint64m4_t test___riscv_vwsub_wx_mu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx_mu(mask,merge,op1,0xAA,32);
+}
+
+
+vint64m8_t test___riscv_vwsub_wx_mu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx_mu(mask,merge,op1,0xAA,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wx_tu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wx_tu-1.C
new file mode 100644
index 00000000000..a253bb6dbd2
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wx_tu-1.C
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwsub_wx_tu(vint16mf4_t merge,vint16mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx_tu(merge,op1,0xAA,vl);
+}
+
+
+vint16mf2_t test___riscv_vwsub_wx_tu(vint16mf2_t merge,vint16mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx_tu(merge,op1,0xAA,vl);
+}
+
+
+vint16m1_t test___riscv_vwsub_wx_tu(vint16m1_t merge,vint16m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx_tu(merge,op1,0xAA,vl);
+}
+
+
+vint16m2_t test___riscv_vwsub_wx_tu(vint16m2_t merge,vint16m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx_tu(merge,op1,0xAA,vl);
+}
+
+
+vint16m4_t test___riscv_vwsub_wx_tu(vint16m4_t merge,vint16m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx_tu(merge,op1,0xAA,vl);
+}
+
+
+vint16m8_t test___riscv_vwsub_wx_tu(vint16m8_t merge,vint16m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx_tu(merge,op1,0xAA,vl);
+}
+
+
+vint32mf2_t test___riscv_vwsub_wx_tu(vint32mf2_t merge,vint32mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx_tu(merge,op1,0xAA,vl);
+}
+
+
+vint32m1_t test___riscv_vwsub_wx_tu(vint32m1_t merge,vint32m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx_tu(merge,op1,0xAA,vl);
+}
+
+
+vint32m2_t test___riscv_vwsub_wx_tu(vint32m2_t merge,vint32m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx_tu(merge,op1,0xAA,vl);
+}
+
+
+vint32m4_t test___riscv_vwsub_wx_tu(vint32m4_t merge,vint32m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx_tu(merge,op1,0xAA,vl);
+}
+
+
+vint32m8_t test___riscv_vwsub_wx_tu(vint32m8_t merge,vint32m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx_tu(merge,op1,0xAA,vl);
+}
+
+
+vint64m1_t test___riscv_vwsub_wx_tu(vint64m1_t merge,vint64m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx_tu(merge,op1,0xAA,vl);
+}
+
+
+vint64m2_t test___riscv_vwsub_wx_tu(vint64m2_t merge,vint64m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx_tu(merge,op1,0xAA,vl);
+}
+
+
+vint64m4_t test___riscv_vwsub_wx_tu(vint64m4_t merge,vint64m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx_tu(merge,op1,0xAA,vl);
+}
+
+
+vint64m8_t test___riscv_vwsub_wx_tu(vint64m8_t merge,vint64m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx_tu(merge,op1,0xAA,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wx_tu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wx_tu-2.C
new file mode 100644
index 00000000000..1eb145ea4ef
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wx_tu-2.C
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwsub_wx_tu(vint16mf4_t merge,vint16mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx_tu(merge,op1,0xAA,31);
+}
+
+
+vint16mf2_t test___riscv_vwsub_wx_tu(vint16mf2_t merge,vint16mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx_tu(merge,op1,0xAA,31);
+}
+
+
+vint16m1_t test___riscv_vwsub_wx_tu(vint16m1_t merge,vint16m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx_tu(merge,op1,0xAA,31);
+}
+
+
+vint16m2_t test___riscv_vwsub_wx_tu(vint16m2_t merge,vint16m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx_tu(merge,op1,0xAA,31);
+}
+
+
+vint16m4_t test___riscv_vwsub_wx_tu(vint16m4_t merge,vint16m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx_tu(merge,op1,0xAA,31);
+}
+
+
+vint16m8_t test___riscv_vwsub_wx_tu(vint16m8_t merge,vint16m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx_tu(merge,op1,0xAA,31);
+}
+
+
+vint32mf2_t test___riscv_vwsub_wx_tu(vint32mf2_t merge,vint32mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx_tu(merge,op1,0xAA,31);
+}
+
+
+vint32m1_t test___riscv_vwsub_wx_tu(vint32m1_t merge,vint32m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx_tu(merge,op1,0xAA,31);
+}
+
+
+vint32m2_t test___riscv_vwsub_wx_tu(vint32m2_t merge,vint32m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx_tu(merge,op1,0xAA,31);
+}
+
+
+vint32m4_t test___riscv_vwsub_wx_tu(vint32m4_t merge,vint32m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx_tu(merge,op1,0xAA,31);
+}
+
+
+vint32m8_t test___riscv_vwsub_wx_tu(vint32m8_t merge,vint32m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx_tu(merge,op1,0xAA,31);
+}
+
+
+vint64m1_t test___riscv_vwsub_wx_tu(vint64m1_t merge,vint64m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx_tu(merge,op1,0xAA,31);
+}
+
+
+vint64m2_t test___riscv_vwsub_wx_tu(vint64m2_t merge,vint64m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx_tu(merge,op1,0xAA,31);
+}
+
+
+vint64m4_t test___riscv_vwsub_wx_tu(vint64m4_t merge,vint64m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx_tu(merge,op1,0xAA,31);
+}
+
+
+vint64m8_t test___riscv_vwsub_wx_tu(vint64m8_t merge,vint64m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx_tu(merge,op1,0xAA,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wx_tu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wx_tu-3.C
new file mode 100644
index 00000000000..56b2f3677a7
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wx_tu-3.C
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwsub_wx_tu(vint16mf4_t merge,vint16mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx_tu(merge,op1,0xAA,32);
+}
+
+
+vint16mf2_t test___riscv_vwsub_wx_tu(vint16mf2_t merge,vint16mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx_tu(merge,op1,0xAA,32);
+}
+
+
+vint16m1_t test___riscv_vwsub_wx_tu(vint16m1_t merge,vint16m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx_tu(merge,op1,0xAA,32);
+}
+
+
+vint16m2_t test___riscv_vwsub_wx_tu(vint16m2_t merge,vint16m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx_tu(merge,op1,0xAA,32);
+}
+
+
+vint16m4_t test___riscv_vwsub_wx_tu(vint16m4_t merge,vint16m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx_tu(merge,op1,0xAA,32);
+}
+
+
+vint16m8_t test___riscv_vwsub_wx_tu(vint16m8_t merge,vint16m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx_tu(merge,op1,0xAA,32);
+}
+
+
+vint32mf2_t test___riscv_vwsub_wx_tu(vint32mf2_t merge,vint32mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx_tu(merge,op1,0xAA,32);
+}
+
+
+vint32m1_t test___riscv_vwsub_wx_tu(vint32m1_t merge,vint32m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx_tu(merge,op1,0xAA,32);
+}
+
+
+vint32m2_t test___riscv_vwsub_wx_tu(vint32m2_t merge,vint32m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx_tu(merge,op1,0xAA,32);
+}
+
+
+vint32m4_t test___riscv_vwsub_wx_tu(vint32m4_t merge,vint32m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx_tu(merge,op1,0xAA,32);
+}
+
+
+vint32m8_t test___riscv_vwsub_wx_tu(vint32m8_t merge,vint32m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx_tu(merge,op1,0xAA,32);
+}
+
+
+vint64m1_t test___riscv_vwsub_wx_tu(vint64m1_t merge,vint64m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx_tu(merge,op1,0xAA,32);
+}
+
+
+vint64m2_t test___riscv_vwsub_wx_tu(vint64m2_t merge,vint64m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx_tu(merge,op1,0xAA,32);
+}
+
+
+vint64m4_t test___riscv_vwsub_wx_tu(vint64m4_t merge,vint64m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx_tu(merge,op1,0xAA,32);
+}
+
+
+vint64m8_t test___riscv_vwsub_wx_tu(vint64m8_t merge,vint64m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx_tu(merge,op1,0xAA,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wx_tum-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wx_tum-1.C
new file mode 100644
index 00000000000..6d403facaf8
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wx_tum-1.C
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwsub_wx_tum(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx_tum(mask,merge,op1,0xAA,vl);
+}
+
+
+vint16mf2_t test___riscv_vwsub_wx_tum(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx_tum(mask,merge,op1,0xAA,vl);
+}
+
+
+vint16m1_t test___riscv_vwsub_wx_tum(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx_tum(mask,merge,op1,0xAA,vl);
+}
+
+
+vint16m2_t test___riscv_vwsub_wx_tum(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx_tum(mask,merge,op1,0xAA,vl);
+}
+
+
+vint16m4_t test___riscv_vwsub_wx_tum(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx_tum(mask,merge,op1,0xAA,vl);
+}
+
+
+vint16m8_t test___riscv_vwsub_wx_tum(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx_tum(mask,merge,op1,0xAA,vl);
+}
+
+
+vint32mf2_t test___riscv_vwsub_wx_tum(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx_tum(mask,merge,op1,0xAA,vl);
+}
+
+
+vint32m1_t test___riscv_vwsub_wx_tum(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx_tum(mask,merge,op1,0xAA,vl);
+}
+
+
+vint32m2_t test___riscv_vwsub_wx_tum(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx_tum(mask,merge,op1,0xAA,vl);
+}
+
+
+vint32m4_t test___riscv_vwsub_wx_tum(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx_tum(mask,merge,op1,0xAA,vl);
+}
+
+
+vint32m8_t test___riscv_vwsub_wx_tum(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx_tum(mask,merge,op1,0xAA,vl);
+}
+
+
+vint64m1_t test___riscv_vwsub_wx_tum(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx_tum(mask,merge,op1,0xAA,vl);
+}
+
+
+vint64m2_t test___riscv_vwsub_wx_tum(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx_tum(mask,merge,op1,0xAA,vl);
+}
+
+
+vint64m4_t test___riscv_vwsub_wx_tum(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx_tum(mask,merge,op1,0xAA,vl);
+}
+
+
+vint64m8_t test___riscv_vwsub_wx_tum(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx_tum(mask,merge,op1,0xAA,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wx_tum-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wx_tum-2.C
new file mode 100644
index 00000000000..4f39d244f45
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wx_tum-2.C
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwsub_wx_tum(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx_tum(mask,merge,op1,0xAA,31);
+}
+
+
+vint16mf2_t test___riscv_vwsub_wx_tum(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx_tum(mask,merge,op1,0xAA,31);
+}
+
+
+vint16m1_t test___riscv_vwsub_wx_tum(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx_tum(mask,merge,op1,0xAA,31);
+}
+
+
+vint16m2_t test___riscv_vwsub_wx_tum(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx_tum(mask,merge,op1,0xAA,31);
+}
+
+
+vint16m4_t test___riscv_vwsub_wx_tum(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx_tum(mask,merge,op1,0xAA,31);
+}
+
+
+vint16m8_t test___riscv_vwsub_wx_tum(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx_tum(mask,merge,op1,0xAA,31);
+}
+
+
+vint32mf2_t test___riscv_vwsub_wx_tum(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx_tum(mask,merge,op1,0xAA,31);
+}
+
+
+vint32m1_t test___riscv_vwsub_wx_tum(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx_tum(mask,merge,op1,0xAA,31);
+}
+
+
+vint32m2_t test___riscv_vwsub_wx_tum(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx_tum(mask,merge,op1,0xAA,31);
+}
+
+
+vint32m4_t test___riscv_vwsub_wx_tum(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx_tum(mask,merge,op1,0xAA,31);
+}
+
+
+vint32m8_t test___riscv_vwsub_wx_tum(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx_tum(mask,merge,op1,0xAA,31);
+}
+
+
+vint64m1_t test___riscv_vwsub_wx_tum(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx_tum(mask,merge,op1,0xAA,31);
+}
+
+
+vint64m2_t test___riscv_vwsub_wx_tum(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx_tum(mask,merge,op1,0xAA,31);
+}
+
+
+vint64m4_t test___riscv_vwsub_wx_tum(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx_tum(mask,merge,op1,0xAA,31);
+}
+
+
+vint64m8_t test___riscv_vwsub_wx_tum(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx_tum(mask,merge,op1,0xAA,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wx_tum-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wx_tum-3.C
new file mode 100644
index 00000000000..d8df066beb7
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wx_tum-3.C
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwsub_wx_tum(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx_tum(mask,merge,op1,0xAA,32);
+}
+
+
+vint16mf2_t test___riscv_vwsub_wx_tum(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx_tum(mask,merge,op1,0xAA,32);
+}
+
+
+vint16m1_t test___riscv_vwsub_wx_tum(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx_tum(mask,merge,op1,0xAA,32);
+}
+
+
+vint16m2_t test___riscv_vwsub_wx_tum(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx_tum(mask,merge,op1,0xAA,32);
+}
+
+
+vint16m4_t test___riscv_vwsub_wx_tum(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx_tum(mask,merge,op1,0xAA,32);
+}
+
+
+vint16m8_t test___riscv_vwsub_wx_tum(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx_tum(mask,merge,op1,0xAA,32);
+}
+
+
+vint32mf2_t test___riscv_vwsub_wx_tum(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx_tum(mask,merge,op1,0xAA,32);
+}
+
+
+vint32m1_t test___riscv_vwsub_wx_tum(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx_tum(mask,merge,op1,0xAA,32);
+}
+
+
+vint32m2_t test___riscv_vwsub_wx_tum(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx_tum(mask,merge,op1,0xAA,32);
+}
+
+
+vint32m4_t test___riscv_vwsub_wx_tum(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx_tum(mask,merge,op1,0xAA,32);
+}
+
+
+vint32m8_t test___riscv_vwsub_wx_tum(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx_tum(mask,merge,op1,0xAA,32);
+}
+
+
+vint64m1_t test___riscv_vwsub_wx_tum(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx_tum(mask,merge,op1,0xAA,32);
+}
+
+
+vint64m2_t test___riscv_vwsub_wx_tum(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx_tum(mask,merge,op1,0xAA,32);
+}
+
+
+vint64m4_t test___riscv_vwsub_wx_tum(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx_tum(mask,merge,op1,0xAA,32);
+}
+
+
+vint64m8_t test___riscv_vwsub_wx_tum(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx_tum(mask,merge,op1,0xAA,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wx_tumu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wx_tumu-1.C
new file mode 100644
index 00000000000..d08185bdc1d
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wx_tumu-1.C
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwsub_wx_tumu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx_tumu(mask,merge,op1,0xAA,vl);
+}
+
+
+vint16mf2_t test___riscv_vwsub_wx_tumu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx_tumu(mask,merge,op1,0xAA,vl);
+}
+
+
+vint16m1_t test___riscv_vwsub_wx_tumu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx_tumu(mask,merge,op1,0xAA,vl);
+}
+
+
+vint16m2_t test___riscv_vwsub_wx_tumu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx_tumu(mask,merge,op1,0xAA,vl);
+}
+
+
+vint16m4_t test___riscv_vwsub_wx_tumu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx_tumu(mask,merge,op1,0xAA,vl);
+}
+
+
+vint16m8_t test___riscv_vwsub_wx_tumu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx_tumu(mask,merge,op1,0xAA,vl);
+}
+
+
+vint32mf2_t test___riscv_vwsub_wx_tumu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx_tumu(mask,merge,op1,0xAA,vl);
+}
+
+
+vint32m1_t test___riscv_vwsub_wx_tumu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx_tumu(mask,merge,op1,0xAA,vl);
+}
+
+
+vint32m2_t test___riscv_vwsub_wx_tumu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx_tumu(mask,merge,op1,0xAA,vl);
+}
+
+
+vint32m4_t test___riscv_vwsub_wx_tumu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx_tumu(mask,merge,op1,0xAA,vl);
+}
+
+
+vint32m8_t test___riscv_vwsub_wx_tumu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx_tumu(mask,merge,op1,0xAA,vl);
+}
+
+
+vint64m1_t test___riscv_vwsub_wx_tumu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx_tumu(mask,merge,op1,0xAA,vl);
+}
+
+
+vint64m2_t test___riscv_vwsub_wx_tumu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx_tumu(mask,merge,op1,0xAA,vl);
+}
+
+
+vint64m4_t test___riscv_vwsub_wx_tumu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx_tumu(mask,merge,op1,0xAA,vl);
+}
+
+
+vint64m8_t test___riscv_vwsub_wx_tumu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx_tumu(mask,merge,op1,0xAA,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wx_tumu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wx_tumu-2.C
new file mode 100644
index 00000000000..01ab6335071
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wx_tumu-2.C
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwsub_wx_tumu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx_tumu(mask,merge,op1,0xAA,31);
+}
+
+
+vint16mf2_t test___riscv_vwsub_wx_tumu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx_tumu(mask,merge,op1,0xAA,31);
+}
+
+
+vint16m1_t test___riscv_vwsub_wx_tumu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx_tumu(mask,merge,op1,0xAA,31);
+}
+
+
+vint16m2_t test___riscv_vwsub_wx_tumu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx_tumu(mask,merge,op1,0xAA,31);
+}
+
+
+vint16m4_t test___riscv_vwsub_wx_tumu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx_tumu(mask,merge,op1,0xAA,31);
+}
+
+
+vint16m8_t test___riscv_vwsub_wx_tumu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx_tumu(mask,merge,op1,0xAA,31);
+}
+
+
+vint32mf2_t test___riscv_vwsub_wx_tumu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx_tumu(mask,merge,op1,0xAA,31);
+}
+
+
+vint32m1_t test___riscv_vwsub_wx_tumu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx_tumu(mask,merge,op1,0xAA,31);
+}
+
+
+vint32m2_t test___riscv_vwsub_wx_tumu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx_tumu(mask,merge,op1,0xAA,31);
+}
+
+
+vint32m4_t test___riscv_vwsub_wx_tumu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx_tumu(mask,merge,op1,0xAA,31);
+}
+
+
+vint32m8_t test___riscv_vwsub_wx_tumu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx_tumu(mask,merge,op1,0xAA,31);
+}
+
+
+vint64m1_t test___riscv_vwsub_wx_tumu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx_tumu(mask,merge,op1,0xAA,31);
+}
+
+
+vint64m2_t test___riscv_vwsub_wx_tumu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx_tumu(mask,merge,op1,0xAA,31);
+}
+
+
+vint64m4_t test___riscv_vwsub_wx_tumu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx_tumu(mask,merge,op1,0xAA,31);
+}
+
+
+vint64m8_t test___riscv_vwsub_wx_tumu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx_tumu(mask,merge,op1,0xAA,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*mu\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*mu\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*mu\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*mu\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*mu\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*mu\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*mu\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*mu\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*mu\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*mu\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*mu\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*mu\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*mu\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*mu\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*mu\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wx_tumu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wx_tumu-3.C
new file mode 100644
index 00000000000..9a58c760b64
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wx_tumu-3.C
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwsub_wx_tumu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx_tumu(mask,merge,op1,0xAA,32);
+}
+
+
+vint16mf2_t test___riscv_vwsub_wx_tumu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx_tumu(mask,merge,op1,0xAA,32);
+}
+
+
+vint16m1_t test___riscv_vwsub_wx_tumu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx_tumu(mask,merge,op1,0xAA,32);
+}
+
+
+vint16m2_t test___riscv_vwsub_wx_tumu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx_tumu(mask,merge,op1,0xAA,32);
+}
+
+
+vint16m4_t test___riscv_vwsub_wx_tumu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx_tumu(mask,merge,op1,0xAA,32);
+}
+
+
+vint16m8_t test___riscv_vwsub_wx_tumu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx_tumu(mask,merge,op1,0xAA,32);
+}
+
+
+vint32mf2_t test___riscv_vwsub_wx_tumu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx_tumu(mask,merge,op1,0xAA,32);
+}
+
+
+vint32m1_t test___riscv_vwsub_wx_tumu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx_tumu(mask,merge,op1,0xAA,32);
+}
+
+
+vint32m2_t test___riscv_vwsub_wx_tumu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx_tumu(mask,merge,op1,0xAA,32);
+}
+
+
+vint32m4_t test___riscv_vwsub_wx_tumu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx_tumu(mask,merge,op1,0xAA,32);
+}
+
+
+vint32m8_t test___riscv_vwsub_wx_tumu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx_tumu(mask,merge,op1,0xAA,32);
+}
+
+
+vint64m1_t test___riscv_vwsub_wx_tumu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx_tumu(mask,merge,op1,0xAA,32);
+}
+
+
+vint64m2_t test___riscv_vwsub_wx_tumu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx_tumu(mask,merge,op1,0xAA,32);
+}
+
+
+vint64m4_t test___riscv_vwsub_wx_tumu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx_tumu(mask,merge,op1,0xAA,32);
+}
+
+
+vint64m8_t test___riscv_vwsub_wx_tumu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vwsub_wx_tumu(mask,merge,op1,0xAA,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */