From patchwork Tue Feb 7 06:40:38 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "juzhe.zhong@rivai.ai" X-Patchwork-Id: 64421 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id C1A2B3858C52 for ; Tue, 7 Feb 2023 06:41:10 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from smtpbguseast1.qq.com (smtpbguseast1.qq.com [54.204.34.129]) by sourceware.org (Postfix) with ESMTPS id 039543858D35 for ; Tue, 7 Feb 2023 06:40:44 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 039543858D35 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivai.ai Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivai.ai X-QQ-mid: bizesmtp88t1675752040tv57muhb Received: from server1.localdomain ( [58.60.1.22]) by bizesmtp.qq.com (ESMTP) with id ; Tue, 07 Feb 2023 14:40:39 +0800 (CST) X-QQ-SSF: 01400000000000E0L000000A0000000 X-QQ-FEAT: EJRychaPwbeQDiHxsa7r3BsPUHJiymD/GDkPP/5nPAo5lY75nk6h61Ojpc5Af qi23Rq6GYz3rTQWVOBPjdDpOjFTmN5760aL074XJQK3LoyXzpY+oIBcpUkx4QTidBGI74qa fhq90C9Fj9eZm6vARm19zudVUGZvX4gOR+qcrjAHODXYvmwJsh2eGsQqQWgbrplUeAFGsFk 5e5sP+6j/KNx7EnTBsigEHSmaFWC4paz+T0uLqVmwOfH8m6D/Q/Pzfs/Zw1EvizgQ4geV48 0C28TttX8ruERyP4fbOdsoLilWMHSrrQSEqMG7XyGLDD0NBVbRmE8dfQ/ROcOcsJuM0qLWu P+5WxZCZ1QTv+vhjwVr6Dm+CHYiadAY4HUC9WL3wv/oRilM5YWZjCMmoKmgkg== X-QQ-GoodBg: 2 From: juzhe.zhong@rivai.ai To: gcc-patches@gcc.gnu.org Cc: kito.cheng@gmail.com, Ju-Zhe Zhong Subject: [PATCH] RISC-V: Add vwsubu.w C++ api TETS Date: Tue, 7 Feb 2023 14:40:38 +0800 Message-Id: <20230207064038.41137-1-juzhe.zhong@rivai.ai> X-Mailer: git-send-email 2.36.1 MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:rivai.ai:qybglogicsvr:qybglogicsvr7 X-Spam-Status: No, score=-10.9 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, RCVD_IN_BARRACUDACENTRAL, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_PASS, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" From: Ju-Zhe Zhong gcc/testsuite/ChangeLog: * g++.target/riscv/rvv/base/vwsubu_wv-1.C: New test. * g++.target/riscv/rvv/base/vwsubu_wv-2.C: New test. * g++.target/riscv/rvv/base/vwsubu_wv-3.C: New test. * g++.target/riscv/rvv/base/vwsubu_wv_mu-1.C: New test. * g++.target/riscv/rvv/base/vwsubu_wv_mu-2.C: New test. * g++.target/riscv/rvv/base/vwsubu_wv_mu-3.C: New test. * g++.target/riscv/rvv/base/vwsubu_wv_tu-1.C: New test. * g++.target/riscv/rvv/base/vwsubu_wv_tu-2.C: New test. * g++.target/riscv/rvv/base/vwsubu_wv_tu-3.C: New test. * g++.target/riscv/rvv/base/vwsubu_wv_tum-1.C: New test. * g++.target/riscv/rvv/base/vwsubu_wv_tum-2.C: New test. * g++.target/riscv/rvv/base/vwsubu_wv_tum-3.C: New test. * g++.target/riscv/rvv/base/vwsubu_wv_tumu-1.C: New test. * g++.target/riscv/rvv/base/vwsubu_wv_tumu-2.C: New test. * g++.target/riscv/rvv/base/vwsubu_wv_tumu-3.C: New test. * g++.target/riscv/rvv/base/vwsubu_wx-1.C: New test. * g++.target/riscv/rvv/base/vwsubu_wx-2.C: New test. * g++.target/riscv/rvv/base/vwsubu_wx-3.C: New test. * g++.target/riscv/rvv/base/vwsubu_wx_mu-1.C: New test. * g++.target/riscv/rvv/base/vwsubu_wx_mu-2.C: New test. * g++.target/riscv/rvv/base/vwsubu_wx_mu-3.C: New test. * g++.target/riscv/rvv/base/vwsubu_wx_tu-1.C: New test. * g++.target/riscv/rvv/base/vwsubu_wx_tu-2.C: New test. * g++.target/riscv/rvv/base/vwsubu_wx_tu-3.C: New test. * g++.target/riscv/rvv/base/vwsubu_wx_tum-1.C: New test. * g++.target/riscv/rvv/base/vwsubu_wx_tum-2.C: New test. * g++.target/riscv/rvv/base/vwsubu_wx_tum-3.C: New test. * g++.target/riscv/rvv/base/vwsubu_wx_tumu-1.C: New test. * g++.target/riscv/rvv/base/vwsubu_wx_tumu-2.C: New test. * g++.target/riscv/rvv/base/vwsubu_wx_tumu-3.C: New test. --- .../g++.target/riscv/rvv/base/vwsubu_wv-1.C | 216 ++++++++++++++++++ .../g++.target/riscv/rvv/base/vwsubu_wv-2.C | 216 ++++++++++++++++++ .../g++.target/riscv/rvv/base/vwsubu_wv-3.C | 216 ++++++++++++++++++ .../riscv/rvv/base/vwsubu_wv_mu-1.C | 111 +++++++++ .../riscv/rvv/base/vwsubu_wv_mu-2.C | 111 +++++++++ .../riscv/rvv/base/vwsubu_wv_mu-3.C | 111 +++++++++ .../riscv/rvv/base/vwsubu_wv_tu-1.C | 111 +++++++++ .../riscv/rvv/base/vwsubu_wv_tu-2.C | 111 +++++++++ .../riscv/rvv/base/vwsubu_wv_tu-3.C | 111 +++++++++ .../riscv/rvv/base/vwsubu_wv_tum-1.C | 111 +++++++++ .../riscv/rvv/base/vwsubu_wv_tum-2.C | 111 +++++++++ .../riscv/rvv/base/vwsubu_wv_tum-3.C | 111 +++++++++ .../riscv/rvv/base/vwsubu_wv_tumu-1.C | 111 +++++++++ .../riscv/rvv/base/vwsubu_wv_tumu-2.C | 111 +++++++++ .../riscv/rvv/base/vwsubu_wv_tumu-3.C | 111 +++++++++ .../g++.target/riscv/rvv/base/vwsubu_wx-1.C | 216 ++++++++++++++++++ .../g++.target/riscv/rvv/base/vwsubu_wx-2.C | 216 ++++++++++++++++++ .../g++.target/riscv/rvv/base/vwsubu_wx-3.C | 216 ++++++++++++++++++ .../riscv/rvv/base/vwsubu_wx_mu-1.C | 111 +++++++++ .../riscv/rvv/base/vwsubu_wx_mu-2.C | 111 +++++++++ .../riscv/rvv/base/vwsubu_wx_mu-3.C | 111 +++++++++ .../riscv/rvv/base/vwsubu_wx_tu-1.C | 111 +++++++++ .../riscv/rvv/base/vwsubu_wx_tu-2.C | 111 +++++++++ .../riscv/rvv/base/vwsubu_wx_tu-3.C | 111 +++++++++ .../riscv/rvv/base/vwsubu_wx_tum-1.C | 111 +++++++++ .../riscv/rvv/base/vwsubu_wx_tum-2.C | 111 +++++++++ .../riscv/rvv/base/vwsubu_wx_tum-3.C | 111 +++++++++ .../riscv/rvv/base/vwsubu_wx_tumu-1.C | 111 +++++++++ .../riscv/rvv/base/vwsubu_wx_tumu-2.C | 111 +++++++++ .../riscv/rvv/base/vwsubu_wx_tumu-3.C | 111 +++++++++ 30 files changed, 3960 insertions(+) create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_wv-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_wv-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_wv-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_wv_mu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_wv_mu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_wv_mu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_wv_tu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_wv_tu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_wv_tu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_wv_tum-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_wv_tum-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_wv_tum-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_wv_tumu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_wv_tumu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_wv_tumu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_wx-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_wx-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_wx-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_wx_mu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_wx_mu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_wx_mu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_wx_tu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_wx_tu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_wx_tu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_wx_tum-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_wx_tum-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_wx_tum-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_wx_tumu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_wx_tumu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_wx_tumu-3.C diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_wv-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_wv-1.C new file mode 100644 index 00000000000..730d9ba9ca2 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_wv-1.C @@ -0,0 +1,216 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwsubu_wv(vuint16mf4_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vwsubu_wv(op1,op2,vl); +} + + +vuint16mf2_t test___riscv_vwsubu_wv(vuint16mf2_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vwsubu_wv(op1,op2,vl); +} + + +vuint16m1_t test___riscv_vwsubu_wv(vuint16m1_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vwsubu_wv(op1,op2,vl); +} + + +vuint16m2_t test___riscv_vwsubu_wv(vuint16m2_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vwsubu_wv(op1,op2,vl); +} + + +vuint16m4_t test___riscv_vwsubu_wv(vuint16m4_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vwsubu_wv(op1,op2,vl); +} + + +vuint16m8_t test___riscv_vwsubu_wv(vuint16m8_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vwsubu_wv(op1,op2,vl); +} + + +vuint32mf2_t test___riscv_vwsubu_wv(vuint32mf2_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vwsubu_wv(op1,op2,vl); +} + + +vuint32m1_t test___riscv_vwsubu_wv(vuint32m1_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vwsubu_wv(op1,op2,vl); +} + + +vuint32m2_t test___riscv_vwsubu_wv(vuint32m2_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vwsubu_wv(op1,op2,vl); +} + + +vuint32m4_t test___riscv_vwsubu_wv(vuint32m4_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vwsubu_wv(op1,op2,vl); +} + + +vuint32m8_t test___riscv_vwsubu_wv(vuint32m8_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vwsubu_wv(op1,op2,vl); +} + + +vuint64m1_t test___riscv_vwsubu_wv(vuint64m1_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vwsubu_wv(op1,op2,vl); +} + + +vuint64m2_t test___riscv_vwsubu_wv(vuint64m2_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vwsubu_wv(op1,op2,vl); +} + + +vuint64m4_t test___riscv_vwsubu_wv(vuint64m4_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vwsubu_wv(op1,op2,vl); +} + + +vuint64m8_t test___riscv_vwsubu_wv(vuint64m8_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vwsubu_wv(op1,op2,vl); +} + + +vuint16mf4_t test___riscv_vwsubu_wv(vbool64_t mask,vuint16mf4_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vwsubu_wv(mask,op1,op2,vl); +} + + +vuint16mf2_t test___riscv_vwsubu_wv(vbool32_t mask,vuint16mf2_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vwsubu_wv(mask,op1,op2,vl); +} + + +vuint16m1_t test___riscv_vwsubu_wv(vbool16_t mask,vuint16m1_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vwsubu_wv(mask,op1,op2,vl); +} + + +vuint16m2_t test___riscv_vwsubu_wv(vbool8_t mask,vuint16m2_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vwsubu_wv(mask,op1,op2,vl); +} + + +vuint16m4_t test___riscv_vwsubu_wv(vbool4_t mask,vuint16m4_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vwsubu_wv(mask,op1,op2,vl); +} + + +vuint16m8_t test___riscv_vwsubu_wv(vbool2_t mask,vuint16m8_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vwsubu_wv(mask,op1,op2,vl); +} + + +vuint32mf2_t test___riscv_vwsubu_wv(vbool64_t mask,vuint32mf2_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vwsubu_wv(mask,op1,op2,vl); +} + + +vuint32m1_t test___riscv_vwsubu_wv(vbool32_t mask,vuint32m1_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vwsubu_wv(mask,op1,op2,vl); +} + + +vuint32m2_t test___riscv_vwsubu_wv(vbool16_t mask,vuint32m2_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vwsubu_wv(mask,op1,op2,vl); +} + + +vuint32m4_t test___riscv_vwsubu_wv(vbool8_t mask,vuint32m4_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vwsubu_wv(mask,op1,op2,vl); +} + + +vuint32m8_t test___riscv_vwsubu_wv(vbool4_t mask,vuint32m8_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vwsubu_wv(mask,op1,op2,vl); +} + + +vuint64m1_t test___riscv_vwsubu_wv(vbool64_t mask,vuint64m1_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vwsubu_wv(mask,op1,op2,vl); +} + + +vuint64m2_t test___riscv_vwsubu_wv(vbool32_t mask,vuint64m2_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vwsubu_wv(mask,op1,op2,vl); +} + + +vuint64m4_t test___riscv_vwsubu_wv(vbool16_t mask,vuint64m4_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vwsubu_wv(mask,op1,op2,vl); +} + + +vuint64m8_t test___riscv_vwsubu_wv(vbool8_t mask,vuint64m8_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vwsubu_wv(mask,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_wv-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_wv-2.C new file mode 100644 index 00000000000..36070bcebcf --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_wv-2.C @@ -0,0 +1,216 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwsubu_wv(vuint16mf4_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vwsubu_wv(op1,op2,31); +} + + +vuint16mf2_t test___riscv_vwsubu_wv(vuint16mf2_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vwsubu_wv(op1,op2,31); +} + + +vuint16m1_t test___riscv_vwsubu_wv(vuint16m1_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vwsubu_wv(op1,op2,31); +} + + +vuint16m2_t test___riscv_vwsubu_wv(vuint16m2_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vwsubu_wv(op1,op2,31); +} + + +vuint16m4_t test___riscv_vwsubu_wv(vuint16m4_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vwsubu_wv(op1,op2,31); +} + + +vuint16m8_t test___riscv_vwsubu_wv(vuint16m8_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vwsubu_wv(op1,op2,31); +} + + +vuint32mf2_t test___riscv_vwsubu_wv(vuint32mf2_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vwsubu_wv(op1,op2,31); +} + + +vuint32m1_t test___riscv_vwsubu_wv(vuint32m1_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vwsubu_wv(op1,op2,31); +} + + +vuint32m2_t test___riscv_vwsubu_wv(vuint32m2_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vwsubu_wv(op1,op2,31); +} + + +vuint32m4_t test___riscv_vwsubu_wv(vuint32m4_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vwsubu_wv(op1,op2,31); +} + + +vuint32m8_t test___riscv_vwsubu_wv(vuint32m8_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vwsubu_wv(op1,op2,31); +} + + +vuint64m1_t test___riscv_vwsubu_wv(vuint64m1_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vwsubu_wv(op1,op2,31); +} + + +vuint64m2_t test___riscv_vwsubu_wv(vuint64m2_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vwsubu_wv(op1,op2,31); +} + + +vuint64m4_t test___riscv_vwsubu_wv(vuint64m4_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vwsubu_wv(op1,op2,31); +} + + +vuint64m8_t test___riscv_vwsubu_wv(vuint64m8_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vwsubu_wv(op1,op2,31); +} + + +vuint16mf4_t test___riscv_vwsubu_wv(vbool64_t mask,vuint16mf4_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vwsubu_wv(mask,op1,op2,31); +} + + +vuint16mf2_t test___riscv_vwsubu_wv(vbool32_t mask,vuint16mf2_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vwsubu_wv(mask,op1,op2,31); +} + + +vuint16m1_t test___riscv_vwsubu_wv(vbool16_t mask,vuint16m1_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vwsubu_wv(mask,op1,op2,31); +} + + +vuint16m2_t test___riscv_vwsubu_wv(vbool8_t mask,vuint16m2_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vwsubu_wv(mask,op1,op2,31); +} + + +vuint16m4_t test___riscv_vwsubu_wv(vbool4_t mask,vuint16m4_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vwsubu_wv(mask,op1,op2,31); +} + + +vuint16m8_t test___riscv_vwsubu_wv(vbool2_t mask,vuint16m8_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vwsubu_wv(mask,op1,op2,31); +} + + +vuint32mf2_t test___riscv_vwsubu_wv(vbool64_t mask,vuint32mf2_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vwsubu_wv(mask,op1,op2,31); +} + + +vuint32m1_t test___riscv_vwsubu_wv(vbool32_t mask,vuint32m1_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vwsubu_wv(mask,op1,op2,31); +} + + +vuint32m2_t test___riscv_vwsubu_wv(vbool16_t mask,vuint32m2_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vwsubu_wv(mask,op1,op2,31); +} + + +vuint32m4_t test___riscv_vwsubu_wv(vbool8_t mask,vuint32m4_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vwsubu_wv(mask,op1,op2,31); +} + + +vuint32m8_t test___riscv_vwsubu_wv(vbool4_t mask,vuint32m8_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vwsubu_wv(mask,op1,op2,31); +} + + +vuint64m1_t test___riscv_vwsubu_wv(vbool64_t mask,vuint64m1_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vwsubu_wv(mask,op1,op2,31); +} + + +vuint64m2_t test___riscv_vwsubu_wv(vbool32_t mask,vuint64m2_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vwsubu_wv(mask,op1,op2,31); +} + + +vuint64m4_t test___riscv_vwsubu_wv(vbool16_t mask,vuint64m4_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vwsubu_wv(mask,op1,op2,31); +} + + +vuint64m8_t test___riscv_vwsubu_wv(vbool8_t mask,vuint64m8_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vwsubu_wv(mask,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_wv-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_wv-3.C new file mode 100644 index 00000000000..690bd5574ea --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_wv-3.C @@ -0,0 +1,216 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwsubu_wv(vuint16mf4_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vwsubu_wv(op1,op2,32); +} + + +vuint16mf2_t test___riscv_vwsubu_wv(vuint16mf2_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vwsubu_wv(op1,op2,32); +} + + +vuint16m1_t test___riscv_vwsubu_wv(vuint16m1_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vwsubu_wv(op1,op2,32); +} + + +vuint16m2_t test___riscv_vwsubu_wv(vuint16m2_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vwsubu_wv(op1,op2,32); +} + + +vuint16m4_t test___riscv_vwsubu_wv(vuint16m4_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vwsubu_wv(op1,op2,32); +} + + +vuint16m8_t test___riscv_vwsubu_wv(vuint16m8_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vwsubu_wv(op1,op2,32); +} + + +vuint32mf2_t test___riscv_vwsubu_wv(vuint32mf2_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vwsubu_wv(op1,op2,32); +} + + +vuint32m1_t test___riscv_vwsubu_wv(vuint32m1_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vwsubu_wv(op1,op2,32); +} + + +vuint32m2_t test___riscv_vwsubu_wv(vuint32m2_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vwsubu_wv(op1,op2,32); +} + + +vuint32m4_t test___riscv_vwsubu_wv(vuint32m4_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vwsubu_wv(op1,op2,32); +} + + +vuint32m8_t test___riscv_vwsubu_wv(vuint32m8_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vwsubu_wv(op1,op2,32); +} + + +vuint64m1_t test___riscv_vwsubu_wv(vuint64m1_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vwsubu_wv(op1,op2,32); +} + + +vuint64m2_t test___riscv_vwsubu_wv(vuint64m2_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vwsubu_wv(op1,op2,32); +} + + +vuint64m4_t test___riscv_vwsubu_wv(vuint64m4_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vwsubu_wv(op1,op2,32); +} + + +vuint64m8_t test___riscv_vwsubu_wv(vuint64m8_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vwsubu_wv(op1,op2,32); +} + + +vuint16mf4_t test___riscv_vwsubu_wv(vbool64_t mask,vuint16mf4_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vwsubu_wv(mask,op1,op2,32); +} + + +vuint16mf2_t test___riscv_vwsubu_wv(vbool32_t mask,vuint16mf2_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vwsubu_wv(mask,op1,op2,32); +} + + +vuint16m1_t test___riscv_vwsubu_wv(vbool16_t mask,vuint16m1_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vwsubu_wv(mask,op1,op2,32); +} + + +vuint16m2_t test___riscv_vwsubu_wv(vbool8_t mask,vuint16m2_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vwsubu_wv(mask,op1,op2,32); +} + + +vuint16m4_t test___riscv_vwsubu_wv(vbool4_t mask,vuint16m4_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vwsubu_wv(mask,op1,op2,32); +} + + +vuint16m8_t test___riscv_vwsubu_wv(vbool2_t mask,vuint16m8_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vwsubu_wv(mask,op1,op2,32); +} + + +vuint32mf2_t test___riscv_vwsubu_wv(vbool64_t mask,vuint32mf2_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vwsubu_wv(mask,op1,op2,32); +} + + +vuint32m1_t test___riscv_vwsubu_wv(vbool32_t mask,vuint32m1_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vwsubu_wv(mask,op1,op2,32); +} + + +vuint32m2_t test___riscv_vwsubu_wv(vbool16_t mask,vuint32m2_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vwsubu_wv(mask,op1,op2,32); +} + + +vuint32m4_t test___riscv_vwsubu_wv(vbool8_t mask,vuint32m4_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vwsubu_wv(mask,op1,op2,32); +} + + +vuint32m8_t test___riscv_vwsubu_wv(vbool4_t mask,vuint32m8_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vwsubu_wv(mask,op1,op2,32); +} + + +vuint64m1_t test___riscv_vwsubu_wv(vbool64_t mask,vuint64m1_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vwsubu_wv(mask,op1,op2,32); +} + + +vuint64m2_t test___riscv_vwsubu_wv(vbool32_t mask,vuint64m2_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vwsubu_wv(mask,op1,op2,32); +} + + +vuint64m4_t test___riscv_vwsubu_wv(vbool16_t mask,vuint64m4_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vwsubu_wv(mask,op1,op2,32); +} + + +vuint64m8_t test___riscv_vwsubu_wv(vbool8_t mask,vuint64m8_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vwsubu_wv(mask,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_wv_mu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_wv_mu-1.C new file mode 100644 index 00000000000..88220971cc3 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_wv_mu-1.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwsubu_wv_mu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_mu(mask,merge,op1,op2,vl); +} + + +vuint16mf2_t test___riscv_vwsubu_wv_mu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_mu(mask,merge,op1,op2,vl); +} + + +vuint16m1_t test___riscv_vwsubu_wv_mu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_mu(mask,merge,op1,op2,vl); +} + + +vuint16m2_t test___riscv_vwsubu_wv_mu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_mu(mask,merge,op1,op2,vl); +} + + +vuint16m4_t test___riscv_vwsubu_wv_mu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_mu(mask,merge,op1,op2,vl); +} + + +vuint16m8_t test___riscv_vwsubu_wv_mu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_mu(mask,merge,op1,op2,vl); +} + + +vuint32mf2_t test___riscv_vwsubu_wv_mu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_mu(mask,merge,op1,op2,vl); +} + + +vuint32m1_t test___riscv_vwsubu_wv_mu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_mu(mask,merge,op1,op2,vl); +} + + +vuint32m2_t test___riscv_vwsubu_wv_mu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_mu(mask,merge,op1,op2,vl); +} + + +vuint32m4_t test___riscv_vwsubu_wv_mu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_mu(mask,merge,op1,op2,vl); +} + + +vuint32m8_t test___riscv_vwsubu_wv_mu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_mu(mask,merge,op1,op2,vl); +} + + +vuint64m1_t test___riscv_vwsubu_wv_mu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_mu(mask,merge,op1,op2,vl); +} + + +vuint64m2_t test___riscv_vwsubu_wv_mu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_mu(mask,merge,op1,op2,vl); +} + + +vuint64m4_t test___riscv_vwsubu_wv_mu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_mu(mask,merge,op1,op2,vl); +} + + +vuint64m8_t test___riscv_vwsubu_wv_mu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_mu(mask,merge,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_wv_mu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_wv_mu-2.C new file mode 100644 index 00000000000..e0f90bb78fc --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_wv_mu-2.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwsubu_wv_mu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_mu(mask,merge,op1,op2,31); +} + + +vuint16mf2_t test___riscv_vwsubu_wv_mu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_mu(mask,merge,op1,op2,31); +} + + +vuint16m1_t test___riscv_vwsubu_wv_mu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_mu(mask,merge,op1,op2,31); +} + + +vuint16m2_t test___riscv_vwsubu_wv_mu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_mu(mask,merge,op1,op2,31); +} + + +vuint16m4_t test___riscv_vwsubu_wv_mu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_mu(mask,merge,op1,op2,31); +} + + +vuint16m8_t test___riscv_vwsubu_wv_mu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_mu(mask,merge,op1,op2,31); +} + + +vuint32mf2_t test___riscv_vwsubu_wv_mu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_mu(mask,merge,op1,op2,31); +} + + +vuint32m1_t test___riscv_vwsubu_wv_mu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_mu(mask,merge,op1,op2,31); +} + + +vuint32m2_t test___riscv_vwsubu_wv_mu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_mu(mask,merge,op1,op2,31); +} + + +vuint32m4_t test___riscv_vwsubu_wv_mu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_mu(mask,merge,op1,op2,31); +} + + +vuint32m8_t test___riscv_vwsubu_wv_mu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_mu(mask,merge,op1,op2,31); +} + + +vuint64m1_t test___riscv_vwsubu_wv_mu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_mu(mask,merge,op1,op2,31); +} + + +vuint64m2_t test___riscv_vwsubu_wv_mu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_mu(mask,merge,op1,op2,31); +} + + +vuint64m4_t test___riscv_vwsubu_wv_mu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_mu(mask,merge,op1,op2,31); +} + + +vuint64m8_t test___riscv_vwsubu_wv_mu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_mu(mask,merge,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_wv_mu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_wv_mu-3.C new file mode 100644 index 00000000000..ef711e04dba --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_wv_mu-3.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwsubu_wv_mu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_mu(mask,merge,op1,op2,32); +} + + +vuint16mf2_t test___riscv_vwsubu_wv_mu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_mu(mask,merge,op1,op2,32); +} + + +vuint16m1_t test___riscv_vwsubu_wv_mu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_mu(mask,merge,op1,op2,32); +} + + +vuint16m2_t test___riscv_vwsubu_wv_mu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_mu(mask,merge,op1,op2,32); +} + + +vuint16m4_t test___riscv_vwsubu_wv_mu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_mu(mask,merge,op1,op2,32); +} + + +vuint16m8_t test___riscv_vwsubu_wv_mu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_mu(mask,merge,op1,op2,32); +} + + +vuint32mf2_t test___riscv_vwsubu_wv_mu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_mu(mask,merge,op1,op2,32); +} + + +vuint32m1_t test___riscv_vwsubu_wv_mu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_mu(mask,merge,op1,op2,32); +} + + +vuint32m2_t test___riscv_vwsubu_wv_mu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_mu(mask,merge,op1,op2,32); +} + + +vuint32m4_t test___riscv_vwsubu_wv_mu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_mu(mask,merge,op1,op2,32); +} + + +vuint32m8_t test___riscv_vwsubu_wv_mu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_mu(mask,merge,op1,op2,32); +} + + +vuint64m1_t test___riscv_vwsubu_wv_mu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_mu(mask,merge,op1,op2,32); +} + + +vuint64m2_t test___riscv_vwsubu_wv_mu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_mu(mask,merge,op1,op2,32); +} + + +vuint64m4_t test___riscv_vwsubu_wv_mu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_mu(mask,merge,op1,op2,32); +} + + +vuint64m8_t test___riscv_vwsubu_wv_mu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_mu(mask,merge,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_wv_tu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_wv_tu-1.C new file mode 100644 index 00000000000..de41838b784 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_wv_tu-1.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwsubu_wv_tu(vuint16mf4_t merge,vuint16mf4_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_tu(merge,op1,op2,vl); +} + + +vuint16mf2_t test___riscv_vwsubu_wv_tu(vuint16mf2_t merge,vuint16mf2_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_tu(merge,op1,op2,vl); +} + + +vuint16m1_t test___riscv_vwsubu_wv_tu(vuint16m1_t merge,vuint16m1_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_tu(merge,op1,op2,vl); +} + + +vuint16m2_t test___riscv_vwsubu_wv_tu(vuint16m2_t merge,vuint16m2_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_tu(merge,op1,op2,vl); +} + + +vuint16m4_t test___riscv_vwsubu_wv_tu(vuint16m4_t merge,vuint16m4_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_tu(merge,op1,op2,vl); +} + + +vuint16m8_t test___riscv_vwsubu_wv_tu(vuint16m8_t merge,vuint16m8_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_tu(merge,op1,op2,vl); +} + + +vuint32mf2_t test___riscv_vwsubu_wv_tu(vuint32mf2_t merge,vuint32mf2_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_tu(merge,op1,op2,vl); +} + + +vuint32m1_t test___riscv_vwsubu_wv_tu(vuint32m1_t merge,vuint32m1_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_tu(merge,op1,op2,vl); +} + + +vuint32m2_t test___riscv_vwsubu_wv_tu(vuint32m2_t merge,vuint32m2_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_tu(merge,op1,op2,vl); +} + + +vuint32m4_t test___riscv_vwsubu_wv_tu(vuint32m4_t merge,vuint32m4_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_tu(merge,op1,op2,vl); +} + + +vuint32m8_t test___riscv_vwsubu_wv_tu(vuint32m8_t merge,vuint32m8_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_tu(merge,op1,op2,vl); +} + + +vuint64m1_t test___riscv_vwsubu_wv_tu(vuint64m1_t merge,vuint64m1_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_tu(merge,op1,op2,vl); +} + + +vuint64m2_t test___riscv_vwsubu_wv_tu(vuint64m2_t merge,vuint64m2_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_tu(merge,op1,op2,vl); +} + + +vuint64m4_t test___riscv_vwsubu_wv_tu(vuint64m4_t merge,vuint64m4_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_tu(merge,op1,op2,vl); +} + + +vuint64m8_t test___riscv_vwsubu_wv_tu(vuint64m8_t merge,vuint64m8_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_tu(merge,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_wv_tu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_wv_tu-2.C new file mode 100644 index 00000000000..47a0aa2dfea --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_wv_tu-2.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwsubu_wv_tu(vuint16mf4_t merge,vuint16mf4_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_tu(merge,op1,op2,31); +} + + +vuint16mf2_t test___riscv_vwsubu_wv_tu(vuint16mf2_t merge,vuint16mf2_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_tu(merge,op1,op2,31); +} + + +vuint16m1_t test___riscv_vwsubu_wv_tu(vuint16m1_t merge,vuint16m1_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_tu(merge,op1,op2,31); +} + + +vuint16m2_t test___riscv_vwsubu_wv_tu(vuint16m2_t merge,vuint16m2_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_tu(merge,op1,op2,31); +} + + +vuint16m4_t test___riscv_vwsubu_wv_tu(vuint16m4_t merge,vuint16m4_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_tu(merge,op1,op2,31); +} + + +vuint16m8_t test___riscv_vwsubu_wv_tu(vuint16m8_t merge,vuint16m8_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_tu(merge,op1,op2,31); +} + + +vuint32mf2_t test___riscv_vwsubu_wv_tu(vuint32mf2_t merge,vuint32mf2_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_tu(merge,op1,op2,31); +} + + +vuint32m1_t test___riscv_vwsubu_wv_tu(vuint32m1_t merge,vuint32m1_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_tu(merge,op1,op2,31); +} + + +vuint32m2_t test___riscv_vwsubu_wv_tu(vuint32m2_t merge,vuint32m2_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_tu(merge,op1,op2,31); +} + + +vuint32m4_t test___riscv_vwsubu_wv_tu(vuint32m4_t merge,vuint32m4_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_tu(merge,op1,op2,31); +} + + +vuint32m8_t test___riscv_vwsubu_wv_tu(vuint32m8_t merge,vuint32m8_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_tu(merge,op1,op2,31); +} + + +vuint64m1_t test___riscv_vwsubu_wv_tu(vuint64m1_t merge,vuint64m1_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_tu(merge,op1,op2,31); +} + + +vuint64m2_t test___riscv_vwsubu_wv_tu(vuint64m2_t merge,vuint64m2_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_tu(merge,op1,op2,31); +} + + +vuint64m4_t test___riscv_vwsubu_wv_tu(vuint64m4_t merge,vuint64m4_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_tu(merge,op1,op2,31); +} + + +vuint64m8_t test___riscv_vwsubu_wv_tu(vuint64m8_t merge,vuint64m8_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_tu(merge,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_wv_tu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_wv_tu-3.C new file mode 100644 index 00000000000..84f184b1fac --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_wv_tu-3.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwsubu_wv_tu(vuint16mf4_t merge,vuint16mf4_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_tu(merge,op1,op2,32); +} + + +vuint16mf2_t test___riscv_vwsubu_wv_tu(vuint16mf2_t merge,vuint16mf2_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_tu(merge,op1,op2,32); +} + + +vuint16m1_t test___riscv_vwsubu_wv_tu(vuint16m1_t merge,vuint16m1_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_tu(merge,op1,op2,32); +} + + +vuint16m2_t test___riscv_vwsubu_wv_tu(vuint16m2_t merge,vuint16m2_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_tu(merge,op1,op2,32); +} + + +vuint16m4_t test___riscv_vwsubu_wv_tu(vuint16m4_t merge,vuint16m4_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_tu(merge,op1,op2,32); +} + + +vuint16m8_t test___riscv_vwsubu_wv_tu(vuint16m8_t merge,vuint16m8_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_tu(merge,op1,op2,32); +} + + +vuint32mf2_t test___riscv_vwsubu_wv_tu(vuint32mf2_t merge,vuint32mf2_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_tu(merge,op1,op2,32); +} + + +vuint32m1_t test___riscv_vwsubu_wv_tu(vuint32m1_t merge,vuint32m1_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_tu(merge,op1,op2,32); +} + + +vuint32m2_t test___riscv_vwsubu_wv_tu(vuint32m2_t merge,vuint32m2_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_tu(merge,op1,op2,32); +} + + +vuint32m4_t test___riscv_vwsubu_wv_tu(vuint32m4_t merge,vuint32m4_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_tu(merge,op1,op2,32); +} + + +vuint32m8_t test___riscv_vwsubu_wv_tu(vuint32m8_t merge,vuint32m8_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_tu(merge,op1,op2,32); +} + + +vuint64m1_t test___riscv_vwsubu_wv_tu(vuint64m1_t merge,vuint64m1_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_tu(merge,op1,op2,32); +} + + +vuint64m2_t test___riscv_vwsubu_wv_tu(vuint64m2_t merge,vuint64m2_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_tu(merge,op1,op2,32); +} + + +vuint64m4_t test___riscv_vwsubu_wv_tu(vuint64m4_t merge,vuint64m4_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_tu(merge,op1,op2,32); +} + + +vuint64m8_t test___riscv_vwsubu_wv_tu(vuint64m8_t merge,vuint64m8_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_tu(merge,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_wv_tum-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_wv_tum-1.C new file mode 100644 index 00000000000..dcceb9cb8d9 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_wv_tum-1.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwsubu_wv_tum(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_tum(mask,merge,op1,op2,vl); +} + + +vuint16mf2_t test___riscv_vwsubu_wv_tum(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_tum(mask,merge,op1,op2,vl); +} + + +vuint16m1_t test___riscv_vwsubu_wv_tum(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_tum(mask,merge,op1,op2,vl); +} + + +vuint16m2_t test___riscv_vwsubu_wv_tum(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_tum(mask,merge,op1,op2,vl); +} + + +vuint16m4_t test___riscv_vwsubu_wv_tum(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_tum(mask,merge,op1,op2,vl); +} + + +vuint16m8_t test___riscv_vwsubu_wv_tum(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_tum(mask,merge,op1,op2,vl); +} + + +vuint32mf2_t test___riscv_vwsubu_wv_tum(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_tum(mask,merge,op1,op2,vl); +} + + +vuint32m1_t test___riscv_vwsubu_wv_tum(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_tum(mask,merge,op1,op2,vl); +} + + +vuint32m2_t test___riscv_vwsubu_wv_tum(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_tum(mask,merge,op1,op2,vl); +} + + +vuint32m4_t test___riscv_vwsubu_wv_tum(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_tum(mask,merge,op1,op2,vl); +} + + +vuint32m8_t test___riscv_vwsubu_wv_tum(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_tum(mask,merge,op1,op2,vl); +} + + +vuint64m1_t test___riscv_vwsubu_wv_tum(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_tum(mask,merge,op1,op2,vl); +} + + +vuint64m2_t test___riscv_vwsubu_wv_tum(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_tum(mask,merge,op1,op2,vl); +} + + +vuint64m4_t test___riscv_vwsubu_wv_tum(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_tum(mask,merge,op1,op2,vl); +} + + +vuint64m8_t test___riscv_vwsubu_wv_tum(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_tum(mask,merge,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_wv_tum-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_wv_tum-2.C new file mode 100644 index 00000000000..64b0a4f060f --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_wv_tum-2.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwsubu_wv_tum(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_tum(mask,merge,op1,op2,31); +} + + +vuint16mf2_t test___riscv_vwsubu_wv_tum(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_tum(mask,merge,op1,op2,31); +} + + +vuint16m1_t test___riscv_vwsubu_wv_tum(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_tum(mask,merge,op1,op2,31); +} + + +vuint16m2_t test___riscv_vwsubu_wv_tum(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_tum(mask,merge,op1,op2,31); +} + + +vuint16m4_t test___riscv_vwsubu_wv_tum(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_tum(mask,merge,op1,op2,31); +} + + +vuint16m8_t test___riscv_vwsubu_wv_tum(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_tum(mask,merge,op1,op2,31); +} + + +vuint32mf2_t test___riscv_vwsubu_wv_tum(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_tum(mask,merge,op1,op2,31); +} + + +vuint32m1_t test___riscv_vwsubu_wv_tum(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_tum(mask,merge,op1,op2,31); +} + + +vuint32m2_t test___riscv_vwsubu_wv_tum(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_tum(mask,merge,op1,op2,31); +} + + +vuint32m4_t test___riscv_vwsubu_wv_tum(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_tum(mask,merge,op1,op2,31); +} + + +vuint32m8_t test___riscv_vwsubu_wv_tum(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_tum(mask,merge,op1,op2,31); +} + + +vuint64m1_t test___riscv_vwsubu_wv_tum(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_tum(mask,merge,op1,op2,31); +} + + +vuint64m2_t test___riscv_vwsubu_wv_tum(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_tum(mask,merge,op1,op2,31); +} + + +vuint64m4_t test___riscv_vwsubu_wv_tum(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_tum(mask,merge,op1,op2,31); +} + + +vuint64m8_t test___riscv_vwsubu_wv_tum(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_tum(mask,merge,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_wv_tum-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_wv_tum-3.C new file mode 100644 index 00000000000..722beb70ac6 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_wv_tum-3.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwsubu_wv_tum(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_tum(mask,merge,op1,op2,32); +} + + +vuint16mf2_t test___riscv_vwsubu_wv_tum(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_tum(mask,merge,op1,op2,32); +} + + +vuint16m1_t test___riscv_vwsubu_wv_tum(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_tum(mask,merge,op1,op2,32); +} + + +vuint16m2_t test___riscv_vwsubu_wv_tum(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_tum(mask,merge,op1,op2,32); +} + + +vuint16m4_t test___riscv_vwsubu_wv_tum(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_tum(mask,merge,op1,op2,32); +} + + +vuint16m8_t test___riscv_vwsubu_wv_tum(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_tum(mask,merge,op1,op2,32); +} + + +vuint32mf2_t test___riscv_vwsubu_wv_tum(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_tum(mask,merge,op1,op2,32); +} + + +vuint32m1_t test___riscv_vwsubu_wv_tum(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_tum(mask,merge,op1,op2,32); +} + + +vuint32m2_t test___riscv_vwsubu_wv_tum(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_tum(mask,merge,op1,op2,32); +} + + +vuint32m4_t test___riscv_vwsubu_wv_tum(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_tum(mask,merge,op1,op2,32); +} + + +vuint32m8_t test___riscv_vwsubu_wv_tum(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_tum(mask,merge,op1,op2,32); +} + + +vuint64m1_t test___riscv_vwsubu_wv_tum(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_tum(mask,merge,op1,op2,32); +} + + +vuint64m2_t test___riscv_vwsubu_wv_tum(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_tum(mask,merge,op1,op2,32); +} + + +vuint64m4_t test___riscv_vwsubu_wv_tum(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_tum(mask,merge,op1,op2,32); +} + + +vuint64m8_t test___riscv_vwsubu_wv_tum(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_tum(mask,merge,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_wv_tumu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_wv_tumu-1.C new file mode 100644 index 00000000000..17cfe6fbbfc --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_wv_tumu-1.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwsubu_wv_tumu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_tumu(mask,merge,op1,op2,vl); +} + + +vuint16mf2_t test___riscv_vwsubu_wv_tumu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_tumu(mask,merge,op1,op2,vl); +} + + +vuint16m1_t test___riscv_vwsubu_wv_tumu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_tumu(mask,merge,op1,op2,vl); +} + + +vuint16m2_t test___riscv_vwsubu_wv_tumu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_tumu(mask,merge,op1,op2,vl); +} + + +vuint16m4_t test___riscv_vwsubu_wv_tumu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_tumu(mask,merge,op1,op2,vl); +} + + +vuint16m8_t test___riscv_vwsubu_wv_tumu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_tumu(mask,merge,op1,op2,vl); +} + + +vuint32mf2_t test___riscv_vwsubu_wv_tumu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_tumu(mask,merge,op1,op2,vl); +} + + +vuint32m1_t test___riscv_vwsubu_wv_tumu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_tumu(mask,merge,op1,op2,vl); +} + + +vuint32m2_t test___riscv_vwsubu_wv_tumu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_tumu(mask,merge,op1,op2,vl); +} + + +vuint32m4_t test___riscv_vwsubu_wv_tumu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_tumu(mask,merge,op1,op2,vl); +} + + +vuint32m8_t test___riscv_vwsubu_wv_tumu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_tumu(mask,merge,op1,op2,vl); +} + + +vuint64m1_t test___riscv_vwsubu_wv_tumu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_tumu(mask,merge,op1,op2,vl); +} + + +vuint64m2_t test___riscv_vwsubu_wv_tumu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_tumu(mask,merge,op1,op2,vl); +} + + +vuint64m4_t test___riscv_vwsubu_wv_tumu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_tumu(mask,merge,op1,op2,vl); +} + + +vuint64m8_t test___riscv_vwsubu_wv_tumu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_tumu(mask,merge,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_wv_tumu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_wv_tumu-2.C new file mode 100644 index 00000000000..93141147d7e --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_wv_tumu-2.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwsubu_wv_tumu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_tumu(mask,merge,op1,op2,31); +} + + +vuint16mf2_t test___riscv_vwsubu_wv_tumu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_tumu(mask,merge,op1,op2,31); +} + + +vuint16m1_t test___riscv_vwsubu_wv_tumu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_tumu(mask,merge,op1,op2,31); +} + + +vuint16m2_t test___riscv_vwsubu_wv_tumu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_tumu(mask,merge,op1,op2,31); +} + + +vuint16m4_t test___riscv_vwsubu_wv_tumu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_tumu(mask,merge,op1,op2,31); +} + + +vuint16m8_t test___riscv_vwsubu_wv_tumu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_tumu(mask,merge,op1,op2,31); +} + + +vuint32mf2_t test___riscv_vwsubu_wv_tumu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_tumu(mask,merge,op1,op2,31); +} + + +vuint32m1_t test___riscv_vwsubu_wv_tumu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_tumu(mask,merge,op1,op2,31); +} + + +vuint32m2_t test___riscv_vwsubu_wv_tumu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_tumu(mask,merge,op1,op2,31); +} + + +vuint32m4_t test___riscv_vwsubu_wv_tumu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_tumu(mask,merge,op1,op2,31); +} + + +vuint32m8_t test___riscv_vwsubu_wv_tumu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_tumu(mask,merge,op1,op2,31); +} + + +vuint64m1_t test___riscv_vwsubu_wv_tumu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_tumu(mask,merge,op1,op2,31); +} + + +vuint64m2_t test___riscv_vwsubu_wv_tumu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_tumu(mask,merge,op1,op2,31); +} + + +vuint64m4_t test___riscv_vwsubu_wv_tumu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_tumu(mask,merge,op1,op2,31); +} + + +vuint64m8_t test___riscv_vwsubu_wv_tumu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_tumu(mask,merge,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_wv_tumu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_wv_tumu-3.C new file mode 100644 index 00000000000..f207cfd9dea --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_wv_tumu-3.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwsubu_wv_tumu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_tumu(mask,merge,op1,op2,32); +} + + +vuint16mf2_t test___riscv_vwsubu_wv_tumu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_tumu(mask,merge,op1,op2,32); +} + + +vuint16m1_t test___riscv_vwsubu_wv_tumu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_tumu(mask,merge,op1,op2,32); +} + + +vuint16m2_t test___riscv_vwsubu_wv_tumu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_tumu(mask,merge,op1,op2,32); +} + + +vuint16m4_t test___riscv_vwsubu_wv_tumu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_tumu(mask,merge,op1,op2,32); +} + + +vuint16m8_t test___riscv_vwsubu_wv_tumu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_tumu(mask,merge,op1,op2,32); +} + + +vuint32mf2_t test___riscv_vwsubu_wv_tumu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_tumu(mask,merge,op1,op2,32); +} + + +vuint32m1_t test___riscv_vwsubu_wv_tumu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_tumu(mask,merge,op1,op2,32); +} + + +vuint32m2_t test___riscv_vwsubu_wv_tumu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_tumu(mask,merge,op1,op2,32); +} + + +vuint32m4_t test___riscv_vwsubu_wv_tumu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_tumu(mask,merge,op1,op2,32); +} + + +vuint32m8_t test___riscv_vwsubu_wv_tumu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_tumu(mask,merge,op1,op2,32); +} + + +vuint64m1_t test___riscv_vwsubu_wv_tumu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_tumu(mask,merge,op1,op2,32); +} + + +vuint64m2_t test___riscv_vwsubu_wv_tumu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_tumu(mask,merge,op1,op2,32); +} + + +vuint64m4_t test___riscv_vwsubu_wv_tumu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_tumu(mask,merge,op1,op2,32); +} + + +vuint64m8_t test___riscv_vwsubu_wv_tumu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_tumu(mask,merge,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_wx-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_wx-1.C new file mode 100644 index 00000000000..817fcb09ffc --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_wx-1.C @@ -0,0 +1,216 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwsubu_wx(vuint16mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_wx(op1,0xAA,vl); +} + + +vuint16mf2_t test___riscv_vwsubu_wx(vuint16mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_wx(op1,0xAA,vl); +} + + +vuint16m1_t test___riscv_vwsubu_wx(vuint16m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_wx(op1,0xAA,vl); +} + + +vuint16m2_t test___riscv_vwsubu_wx(vuint16m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_wx(op1,0xAA,vl); +} + + +vuint16m4_t test___riscv_vwsubu_wx(vuint16m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_wx(op1,0xAA,vl); +} + + +vuint16m8_t test___riscv_vwsubu_wx(vuint16m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_wx(op1,0xAA,vl); +} + + +vuint32mf2_t test___riscv_vwsubu_wx(vuint32mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_wx(op1,0xAA,vl); +} + + +vuint32m1_t test___riscv_vwsubu_wx(vuint32m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_wx(op1,0xAA,vl); +} + + +vuint32m2_t test___riscv_vwsubu_wx(vuint32m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_wx(op1,0xAA,vl); +} + + +vuint32m4_t test___riscv_vwsubu_wx(vuint32m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_wx(op1,0xAA,vl); +} + + +vuint32m8_t test___riscv_vwsubu_wx(vuint32m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_wx(op1,0xAA,vl); +} + + +vuint64m1_t test___riscv_vwsubu_wx(vuint64m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_wx(op1,0xAA,vl); +} + + +vuint64m2_t test___riscv_vwsubu_wx(vuint64m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_wx(op1,0xAA,vl); +} + + +vuint64m4_t test___riscv_vwsubu_wx(vuint64m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_wx(op1,0xAA,vl); +} + + +vuint64m8_t test___riscv_vwsubu_wx(vuint64m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_wx(op1,0xAA,vl); +} + + +vuint16mf4_t test___riscv_vwsubu_wx(vbool64_t mask,vuint16mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_wx(mask,op1,0xAA,vl); +} + + +vuint16mf2_t test___riscv_vwsubu_wx(vbool32_t mask,vuint16mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_wx(mask,op1,0xAA,vl); +} + + +vuint16m1_t test___riscv_vwsubu_wx(vbool16_t mask,vuint16m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_wx(mask,op1,0xAA,vl); +} + + +vuint16m2_t test___riscv_vwsubu_wx(vbool8_t mask,vuint16m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_wx(mask,op1,0xAA,vl); +} + + +vuint16m4_t test___riscv_vwsubu_wx(vbool4_t mask,vuint16m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_wx(mask,op1,0xAA,vl); +} + + +vuint16m8_t test___riscv_vwsubu_wx(vbool2_t mask,vuint16m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_wx(mask,op1,0xAA,vl); +} + + +vuint32mf2_t test___riscv_vwsubu_wx(vbool64_t mask,vuint32mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_wx(mask,op1,0xAA,vl); +} + + +vuint32m1_t test___riscv_vwsubu_wx(vbool32_t mask,vuint32m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_wx(mask,op1,0xAA,vl); +} + + +vuint32m2_t test___riscv_vwsubu_wx(vbool16_t mask,vuint32m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_wx(mask,op1,0xAA,vl); +} + + +vuint32m4_t test___riscv_vwsubu_wx(vbool8_t mask,vuint32m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_wx(mask,op1,0xAA,vl); +} + + +vuint32m8_t test___riscv_vwsubu_wx(vbool4_t mask,vuint32m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_wx(mask,op1,0xAA,vl); +} + + +vuint64m1_t test___riscv_vwsubu_wx(vbool64_t mask,vuint64m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_wx(mask,op1,0xAA,vl); +} + + +vuint64m2_t test___riscv_vwsubu_wx(vbool32_t mask,vuint64m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_wx(mask,op1,0xAA,vl); +} + + +vuint64m4_t test___riscv_vwsubu_wx(vbool16_t mask,vuint64m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_wx(mask,op1,0xAA,vl); +} + + +vuint64m8_t test___riscv_vwsubu_wx(vbool8_t mask,vuint64m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_wx(mask,op1,0xAA,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_wx-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_wx-2.C new file mode 100644 index 00000000000..3b4e0e0b6fe --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_wx-2.C @@ -0,0 +1,216 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwsubu_wx(vuint16mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_wx(op1,0xAA,31); +} + + +vuint16mf2_t test___riscv_vwsubu_wx(vuint16mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_wx(op1,0xAA,31); +} + + +vuint16m1_t test___riscv_vwsubu_wx(vuint16m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_wx(op1,0xAA,31); +} + + +vuint16m2_t test___riscv_vwsubu_wx(vuint16m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_wx(op1,0xAA,31); +} + + +vuint16m4_t test___riscv_vwsubu_wx(vuint16m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_wx(op1,0xAA,31); +} + + +vuint16m8_t test___riscv_vwsubu_wx(vuint16m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_wx(op1,0xAA,31); +} + + +vuint32mf2_t test___riscv_vwsubu_wx(vuint32mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_wx(op1,0xAA,31); +} + + +vuint32m1_t test___riscv_vwsubu_wx(vuint32m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_wx(op1,0xAA,31); +} + + +vuint32m2_t test___riscv_vwsubu_wx(vuint32m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_wx(op1,0xAA,31); +} + + +vuint32m4_t test___riscv_vwsubu_wx(vuint32m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_wx(op1,0xAA,31); +} + + +vuint32m8_t test___riscv_vwsubu_wx(vuint32m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_wx(op1,0xAA,31); +} + + +vuint64m1_t test___riscv_vwsubu_wx(vuint64m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_wx(op1,0xAA,31); +} + + +vuint64m2_t test___riscv_vwsubu_wx(vuint64m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_wx(op1,0xAA,31); +} + + +vuint64m4_t test___riscv_vwsubu_wx(vuint64m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_wx(op1,0xAA,31); +} + + +vuint64m8_t test___riscv_vwsubu_wx(vuint64m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_wx(op1,0xAA,31); +} + + +vuint16mf4_t test___riscv_vwsubu_wx(vbool64_t mask,vuint16mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_wx(mask,op1,0xAA,31); +} + + +vuint16mf2_t test___riscv_vwsubu_wx(vbool32_t mask,vuint16mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_wx(mask,op1,0xAA,31); +} + + +vuint16m1_t test___riscv_vwsubu_wx(vbool16_t mask,vuint16m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_wx(mask,op1,0xAA,31); +} + + +vuint16m2_t test___riscv_vwsubu_wx(vbool8_t mask,vuint16m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_wx(mask,op1,0xAA,31); +} + + +vuint16m4_t test___riscv_vwsubu_wx(vbool4_t mask,vuint16m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_wx(mask,op1,0xAA,31); +} + + +vuint16m8_t test___riscv_vwsubu_wx(vbool2_t mask,vuint16m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_wx(mask,op1,0xAA,31); +} + + +vuint32mf2_t test___riscv_vwsubu_wx(vbool64_t mask,vuint32mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_wx(mask,op1,0xAA,31); +} + + +vuint32m1_t test___riscv_vwsubu_wx(vbool32_t mask,vuint32m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_wx(mask,op1,0xAA,31); +} + + +vuint32m2_t test___riscv_vwsubu_wx(vbool16_t mask,vuint32m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_wx(mask,op1,0xAA,31); +} + + +vuint32m4_t test___riscv_vwsubu_wx(vbool8_t mask,vuint32m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_wx(mask,op1,0xAA,31); +} + + +vuint32m8_t test___riscv_vwsubu_wx(vbool4_t mask,vuint32m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_wx(mask,op1,0xAA,31); +} + + +vuint64m1_t test___riscv_vwsubu_wx(vbool64_t mask,vuint64m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_wx(mask,op1,0xAA,31); +} + + +vuint64m2_t test___riscv_vwsubu_wx(vbool32_t mask,vuint64m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_wx(mask,op1,0xAA,31); +} + + +vuint64m4_t test___riscv_vwsubu_wx(vbool16_t mask,vuint64m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_wx(mask,op1,0xAA,31); +} + + +vuint64m8_t test___riscv_vwsubu_wx(vbool8_t mask,vuint64m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_wx(mask,op1,0xAA,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_wx-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_wx-3.C new file mode 100644 index 00000000000..57df16f6ad2 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_wx-3.C @@ -0,0 +1,216 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwsubu_wx(vuint16mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_wx(op1,0xAA,32); +} + + +vuint16mf2_t test___riscv_vwsubu_wx(vuint16mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_wx(op1,0xAA,32); +} + + +vuint16m1_t test___riscv_vwsubu_wx(vuint16m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_wx(op1,0xAA,32); +} + + +vuint16m2_t test___riscv_vwsubu_wx(vuint16m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_wx(op1,0xAA,32); +} + + +vuint16m4_t test___riscv_vwsubu_wx(vuint16m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_wx(op1,0xAA,32); +} + + +vuint16m8_t test___riscv_vwsubu_wx(vuint16m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_wx(op1,0xAA,32); +} + + +vuint32mf2_t test___riscv_vwsubu_wx(vuint32mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_wx(op1,0xAA,32); +} + + +vuint32m1_t test___riscv_vwsubu_wx(vuint32m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_wx(op1,0xAA,32); +} + + +vuint32m2_t test___riscv_vwsubu_wx(vuint32m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_wx(op1,0xAA,32); +} + + +vuint32m4_t test___riscv_vwsubu_wx(vuint32m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_wx(op1,0xAA,32); +} + + +vuint32m8_t test___riscv_vwsubu_wx(vuint32m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_wx(op1,0xAA,32); +} + + +vuint64m1_t test___riscv_vwsubu_wx(vuint64m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_wx(op1,0xAA,32); +} + + +vuint64m2_t test___riscv_vwsubu_wx(vuint64m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_wx(op1,0xAA,32); +} + + +vuint64m4_t test___riscv_vwsubu_wx(vuint64m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_wx(op1,0xAA,32); +} + + +vuint64m8_t test___riscv_vwsubu_wx(vuint64m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_wx(op1,0xAA,32); +} + + +vuint16mf4_t test___riscv_vwsubu_wx(vbool64_t mask,vuint16mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_wx(mask,op1,0xAA,32); +} + + +vuint16mf2_t test___riscv_vwsubu_wx(vbool32_t mask,vuint16mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_wx(mask,op1,0xAA,32); +} + + +vuint16m1_t test___riscv_vwsubu_wx(vbool16_t mask,vuint16m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_wx(mask,op1,0xAA,32); +} + + +vuint16m2_t test___riscv_vwsubu_wx(vbool8_t mask,vuint16m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_wx(mask,op1,0xAA,32); +} + + +vuint16m4_t test___riscv_vwsubu_wx(vbool4_t mask,vuint16m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_wx(mask,op1,0xAA,32); +} + + +vuint16m8_t test___riscv_vwsubu_wx(vbool2_t mask,vuint16m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_wx(mask,op1,0xAA,32); +} + + +vuint32mf2_t test___riscv_vwsubu_wx(vbool64_t mask,vuint32mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_wx(mask,op1,0xAA,32); +} + + +vuint32m1_t test___riscv_vwsubu_wx(vbool32_t mask,vuint32m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_wx(mask,op1,0xAA,32); +} + + +vuint32m2_t test___riscv_vwsubu_wx(vbool16_t mask,vuint32m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_wx(mask,op1,0xAA,32); +} + + +vuint32m4_t test___riscv_vwsubu_wx(vbool8_t mask,vuint32m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_wx(mask,op1,0xAA,32); +} + + +vuint32m8_t test___riscv_vwsubu_wx(vbool4_t mask,vuint32m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_wx(mask,op1,0xAA,32); +} + + +vuint64m1_t test___riscv_vwsubu_wx(vbool64_t mask,vuint64m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_wx(mask,op1,0xAA,32); +} + + +vuint64m2_t test___riscv_vwsubu_wx(vbool32_t mask,vuint64m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_wx(mask,op1,0xAA,32); +} + + +vuint64m4_t test___riscv_vwsubu_wx(vbool16_t mask,vuint64m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_wx(mask,op1,0xAA,32); +} + + +vuint64m8_t test___riscv_vwsubu_wx(vbool8_t mask,vuint64m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_wx(mask,op1,0xAA,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_wx_mu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_wx_mu-1.C new file mode 100644 index 00000000000..f050d06c202 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_wx_mu-1.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwsubu_wx_mu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_mu(mask,merge,op1,0xAA,vl); +} + + +vuint16mf2_t test___riscv_vwsubu_wx_mu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_mu(mask,merge,op1,0xAA,vl); +} + + +vuint16m1_t test___riscv_vwsubu_wx_mu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_mu(mask,merge,op1,0xAA,vl); +} + + +vuint16m2_t test___riscv_vwsubu_wx_mu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_mu(mask,merge,op1,0xAA,vl); +} + + +vuint16m4_t test___riscv_vwsubu_wx_mu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_mu(mask,merge,op1,0xAA,vl); +} + + +vuint16m8_t test___riscv_vwsubu_wx_mu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_mu(mask,merge,op1,0xAA,vl); +} + + +vuint32mf2_t test___riscv_vwsubu_wx_mu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_mu(mask,merge,op1,0xAA,vl); +} + + +vuint32m1_t test___riscv_vwsubu_wx_mu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_mu(mask,merge,op1,0xAA,vl); +} + + +vuint32m2_t test___riscv_vwsubu_wx_mu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_mu(mask,merge,op1,0xAA,vl); +} + + +vuint32m4_t test___riscv_vwsubu_wx_mu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_mu(mask,merge,op1,0xAA,vl); +} + + +vuint32m8_t test___riscv_vwsubu_wx_mu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_mu(mask,merge,op1,0xAA,vl); +} + + +vuint64m1_t test___riscv_vwsubu_wx_mu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_mu(mask,merge,op1,0xAA,vl); +} + + +vuint64m2_t test___riscv_vwsubu_wx_mu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_mu(mask,merge,op1,0xAA,vl); +} + + +vuint64m4_t test___riscv_vwsubu_wx_mu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_mu(mask,merge,op1,0xAA,vl); +} + + +vuint64m8_t test___riscv_vwsubu_wx_mu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_mu(mask,merge,op1,0xAA,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_wx_mu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_wx_mu-2.C new file mode 100644 index 00000000000..ea2a68eee6b --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_wx_mu-2.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwsubu_wx_mu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_mu(mask,merge,op1,0xAA,31); +} + + +vuint16mf2_t test___riscv_vwsubu_wx_mu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_mu(mask,merge,op1,0xAA,31); +} + + +vuint16m1_t test___riscv_vwsubu_wx_mu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_mu(mask,merge,op1,0xAA,31); +} + + +vuint16m2_t test___riscv_vwsubu_wx_mu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_mu(mask,merge,op1,0xAA,31); +} + + +vuint16m4_t test___riscv_vwsubu_wx_mu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_mu(mask,merge,op1,0xAA,31); +} + + +vuint16m8_t test___riscv_vwsubu_wx_mu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_mu(mask,merge,op1,0xAA,31); +} + + +vuint32mf2_t test___riscv_vwsubu_wx_mu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_mu(mask,merge,op1,0xAA,31); +} + + +vuint32m1_t test___riscv_vwsubu_wx_mu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_mu(mask,merge,op1,0xAA,31); +} + + +vuint32m2_t test___riscv_vwsubu_wx_mu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_mu(mask,merge,op1,0xAA,31); +} + + +vuint32m4_t test___riscv_vwsubu_wx_mu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_mu(mask,merge,op1,0xAA,31); +} + + +vuint32m8_t test___riscv_vwsubu_wx_mu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_mu(mask,merge,op1,0xAA,31); +} + + +vuint64m1_t test___riscv_vwsubu_wx_mu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_mu(mask,merge,op1,0xAA,31); +} + + +vuint64m2_t test___riscv_vwsubu_wx_mu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_mu(mask,merge,op1,0xAA,31); +} + + +vuint64m4_t test___riscv_vwsubu_wx_mu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_mu(mask,merge,op1,0xAA,31); +} + + +vuint64m8_t test___riscv_vwsubu_wx_mu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_mu(mask,merge,op1,0xAA,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_wx_mu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_wx_mu-3.C new file mode 100644 index 00000000000..f8659923b16 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_wx_mu-3.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwsubu_wx_mu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_mu(mask,merge,op1,0xAA,32); +} + + +vuint16mf2_t test___riscv_vwsubu_wx_mu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_mu(mask,merge,op1,0xAA,32); +} + + +vuint16m1_t test___riscv_vwsubu_wx_mu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_mu(mask,merge,op1,0xAA,32); +} + + +vuint16m2_t test___riscv_vwsubu_wx_mu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_mu(mask,merge,op1,0xAA,32); +} + + +vuint16m4_t test___riscv_vwsubu_wx_mu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_mu(mask,merge,op1,0xAA,32); +} + + +vuint16m8_t test___riscv_vwsubu_wx_mu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_mu(mask,merge,op1,0xAA,32); +} + + +vuint32mf2_t test___riscv_vwsubu_wx_mu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_mu(mask,merge,op1,0xAA,32); +} + + +vuint32m1_t test___riscv_vwsubu_wx_mu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_mu(mask,merge,op1,0xAA,32); +} + + +vuint32m2_t test___riscv_vwsubu_wx_mu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_mu(mask,merge,op1,0xAA,32); +} + + +vuint32m4_t test___riscv_vwsubu_wx_mu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_mu(mask,merge,op1,0xAA,32); +} + + +vuint32m8_t test___riscv_vwsubu_wx_mu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_mu(mask,merge,op1,0xAA,32); +} + + +vuint64m1_t test___riscv_vwsubu_wx_mu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_mu(mask,merge,op1,0xAA,32); +} + + +vuint64m2_t test___riscv_vwsubu_wx_mu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_mu(mask,merge,op1,0xAA,32); +} + + +vuint64m4_t test___riscv_vwsubu_wx_mu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_mu(mask,merge,op1,0xAA,32); +} + + +vuint64m8_t test___riscv_vwsubu_wx_mu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_mu(mask,merge,op1,0xAA,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_wx_tu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_wx_tu-1.C new file mode 100644 index 00000000000..ba41ae50c50 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_wx_tu-1.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwsubu_wx_tu(vuint16mf4_t merge,vuint16mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_tu(merge,op1,0xAA,vl); +} + + +vuint16mf2_t test___riscv_vwsubu_wx_tu(vuint16mf2_t merge,vuint16mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_tu(merge,op1,0xAA,vl); +} + + +vuint16m1_t test___riscv_vwsubu_wx_tu(vuint16m1_t merge,vuint16m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_tu(merge,op1,0xAA,vl); +} + + +vuint16m2_t test___riscv_vwsubu_wx_tu(vuint16m2_t merge,vuint16m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_tu(merge,op1,0xAA,vl); +} + + +vuint16m4_t test___riscv_vwsubu_wx_tu(vuint16m4_t merge,vuint16m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_tu(merge,op1,0xAA,vl); +} + + +vuint16m8_t test___riscv_vwsubu_wx_tu(vuint16m8_t merge,vuint16m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_tu(merge,op1,0xAA,vl); +} + + +vuint32mf2_t test___riscv_vwsubu_wx_tu(vuint32mf2_t merge,vuint32mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_tu(merge,op1,0xAA,vl); +} + + +vuint32m1_t test___riscv_vwsubu_wx_tu(vuint32m1_t merge,vuint32m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_tu(merge,op1,0xAA,vl); +} + + +vuint32m2_t test___riscv_vwsubu_wx_tu(vuint32m2_t merge,vuint32m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_tu(merge,op1,0xAA,vl); +} + + +vuint32m4_t test___riscv_vwsubu_wx_tu(vuint32m4_t merge,vuint32m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_tu(merge,op1,0xAA,vl); +} + + +vuint32m8_t test___riscv_vwsubu_wx_tu(vuint32m8_t merge,vuint32m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_tu(merge,op1,0xAA,vl); +} + + +vuint64m1_t test___riscv_vwsubu_wx_tu(vuint64m1_t merge,vuint64m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_tu(merge,op1,0xAA,vl); +} + + +vuint64m2_t test___riscv_vwsubu_wx_tu(vuint64m2_t merge,vuint64m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_tu(merge,op1,0xAA,vl); +} + + +vuint64m4_t test___riscv_vwsubu_wx_tu(vuint64m4_t merge,vuint64m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_tu(merge,op1,0xAA,vl); +} + + +vuint64m8_t test___riscv_vwsubu_wx_tu(vuint64m8_t merge,vuint64m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_tu(merge,op1,0xAA,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_wx_tu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_wx_tu-2.C new file mode 100644 index 00000000000..bc001478b2d --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_wx_tu-2.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwsubu_wx_tu(vuint16mf4_t merge,vuint16mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_tu(merge,op1,0xAA,31); +} + + +vuint16mf2_t test___riscv_vwsubu_wx_tu(vuint16mf2_t merge,vuint16mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_tu(merge,op1,0xAA,31); +} + + +vuint16m1_t test___riscv_vwsubu_wx_tu(vuint16m1_t merge,vuint16m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_tu(merge,op1,0xAA,31); +} + + +vuint16m2_t test___riscv_vwsubu_wx_tu(vuint16m2_t merge,vuint16m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_tu(merge,op1,0xAA,31); +} + + +vuint16m4_t test___riscv_vwsubu_wx_tu(vuint16m4_t merge,vuint16m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_tu(merge,op1,0xAA,31); +} + + +vuint16m8_t test___riscv_vwsubu_wx_tu(vuint16m8_t merge,vuint16m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_tu(merge,op1,0xAA,31); +} + + +vuint32mf2_t test___riscv_vwsubu_wx_tu(vuint32mf2_t merge,vuint32mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_tu(merge,op1,0xAA,31); +} + + +vuint32m1_t test___riscv_vwsubu_wx_tu(vuint32m1_t merge,vuint32m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_tu(merge,op1,0xAA,31); +} + + +vuint32m2_t test___riscv_vwsubu_wx_tu(vuint32m2_t merge,vuint32m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_tu(merge,op1,0xAA,31); +} + + +vuint32m4_t test___riscv_vwsubu_wx_tu(vuint32m4_t merge,vuint32m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_tu(merge,op1,0xAA,31); +} + + +vuint32m8_t test___riscv_vwsubu_wx_tu(vuint32m8_t merge,vuint32m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_tu(merge,op1,0xAA,31); +} + + +vuint64m1_t test___riscv_vwsubu_wx_tu(vuint64m1_t merge,vuint64m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_tu(merge,op1,0xAA,31); +} + + +vuint64m2_t test___riscv_vwsubu_wx_tu(vuint64m2_t merge,vuint64m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_tu(merge,op1,0xAA,31); +} + + +vuint64m4_t test___riscv_vwsubu_wx_tu(vuint64m4_t merge,vuint64m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_tu(merge,op1,0xAA,31); +} + + +vuint64m8_t test___riscv_vwsubu_wx_tu(vuint64m8_t merge,vuint64m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_tu(merge,op1,0xAA,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_wx_tu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_wx_tu-3.C new file mode 100644 index 00000000000..5f084a36684 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_wx_tu-3.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwsubu_wx_tu(vuint16mf4_t merge,vuint16mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_tu(merge,op1,0xAA,32); +} + + +vuint16mf2_t test___riscv_vwsubu_wx_tu(vuint16mf2_t merge,vuint16mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_tu(merge,op1,0xAA,32); +} + + +vuint16m1_t test___riscv_vwsubu_wx_tu(vuint16m1_t merge,vuint16m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_tu(merge,op1,0xAA,32); +} + + +vuint16m2_t test___riscv_vwsubu_wx_tu(vuint16m2_t merge,vuint16m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_tu(merge,op1,0xAA,32); +} + + +vuint16m4_t test___riscv_vwsubu_wx_tu(vuint16m4_t merge,vuint16m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_tu(merge,op1,0xAA,32); +} + + +vuint16m8_t test___riscv_vwsubu_wx_tu(vuint16m8_t merge,vuint16m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_tu(merge,op1,0xAA,32); +} + + +vuint32mf2_t test___riscv_vwsubu_wx_tu(vuint32mf2_t merge,vuint32mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_tu(merge,op1,0xAA,32); +} + + +vuint32m1_t test___riscv_vwsubu_wx_tu(vuint32m1_t merge,vuint32m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_tu(merge,op1,0xAA,32); +} + + +vuint32m2_t test___riscv_vwsubu_wx_tu(vuint32m2_t merge,vuint32m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_tu(merge,op1,0xAA,32); +} + + +vuint32m4_t test___riscv_vwsubu_wx_tu(vuint32m4_t merge,vuint32m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_tu(merge,op1,0xAA,32); +} + + +vuint32m8_t test___riscv_vwsubu_wx_tu(vuint32m8_t merge,vuint32m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_tu(merge,op1,0xAA,32); +} + + +vuint64m1_t test___riscv_vwsubu_wx_tu(vuint64m1_t merge,vuint64m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_tu(merge,op1,0xAA,32); +} + + +vuint64m2_t test___riscv_vwsubu_wx_tu(vuint64m2_t merge,vuint64m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_tu(merge,op1,0xAA,32); +} + + +vuint64m4_t test___riscv_vwsubu_wx_tu(vuint64m4_t merge,vuint64m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_tu(merge,op1,0xAA,32); +} + + +vuint64m8_t test___riscv_vwsubu_wx_tu(vuint64m8_t merge,vuint64m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_tu(merge,op1,0xAA,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_wx_tum-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_wx_tum-1.C new file mode 100644 index 00000000000..cab182d059a --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_wx_tum-1.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwsubu_wx_tum(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_tum(mask,merge,op1,0xAA,vl); +} + + +vuint16mf2_t test___riscv_vwsubu_wx_tum(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_tum(mask,merge,op1,0xAA,vl); +} + + +vuint16m1_t test___riscv_vwsubu_wx_tum(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_tum(mask,merge,op1,0xAA,vl); +} + + +vuint16m2_t test___riscv_vwsubu_wx_tum(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_tum(mask,merge,op1,0xAA,vl); +} + + +vuint16m4_t test___riscv_vwsubu_wx_tum(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_tum(mask,merge,op1,0xAA,vl); +} + + +vuint16m8_t test___riscv_vwsubu_wx_tum(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_tum(mask,merge,op1,0xAA,vl); +} + + +vuint32mf2_t test___riscv_vwsubu_wx_tum(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_tum(mask,merge,op1,0xAA,vl); +} + + +vuint32m1_t test___riscv_vwsubu_wx_tum(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_tum(mask,merge,op1,0xAA,vl); +} + + +vuint32m2_t test___riscv_vwsubu_wx_tum(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_tum(mask,merge,op1,0xAA,vl); +} + + +vuint32m4_t test___riscv_vwsubu_wx_tum(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_tum(mask,merge,op1,0xAA,vl); +} + + +vuint32m8_t test___riscv_vwsubu_wx_tum(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_tum(mask,merge,op1,0xAA,vl); +} + + +vuint64m1_t test___riscv_vwsubu_wx_tum(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_tum(mask,merge,op1,0xAA,vl); +} + + +vuint64m2_t test___riscv_vwsubu_wx_tum(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_tum(mask,merge,op1,0xAA,vl); +} + + +vuint64m4_t test___riscv_vwsubu_wx_tum(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_tum(mask,merge,op1,0xAA,vl); +} + + +vuint64m8_t test___riscv_vwsubu_wx_tum(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_tum(mask,merge,op1,0xAA,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_wx_tum-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_wx_tum-2.C new file mode 100644 index 00000000000..2cf9232b68e --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_wx_tum-2.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwsubu_wx_tum(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_tum(mask,merge,op1,0xAA,31); +} + + +vuint16mf2_t test___riscv_vwsubu_wx_tum(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_tum(mask,merge,op1,0xAA,31); +} + + +vuint16m1_t test___riscv_vwsubu_wx_tum(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_tum(mask,merge,op1,0xAA,31); +} + + +vuint16m2_t test___riscv_vwsubu_wx_tum(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_tum(mask,merge,op1,0xAA,31); +} + + +vuint16m4_t test___riscv_vwsubu_wx_tum(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_tum(mask,merge,op1,0xAA,31); +} + + +vuint16m8_t test___riscv_vwsubu_wx_tum(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_tum(mask,merge,op1,0xAA,31); +} + + +vuint32mf2_t test___riscv_vwsubu_wx_tum(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_tum(mask,merge,op1,0xAA,31); +} + + +vuint32m1_t test___riscv_vwsubu_wx_tum(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_tum(mask,merge,op1,0xAA,31); +} + + +vuint32m2_t test___riscv_vwsubu_wx_tum(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_tum(mask,merge,op1,0xAA,31); +} + + +vuint32m4_t test___riscv_vwsubu_wx_tum(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_tum(mask,merge,op1,0xAA,31); +} + + +vuint32m8_t test___riscv_vwsubu_wx_tum(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_tum(mask,merge,op1,0xAA,31); +} + + +vuint64m1_t test___riscv_vwsubu_wx_tum(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_tum(mask,merge,op1,0xAA,31); +} + + +vuint64m2_t test___riscv_vwsubu_wx_tum(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_tum(mask,merge,op1,0xAA,31); +} + + +vuint64m4_t test___riscv_vwsubu_wx_tum(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_tum(mask,merge,op1,0xAA,31); +} + + +vuint64m8_t test___riscv_vwsubu_wx_tum(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_tum(mask,merge,op1,0xAA,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_wx_tum-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_wx_tum-3.C new file mode 100644 index 00000000000..bbd2d841df5 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_wx_tum-3.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwsubu_wx_tum(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_tum(mask,merge,op1,0xAA,32); +} + + +vuint16mf2_t test___riscv_vwsubu_wx_tum(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_tum(mask,merge,op1,0xAA,32); +} + + +vuint16m1_t test___riscv_vwsubu_wx_tum(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_tum(mask,merge,op1,0xAA,32); +} + + +vuint16m2_t test___riscv_vwsubu_wx_tum(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_tum(mask,merge,op1,0xAA,32); +} + + +vuint16m4_t test___riscv_vwsubu_wx_tum(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_tum(mask,merge,op1,0xAA,32); +} + + +vuint16m8_t test___riscv_vwsubu_wx_tum(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_tum(mask,merge,op1,0xAA,32); +} + + +vuint32mf2_t test___riscv_vwsubu_wx_tum(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_tum(mask,merge,op1,0xAA,32); +} + + +vuint32m1_t test___riscv_vwsubu_wx_tum(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_tum(mask,merge,op1,0xAA,32); +} + + +vuint32m2_t test___riscv_vwsubu_wx_tum(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_tum(mask,merge,op1,0xAA,32); +} + + +vuint32m4_t test___riscv_vwsubu_wx_tum(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_tum(mask,merge,op1,0xAA,32); +} + + +vuint32m8_t test___riscv_vwsubu_wx_tum(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_tum(mask,merge,op1,0xAA,32); +} + + +vuint64m1_t test___riscv_vwsubu_wx_tum(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_tum(mask,merge,op1,0xAA,32); +} + + +vuint64m2_t test___riscv_vwsubu_wx_tum(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_tum(mask,merge,op1,0xAA,32); +} + + +vuint64m4_t test___riscv_vwsubu_wx_tum(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_tum(mask,merge,op1,0xAA,32); +} + + +vuint64m8_t test___riscv_vwsubu_wx_tum(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_tum(mask,merge,op1,0xAA,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_wx_tumu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_wx_tumu-1.C new file mode 100644 index 00000000000..b5f9b8b6fd1 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_wx_tumu-1.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwsubu_wx_tumu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_tumu(mask,merge,op1,0xAA,vl); +} + + +vuint16mf2_t test___riscv_vwsubu_wx_tumu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_tumu(mask,merge,op1,0xAA,vl); +} + + +vuint16m1_t test___riscv_vwsubu_wx_tumu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_tumu(mask,merge,op1,0xAA,vl); +} + + +vuint16m2_t test___riscv_vwsubu_wx_tumu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_tumu(mask,merge,op1,0xAA,vl); +} + + +vuint16m4_t test___riscv_vwsubu_wx_tumu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_tumu(mask,merge,op1,0xAA,vl); +} + + +vuint16m8_t test___riscv_vwsubu_wx_tumu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_tumu(mask,merge,op1,0xAA,vl); +} + + +vuint32mf2_t test___riscv_vwsubu_wx_tumu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_tumu(mask,merge,op1,0xAA,vl); +} + + +vuint32m1_t test___riscv_vwsubu_wx_tumu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_tumu(mask,merge,op1,0xAA,vl); +} + + +vuint32m2_t test___riscv_vwsubu_wx_tumu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_tumu(mask,merge,op1,0xAA,vl); +} + + +vuint32m4_t test___riscv_vwsubu_wx_tumu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_tumu(mask,merge,op1,0xAA,vl); +} + + +vuint32m8_t test___riscv_vwsubu_wx_tumu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_tumu(mask,merge,op1,0xAA,vl); +} + + +vuint64m1_t test___riscv_vwsubu_wx_tumu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_tumu(mask,merge,op1,0xAA,vl); +} + + +vuint64m2_t test___riscv_vwsubu_wx_tumu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_tumu(mask,merge,op1,0xAA,vl); +} + + +vuint64m4_t test___riscv_vwsubu_wx_tumu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_tumu(mask,merge,op1,0xAA,vl); +} + + +vuint64m8_t test___riscv_vwsubu_wx_tumu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_tumu(mask,merge,op1,0xAA,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_wx_tumu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_wx_tumu-2.C new file mode 100644 index 00000000000..76b963f2175 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_wx_tumu-2.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwsubu_wx_tumu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_tumu(mask,merge,op1,0xAA,31); +} + + +vuint16mf2_t test___riscv_vwsubu_wx_tumu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_tumu(mask,merge,op1,0xAA,31); +} + + +vuint16m1_t test___riscv_vwsubu_wx_tumu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_tumu(mask,merge,op1,0xAA,31); +} + + +vuint16m2_t test___riscv_vwsubu_wx_tumu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_tumu(mask,merge,op1,0xAA,31); +} + + +vuint16m4_t test___riscv_vwsubu_wx_tumu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_tumu(mask,merge,op1,0xAA,31); +} + + +vuint16m8_t test___riscv_vwsubu_wx_tumu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_tumu(mask,merge,op1,0xAA,31); +} + + +vuint32mf2_t test___riscv_vwsubu_wx_tumu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_tumu(mask,merge,op1,0xAA,31); +} + + +vuint32m1_t test___riscv_vwsubu_wx_tumu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_tumu(mask,merge,op1,0xAA,31); +} + + +vuint32m2_t test___riscv_vwsubu_wx_tumu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_tumu(mask,merge,op1,0xAA,31); +} + + +vuint32m4_t test___riscv_vwsubu_wx_tumu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_tumu(mask,merge,op1,0xAA,31); +} + + +vuint32m8_t test___riscv_vwsubu_wx_tumu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_tumu(mask,merge,op1,0xAA,31); +} + + +vuint64m1_t test___riscv_vwsubu_wx_tumu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_tumu(mask,merge,op1,0xAA,31); +} + + +vuint64m2_t test___riscv_vwsubu_wx_tumu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_tumu(mask,merge,op1,0xAA,31); +} + + +vuint64m4_t test___riscv_vwsubu_wx_tumu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_tumu(mask,merge,op1,0xAA,31); +} + + +vuint64m8_t test___riscv_vwsubu_wx_tumu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_tumu(mask,merge,op1,0xAA,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_wx_tumu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_wx_tumu-3.C new file mode 100644 index 00000000000..d275239736d --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_wx_tumu-3.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwsubu_wx_tumu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_tumu(mask,merge,op1,0xAA,32); +} + + +vuint16mf2_t test___riscv_vwsubu_wx_tumu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_tumu(mask,merge,op1,0xAA,32); +} + + +vuint16m1_t test___riscv_vwsubu_wx_tumu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_tumu(mask,merge,op1,0xAA,32); +} + + +vuint16m2_t test___riscv_vwsubu_wx_tumu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_tumu(mask,merge,op1,0xAA,32); +} + + +vuint16m4_t test___riscv_vwsubu_wx_tumu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_tumu(mask,merge,op1,0xAA,32); +} + + +vuint16m8_t test___riscv_vwsubu_wx_tumu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_tumu(mask,merge,op1,0xAA,32); +} + + +vuint32mf2_t test___riscv_vwsubu_wx_tumu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_tumu(mask,merge,op1,0xAA,32); +} + + +vuint32m1_t test___riscv_vwsubu_wx_tumu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_tumu(mask,merge,op1,0xAA,32); +} + + +vuint32m2_t test___riscv_vwsubu_wx_tumu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_tumu(mask,merge,op1,0xAA,32); +} + + +vuint32m4_t test___riscv_vwsubu_wx_tumu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_tumu(mask,merge,op1,0xAA,32); +} + + +vuint32m8_t test___riscv_vwsubu_wx_tumu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_tumu(mask,merge,op1,0xAA,32); +} + + +vuint64m1_t test___riscv_vwsubu_wx_tumu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_tumu(mask,merge,op1,0xAA,32); +} + + +vuint64m2_t test___riscv_vwsubu_wx_tumu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_tumu(mask,merge,op1,0xAA,32); +} + + +vuint64m4_t test___riscv_vwsubu_wx_tumu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_tumu(mask,merge,op1,0xAA,32); +} + + +vuint64m8_t test___riscv_vwsubu_wx_tumu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_tumu(mask,merge,op1,0xAA,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */