From patchwork Tue Feb 7 06:32:24 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?6ZKf5bGF5ZOy?= X-Patchwork-Id: 64414 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 92D2D385841C for ; Tue, 7 Feb 2023 06:33:00 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from smtpbg151.qq.com (smtpbg151.qq.com [18.169.211.239]) by sourceware.org (Postfix) with ESMTPS id D63A43858D1E for ; Tue, 7 Feb 2023 06:32:31 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org D63A43858D1E Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivai.ai Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivai.ai X-QQ-mid: bizesmtp74t1675751546txiax5o6 Received: from server1.localdomain ( [58.60.1.22]) by bizesmtp.qq.com (ESMTP) with id ; Tue, 07 Feb 2023 14:32:25 +0800 (CST) X-QQ-SSF: 01400000000000E0L000000A0000000 X-QQ-FEAT: ISZTShXIZRMS/Scza95p9vGQs+V1ahSkPSeFfFa7Q+mw+l2ArfEYkhhY1AhzC pPs2wk1a7nF99pjIKlKz4jAFq+3VmkRscoOh/4CaxXoa13h9CWwoqhBOfJTrkvqU66npPqf KNdtlJhQkjiHTrVGicyhCOwszkccUDFHA1s9LFiV/2Fhyw1Z03Jnb7L8L+li60DyIuzhJpo L1/3kLW82NV3CIHXkuXPZ8r8wYIhIxJX7yavHrDW7P0QxH4wq/fL8fuOhnm5Xsm2PEhj/mF rzWcN/96mVDGIPCN/V2kXk9jrN08zmmt7ksgUoZhVAaPXL9dy7VOkZLGWpQhzg+cUL4C+Sa U0sHgYDhyH8gaHn5/zCcvJ/N4JfFEO5oyNNlLjruO1kVt5mrJ1R6P7/l0sCkg== X-QQ-GoodBg: 2 From: juzhe.zhong@rivai.ai To: gcc-patches@gcc.gnu.org Cc: kito.cheng@gmail.com, Ju-Zhe Zhong Subject: [PATCH] RISC-V: Add vwmul C api tests Date: Tue, 7 Feb 2023 14:32:24 +0800 Message-Id: <20230207063224.39064-1-juzhe.zhong@rivai.ai> X-Mailer: git-send-email 2.36.1 MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:rivai.ai:qybglogicsvr:qybglogicsvr7 X-Spam-Status: No, score=-10.9 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, KAM_SHORT, RCVD_IN_BARRACUDACENTRAL, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_PASS, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" From: Ju-Zhe Zhong gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/vwmul_vv-1.c: New test. * gcc.target/riscv/rvv/base/vwmul_vv-2.c: New test. * gcc.target/riscv/rvv/base/vwmul_vv-3.c: New test. * gcc.target/riscv/rvv/base/vwmul_vv_m-1.c: New test. * gcc.target/riscv/rvv/base/vwmul_vv_m-2.c: New test. * gcc.target/riscv/rvv/base/vwmul_vv_m-3.c: New test. * gcc.target/riscv/rvv/base/vwmul_vv_mu-1.c: New test. * gcc.target/riscv/rvv/base/vwmul_vv_mu-2.c: New test. * gcc.target/riscv/rvv/base/vwmul_vv_mu-3.c: New test. * gcc.target/riscv/rvv/base/vwmul_vv_tu-1.c: New test. * gcc.target/riscv/rvv/base/vwmul_vv_tu-2.c: New test. * gcc.target/riscv/rvv/base/vwmul_vv_tu-3.c: New test. * gcc.target/riscv/rvv/base/vwmul_vv_tum-1.c: New test. * gcc.target/riscv/rvv/base/vwmul_vv_tum-2.c: New test. * gcc.target/riscv/rvv/base/vwmul_vv_tum-3.c: New test. * gcc.target/riscv/rvv/base/vwmul_vv_tumu-1.c: New test. * gcc.target/riscv/rvv/base/vwmul_vv_tumu-2.c: New test. * gcc.target/riscv/rvv/base/vwmul_vv_tumu-3.c: New test. * gcc.target/riscv/rvv/base/vwmul_vx-1.c: New test. * gcc.target/riscv/rvv/base/vwmul_vx-2.c: New test. * gcc.target/riscv/rvv/base/vwmul_vx-3.c: New test. * gcc.target/riscv/rvv/base/vwmul_vx_m-1.c: New test. * gcc.target/riscv/rvv/base/vwmul_vx_m-2.c: New test. * gcc.target/riscv/rvv/base/vwmul_vx_m-3.c: New test. * gcc.target/riscv/rvv/base/vwmul_vx_mu-1.c: New test. * gcc.target/riscv/rvv/base/vwmul_vx_mu-2.c: New test. * gcc.target/riscv/rvv/base/vwmul_vx_mu-3.c: New test. * gcc.target/riscv/rvv/base/vwmul_vx_tu-1.c: New test. * gcc.target/riscv/rvv/base/vwmul_vx_tu-2.c: New test. * gcc.target/riscv/rvv/base/vwmul_vx_tu-3.c: New test. * gcc.target/riscv/rvv/base/vwmul_vx_tum-1.c: New test. * gcc.target/riscv/rvv/base/vwmul_vx_tum-2.c: New test. * gcc.target/riscv/rvv/base/vwmul_vx_tum-3.c: New test. * gcc.target/riscv/rvv/base/vwmul_vx_tumu-1.c: New test. * gcc.target/riscv/rvv/base/vwmul_vx_tumu-2.c: New test. * gcc.target/riscv/rvv/base/vwmul_vx_tumu-3.c: New test. --- .../gcc.target/riscv/rvv/base/vwmul_vv-1.c | 111 ++++++++++++++++++ .../gcc.target/riscv/rvv/base/vwmul_vv-2.c | 111 ++++++++++++++++++ .../gcc.target/riscv/rvv/base/vwmul_vv-3.c | 111 ++++++++++++++++++ .../gcc.target/riscv/rvv/base/vwmul_vv_m-1.c | 111 ++++++++++++++++++ .../gcc.target/riscv/rvv/base/vwmul_vv_m-2.c | 111 ++++++++++++++++++ .../gcc.target/riscv/rvv/base/vwmul_vv_m-3.c | 111 ++++++++++++++++++ .../gcc.target/riscv/rvv/base/vwmul_vv_mu-1.c | 111 ++++++++++++++++++ .../gcc.target/riscv/rvv/base/vwmul_vv_mu-2.c | 111 ++++++++++++++++++ .../gcc.target/riscv/rvv/base/vwmul_vv_mu-3.c | 111 ++++++++++++++++++ .../gcc.target/riscv/rvv/base/vwmul_vv_tu-1.c | 111 ++++++++++++++++++ .../gcc.target/riscv/rvv/base/vwmul_vv_tu-2.c | 111 ++++++++++++++++++ .../gcc.target/riscv/rvv/base/vwmul_vv_tu-3.c | 111 ++++++++++++++++++ .../riscv/rvv/base/vwmul_vv_tum-1.c | 111 ++++++++++++++++++ .../riscv/rvv/base/vwmul_vv_tum-2.c | 111 ++++++++++++++++++ .../riscv/rvv/base/vwmul_vv_tum-3.c | 111 ++++++++++++++++++ .../riscv/rvv/base/vwmul_vv_tumu-1.c | 111 ++++++++++++++++++ .../riscv/rvv/base/vwmul_vv_tumu-2.c | 111 ++++++++++++++++++ .../riscv/rvv/base/vwmul_vv_tumu-3.c | 111 ++++++++++++++++++ .../gcc.target/riscv/rvv/base/vwmul_vx-1.c | 111 ++++++++++++++++++ .../gcc.target/riscv/rvv/base/vwmul_vx-2.c | 111 ++++++++++++++++++ .../gcc.target/riscv/rvv/base/vwmul_vx-3.c | 111 ++++++++++++++++++ .../gcc.target/riscv/rvv/base/vwmul_vx_m-1.c | 111 ++++++++++++++++++ .../gcc.target/riscv/rvv/base/vwmul_vx_m-2.c | 111 ++++++++++++++++++ .../gcc.target/riscv/rvv/base/vwmul_vx_m-3.c | 111 ++++++++++++++++++ .../gcc.target/riscv/rvv/base/vwmul_vx_mu-1.c | 111 ++++++++++++++++++ .../gcc.target/riscv/rvv/base/vwmul_vx_mu-2.c | 111 ++++++++++++++++++ .../gcc.target/riscv/rvv/base/vwmul_vx_mu-3.c | 111 ++++++++++++++++++ .../gcc.target/riscv/rvv/base/vwmul_vx_tu-1.c | 111 ++++++++++++++++++ .../gcc.target/riscv/rvv/base/vwmul_vx_tu-2.c | 111 ++++++++++++++++++ .../gcc.target/riscv/rvv/base/vwmul_vx_tu-3.c | 111 ++++++++++++++++++ .../riscv/rvv/base/vwmul_vx_tum-1.c | 111 ++++++++++++++++++ .../riscv/rvv/base/vwmul_vx_tum-2.c | 111 ++++++++++++++++++ .../riscv/rvv/base/vwmul_vx_tum-3.c | 111 ++++++++++++++++++ .../riscv/rvv/base/vwmul_vx_tumu-1.c | 111 ++++++++++++++++++ .../riscv/rvv/base/vwmul_vx_tumu-2.c | 111 ++++++++++++++++++ .../riscv/rvv/base/vwmul_vx_tumu-3.c | 111 ++++++++++++++++++ 36 files changed, 3996 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmul_vv-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmul_vv-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmul_vv-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmul_vv_m-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmul_vv_m-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmul_vv_m-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmul_vv_mu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmul_vv_mu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmul_vv_mu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmul_vv_tu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmul_vv_tu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmul_vv_tu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmul_vv_tum-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmul_vv_tum-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmul_vv_tum-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmul_vv_tumu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmul_vv_tumu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmul_vv_tumu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmul_vx-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmul_vx-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmul_vx-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmul_vx_m-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmul_vx_m-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmul_vx_m-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmul_vx_mu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmul_vx_mu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmul_vx_mu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmul_vx_tu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmul_vx_tu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmul_vx_tu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmul_vx_tum-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmul_vx_tum-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmul_vx_tum-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmul_vx_tumu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmul_vx_tumu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmul_vx_tumu-3.c diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmul_vv-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmul_vv-1.c new file mode 100644 index 00000000000..d70370f25e2 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmul_vv-1.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwmul_vv_i16mf4(vint8mf8_t op1,vint8mf8_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i16mf4(op1,op2,vl); +} + + +vint16mf2_t test___riscv_vwmul_vv_i16mf2(vint8mf4_t op1,vint8mf4_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i16mf2(op1,op2,vl); +} + + +vint16m1_t test___riscv_vwmul_vv_i16m1(vint8mf2_t op1,vint8mf2_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i16m1(op1,op2,vl); +} + + +vint16m2_t test___riscv_vwmul_vv_i16m2(vint8m1_t op1,vint8m1_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i16m2(op1,op2,vl); +} + + +vint16m4_t test___riscv_vwmul_vv_i16m4(vint8m2_t op1,vint8m2_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i16m4(op1,op2,vl); +} + + +vint16m8_t test___riscv_vwmul_vv_i16m8(vint8m4_t op1,vint8m4_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i16m8(op1,op2,vl); +} + + +vint32mf2_t test___riscv_vwmul_vv_i32mf2(vint16mf4_t op1,vint16mf4_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i32mf2(op1,op2,vl); +} + + +vint32m1_t test___riscv_vwmul_vv_i32m1(vint16mf2_t op1,vint16mf2_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i32m1(op1,op2,vl); +} + + +vint32m2_t test___riscv_vwmul_vv_i32m2(vint16m1_t op1,vint16m1_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i32m2(op1,op2,vl); +} + + +vint32m4_t test___riscv_vwmul_vv_i32m4(vint16m2_t op1,vint16m2_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i32m4(op1,op2,vl); +} + + +vint32m8_t test___riscv_vwmul_vv_i32m8(vint16m4_t op1,vint16m4_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i32m8(op1,op2,vl); +} + + +vint64m1_t test___riscv_vwmul_vv_i64m1(vint32mf2_t op1,vint32mf2_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i64m1(op1,op2,vl); +} + + +vint64m2_t test___riscv_vwmul_vv_i64m2(vint32m1_t op1,vint32m1_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i64m2(op1,op2,vl); +} + + +vint64m4_t test___riscv_vwmul_vv_i64m4(vint32m2_t op1,vint32m2_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i64m4(op1,op2,vl); +} + + +vint64m8_t test___riscv_vwmul_vv_i64m8(vint32m4_t op1,vint32m4_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i64m8(op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmul_vv-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmul_vv-2.c new file mode 100644 index 00000000000..aabdc30143f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmul_vv-2.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwmul_vv_i16mf4(vint8mf8_t op1,vint8mf8_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i16mf4(op1,op2,31); +} + + +vint16mf2_t test___riscv_vwmul_vv_i16mf2(vint8mf4_t op1,vint8mf4_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i16mf2(op1,op2,31); +} + + +vint16m1_t test___riscv_vwmul_vv_i16m1(vint8mf2_t op1,vint8mf2_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i16m1(op1,op2,31); +} + + +vint16m2_t test___riscv_vwmul_vv_i16m2(vint8m1_t op1,vint8m1_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i16m2(op1,op2,31); +} + + +vint16m4_t test___riscv_vwmul_vv_i16m4(vint8m2_t op1,vint8m2_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i16m4(op1,op2,31); +} + + +vint16m8_t test___riscv_vwmul_vv_i16m8(vint8m4_t op1,vint8m4_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i16m8(op1,op2,31); +} + + +vint32mf2_t test___riscv_vwmul_vv_i32mf2(vint16mf4_t op1,vint16mf4_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i32mf2(op1,op2,31); +} + + +vint32m1_t test___riscv_vwmul_vv_i32m1(vint16mf2_t op1,vint16mf2_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i32m1(op1,op2,31); +} + + +vint32m2_t test___riscv_vwmul_vv_i32m2(vint16m1_t op1,vint16m1_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i32m2(op1,op2,31); +} + + +vint32m4_t test___riscv_vwmul_vv_i32m4(vint16m2_t op1,vint16m2_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i32m4(op1,op2,31); +} + + +vint32m8_t test___riscv_vwmul_vv_i32m8(vint16m4_t op1,vint16m4_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i32m8(op1,op2,31); +} + + +vint64m1_t test___riscv_vwmul_vv_i64m1(vint32mf2_t op1,vint32mf2_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i64m1(op1,op2,31); +} + + +vint64m2_t test___riscv_vwmul_vv_i64m2(vint32m1_t op1,vint32m1_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i64m2(op1,op2,31); +} + + +vint64m4_t test___riscv_vwmul_vv_i64m4(vint32m2_t op1,vint32m2_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i64m4(op1,op2,31); +} + + +vint64m8_t test___riscv_vwmul_vv_i64m8(vint32m4_t op1,vint32m4_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i64m8(op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmul_vv-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmul_vv-3.c new file mode 100644 index 00000000000..c7dccd7440f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmul_vv-3.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwmul_vv_i16mf4(vint8mf8_t op1,vint8mf8_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i16mf4(op1,op2,32); +} + + +vint16mf2_t test___riscv_vwmul_vv_i16mf2(vint8mf4_t op1,vint8mf4_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i16mf2(op1,op2,32); +} + + +vint16m1_t test___riscv_vwmul_vv_i16m1(vint8mf2_t op1,vint8mf2_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i16m1(op1,op2,32); +} + + +vint16m2_t test___riscv_vwmul_vv_i16m2(vint8m1_t op1,vint8m1_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i16m2(op1,op2,32); +} + + +vint16m4_t test___riscv_vwmul_vv_i16m4(vint8m2_t op1,vint8m2_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i16m4(op1,op2,32); +} + + +vint16m8_t test___riscv_vwmul_vv_i16m8(vint8m4_t op1,vint8m4_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i16m8(op1,op2,32); +} + + +vint32mf2_t test___riscv_vwmul_vv_i32mf2(vint16mf4_t op1,vint16mf4_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i32mf2(op1,op2,32); +} + + +vint32m1_t test___riscv_vwmul_vv_i32m1(vint16mf2_t op1,vint16mf2_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i32m1(op1,op2,32); +} + + +vint32m2_t test___riscv_vwmul_vv_i32m2(vint16m1_t op1,vint16m1_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i32m2(op1,op2,32); +} + + +vint32m4_t test___riscv_vwmul_vv_i32m4(vint16m2_t op1,vint16m2_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i32m4(op1,op2,32); +} + + +vint32m8_t test___riscv_vwmul_vv_i32m8(vint16m4_t op1,vint16m4_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i32m8(op1,op2,32); +} + + +vint64m1_t test___riscv_vwmul_vv_i64m1(vint32mf2_t op1,vint32mf2_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i64m1(op1,op2,32); +} + + +vint64m2_t test___riscv_vwmul_vv_i64m2(vint32m1_t op1,vint32m1_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i64m2(op1,op2,32); +} + + +vint64m4_t test___riscv_vwmul_vv_i64m4(vint32m2_t op1,vint32m2_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i64m4(op1,op2,32); +} + + +vint64m8_t test___riscv_vwmul_vv_i64m8(vint32m4_t op1,vint32m4_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i64m8(op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmul_vv_m-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmul_vv_m-1.c new file mode 100644 index 00000000000..ca990d4c473 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmul_vv_m-1.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwmul_vv_i16mf4_m(vbool64_t mask,vint8mf8_t op1,vint8mf8_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i16mf4_m(mask,op1,op2,vl); +} + + +vint16mf2_t test___riscv_vwmul_vv_i16mf2_m(vbool32_t mask,vint8mf4_t op1,vint8mf4_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i16mf2_m(mask,op1,op2,vl); +} + + +vint16m1_t test___riscv_vwmul_vv_i16m1_m(vbool16_t mask,vint8mf2_t op1,vint8mf2_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i16m1_m(mask,op1,op2,vl); +} + + +vint16m2_t test___riscv_vwmul_vv_i16m2_m(vbool8_t mask,vint8m1_t op1,vint8m1_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i16m2_m(mask,op1,op2,vl); +} + + +vint16m4_t test___riscv_vwmul_vv_i16m4_m(vbool4_t mask,vint8m2_t op1,vint8m2_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i16m4_m(mask,op1,op2,vl); +} + + +vint16m8_t test___riscv_vwmul_vv_i16m8_m(vbool2_t mask,vint8m4_t op1,vint8m4_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i16m8_m(mask,op1,op2,vl); +} + + +vint32mf2_t test___riscv_vwmul_vv_i32mf2_m(vbool64_t mask,vint16mf4_t op1,vint16mf4_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i32mf2_m(mask,op1,op2,vl); +} + + +vint32m1_t test___riscv_vwmul_vv_i32m1_m(vbool32_t mask,vint16mf2_t op1,vint16mf2_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i32m1_m(mask,op1,op2,vl); +} + + +vint32m2_t test___riscv_vwmul_vv_i32m2_m(vbool16_t mask,vint16m1_t op1,vint16m1_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i32m2_m(mask,op1,op2,vl); +} + + +vint32m4_t test___riscv_vwmul_vv_i32m4_m(vbool8_t mask,vint16m2_t op1,vint16m2_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i32m4_m(mask,op1,op2,vl); +} + + +vint32m8_t test___riscv_vwmul_vv_i32m8_m(vbool4_t mask,vint16m4_t op1,vint16m4_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i32m8_m(mask,op1,op2,vl); +} + + +vint64m1_t test___riscv_vwmul_vv_i64m1_m(vbool64_t mask,vint32mf2_t op1,vint32mf2_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i64m1_m(mask,op1,op2,vl); +} + + +vint64m2_t test___riscv_vwmul_vv_i64m2_m(vbool32_t mask,vint32m1_t op1,vint32m1_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i64m2_m(mask,op1,op2,vl); +} + + +vint64m4_t test___riscv_vwmul_vv_i64m4_m(vbool16_t mask,vint32m2_t op1,vint32m2_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i64m4_m(mask,op1,op2,vl); +} + + +vint64m8_t test___riscv_vwmul_vv_i64m8_m(vbool8_t mask,vint32m4_t op1,vint32m4_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i64m8_m(mask,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmul_vv_m-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmul_vv_m-2.c new file mode 100644 index 00000000000..8914cdf7d9e --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmul_vv_m-2.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwmul_vv_i16mf4_m(vbool64_t mask,vint8mf8_t op1,vint8mf8_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i16mf4_m(mask,op1,op2,31); +} + + +vint16mf2_t test___riscv_vwmul_vv_i16mf2_m(vbool32_t mask,vint8mf4_t op1,vint8mf4_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i16mf2_m(mask,op1,op2,31); +} + + +vint16m1_t test___riscv_vwmul_vv_i16m1_m(vbool16_t mask,vint8mf2_t op1,vint8mf2_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i16m1_m(mask,op1,op2,31); +} + + +vint16m2_t test___riscv_vwmul_vv_i16m2_m(vbool8_t mask,vint8m1_t op1,vint8m1_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i16m2_m(mask,op1,op2,31); +} + + +vint16m4_t test___riscv_vwmul_vv_i16m4_m(vbool4_t mask,vint8m2_t op1,vint8m2_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i16m4_m(mask,op1,op2,31); +} + + +vint16m8_t test___riscv_vwmul_vv_i16m8_m(vbool2_t mask,vint8m4_t op1,vint8m4_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i16m8_m(mask,op1,op2,31); +} + + +vint32mf2_t test___riscv_vwmul_vv_i32mf2_m(vbool64_t mask,vint16mf4_t op1,vint16mf4_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i32mf2_m(mask,op1,op2,31); +} + + +vint32m1_t test___riscv_vwmul_vv_i32m1_m(vbool32_t mask,vint16mf2_t op1,vint16mf2_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i32m1_m(mask,op1,op2,31); +} + + +vint32m2_t test___riscv_vwmul_vv_i32m2_m(vbool16_t mask,vint16m1_t op1,vint16m1_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i32m2_m(mask,op1,op2,31); +} + + +vint32m4_t test___riscv_vwmul_vv_i32m4_m(vbool8_t mask,vint16m2_t op1,vint16m2_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i32m4_m(mask,op1,op2,31); +} + + +vint32m8_t test___riscv_vwmul_vv_i32m8_m(vbool4_t mask,vint16m4_t op1,vint16m4_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i32m8_m(mask,op1,op2,31); +} + + +vint64m1_t test___riscv_vwmul_vv_i64m1_m(vbool64_t mask,vint32mf2_t op1,vint32mf2_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i64m1_m(mask,op1,op2,31); +} + + +vint64m2_t test___riscv_vwmul_vv_i64m2_m(vbool32_t mask,vint32m1_t op1,vint32m1_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i64m2_m(mask,op1,op2,31); +} + + +vint64m4_t test___riscv_vwmul_vv_i64m4_m(vbool16_t mask,vint32m2_t op1,vint32m2_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i64m4_m(mask,op1,op2,31); +} + + +vint64m8_t test___riscv_vwmul_vv_i64m8_m(vbool8_t mask,vint32m4_t op1,vint32m4_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i64m8_m(mask,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmul_vv_m-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmul_vv_m-3.c new file mode 100644 index 00000000000..65bc492e859 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmul_vv_m-3.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwmul_vv_i16mf4_m(vbool64_t mask,vint8mf8_t op1,vint8mf8_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i16mf4_m(mask,op1,op2,32); +} + + +vint16mf2_t test___riscv_vwmul_vv_i16mf2_m(vbool32_t mask,vint8mf4_t op1,vint8mf4_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i16mf2_m(mask,op1,op2,32); +} + + +vint16m1_t test___riscv_vwmul_vv_i16m1_m(vbool16_t mask,vint8mf2_t op1,vint8mf2_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i16m1_m(mask,op1,op2,32); +} + + +vint16m2_t test___riscv_vwmul_vv_i16m2_m(vbool8_t mask,vint8m1_t op1,vint8m1_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i16m2_m(mask,op1,op2,32); +} + + +vint16m4_t test___riscv_vwmul_vv_i16m4_m(vbool4_t mask,vint8m2_t op1,vint8m2_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i16m4_m(mask,op1,op2,32); +} + + +vint16m8_t test___riscv_vwmul_vv_i16m8_m(vbool2_t mask,vint8m4_t op1,vint8m4_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i16m8_m(mask,op1,op2,32); +} + + +vint32mf2_t test___riscv_vwmul_vv_i32mf2_m(vbool64_t mask,vint16mf4_t op1,vint16mf4_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i32mf2_m(mask,op1,op2,32); +} + + +vint32m1_t test___riscv_vwmul_vv_i32m1_m(vbool32_t mask,vint16mf2_t op1,vint16mf2_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i32m1_m(mask,op1,op2,32); +} + + +vint32m2_t test___riscv_vwmul_vv_i32m2_m(vbool16_t mask,vint16m1_t op1,vint16m1_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i32m2_m(mask,op1,op2,32); +} + + +vint32m4_t test___riscv_vwmul_vv_i32m4_m(vbool8_t mask,vint16m2_t op1,vint16m2_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i32m4_m(mask,op1,op2,32); +} + + +vint32m8_t test___riscv_vwmul_vv_i32m8_m(vbool4_t mask,vint16m4_t op1,vint16m4_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i32m8_m(mask,op1,op2,32); +} + + +vint64m1_t test___riscv_vwmul_vv_i64m1_m(vbool64_t mask,vint32mf2_t op1,vint32mf2_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i64m1_m(mask,op1,op2,32); +} + + +vint64m2_t test___riscv_vwmul_vv_i64m2_m(vbool32_t mask,vint32m1_t op1,vint32m1_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i64m2_m(mask,op1,op2,32); +} + + +vint64m4_t test___riscv_vwmul_vv_i64m4_m(vbool16_t mask,vint32m2_t op1,vint32m2_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i64m4_m(mask,op1,op2,32); +} + + +vint64m8_t test___riscv_vwmul_vv_i64m8_m(vbool8_t mask,vint32m4_t op1,vint32m4_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i64m8_m(mask,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmul_vv_mu-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmul_vv_mu-1.c new file mode 100644 index 00000000000..fdab68fe8e4 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmul_vv_mu-1.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwmul_vv_i16mf4_mu(vbool64_t mask,vint16mf4_t merge,vint8mf8_t op1,vint8mf8_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i16mf4_mu(mask,merge,op1,op2,vl); +} + + +vint16mf2_t test___riscv_vwmul_vv_i16mf2_mu(vbool32_t mask,vint16mf2_t merge,vint8mf4_t op1,vint8mf4_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i16mf2_mu(mask,merge,op1,op2,vl); +} + + +vint16m1_t test___riscv_vwmul_vv_i16m1_mu(vbool16_t mask,vint16m1_t merge,vint8mf2_t op1,vint8mf2_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i16m1_mu(mask,merge,op1,op2,vl); +} + + +vint16m2_t test___riscv_vwmul_vv_i16m2_mu(vbool8_t mask,vint16m2_t merge,vint8m1_t op1,vint8m1_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i16m2_mu(mask,merge,op1,op2,vl); +} + + +vint16m4_t test___riscv_vwmul_vv_i16m4_mu(vbool4_t mask,vint16m4_t merge,vint8m2_t op1,vint8m2_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i16m4_mu(mask,merge,op1,op2,vl); +} + + +vint16m8_t test___riscv_vwmul_vv_i16m8_mu(vbool2_t mask,vint16m8_t merge,vint8m4_t op1,vint8m4_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i16m8_mu(mask,merge,op1,op2,vl); +} + + +vint32mf2_t test___riscv_vwmul_vv_i32mf2_mu(vbool64_t mask,vint32mf2_t merge,vint16mf4_t op1,vint16mf4_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i32mf2_mu(mask,merge,op1,op2,vl); +} + + +vint32m1_t test___riscv_vwmul_vv_i32m1_mu(vbool32_t mask,vint32m1_t merge,vint16mf2_t op1,vint16mf2_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i32m1_mu(mask,merge,op1,op2,vl); +} + + +vint32m2_t test___riscv_vwmul_vv_i32m2_mu(vbool16_t mask,vint32m2_t merge,vint16m1_t op1,vint16m1_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i32m2_mu(mask,merge,op1,op2,vl); +} + + +vint32m4_t test___riscv_vwmul_vv_i32m4_mu(vbool8_t mask,vint32m4_t merge,vint16m2_t op1,vint16m2_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i32m4_mu(mask,merge,op1,op2,vl); +} + + +vint32m8_t test___riscv_vwmul_vv_i32m8_mu(vbool4_t mask,vint32m8_t merge,vint16m4_t op1,vint16m4_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i32m8_mu(mask,merge,op1,op2,vl); +} + + +vint64m1_t test___riscv_vwmul_vv_i64m1_mu(vbool64_t mask,vint64m1_t merge,vint32mf2_t op1,vint32mf2_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i64m1_mu(mask,merge,op1,op2,vl); +} + + +vint64m2_t test___riscv_vwmul_vv_i64m2_mu(vbool32_t mask,vint64m2_t merge,vint32m1_t op1,vint32m1_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i64m2_mu(mask,merge,op1,op2,vl); +} + + +vint64m4_t test___riscv_vwmul_vv_i64m4_mu(vbool16_t mask,vint64m4_t merge,vint32m2_t op1,vint32m2_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i64m4_mu(mask,merge,op1,op2,vl); +} + + +vint64m8_t test___riscv_vwmul_vv_i64m8_mu(vbool8_t mask,vint64m8_t merge,vint32m4_t op1,vint32m4_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i64m8_mu(mask,merge,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmul_vv_mu-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmul_vv_mu-2.c new file mode 100644 index 00000000000..3f6851aafcf --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmul_vv_mu-2.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwmul_vv_i16mf4_mu(vbool64_t mask,vint16mf4_t merge,vint8mf8_t op1,vint8mf8_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i16mf4_mu(mask,merge,op1,op2,31); +} + + +vint16mf2_t test___riscv_vwmul_vv_i16mf2_mu(vbool32_t mask,vint16mf2_t merge,vint8mf4_t op1,vint8mf4_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i16mf2_mu(mask,merge,op1,op2,31); +} + + +vint16m1_t test___riscv_vwmul_vv_i16m1_mu(vbool16_t mask,vint16m1_t merge,vint8mf2_t op1,vint8mf2_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i16m1_mu(mask,merge,op1,op2,31); +} + + +vint16m2_t test___riscv_vwmul_vv_i16m2_mu(vbool8_t mask,vint16m2_t merge,vint8m1_t op1,vint8m1_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i16m2_mu(mask,merge,op1,op2,31); +} + + +vint16m4_t test___riscv_vwmul_vv_i16m4_mu(vbool4_t mask,vint16m4_t merge,vint8m2_t op1,vint8m2_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i16m4_mu(mask,merge,op1,op2,31); +} + + +vint16m8_t test___riscv_vwmul_vv_i16m8_mu(vbool2_t mask,vint16m8_t merge,vint8m4_t op1,vint8m4_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i16m8_mu(mask,merge,op1,op2,31); +} + + +vint32mf2_t test___riscv_vwmul_vv_i32mf2_mu(vbool64_t mask,vint32mf2_t merge,vint16mf4_t op1,vint16mf4_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i32mf2_mu(mask,merge,op1,op2,31); +} + + +vint32m1_t test___riscv_vwmul_vv_i32m1_mu(vbool32_t mask,vint32m1_t merge,vint16mf2_t op1,vint16mf2_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i32m1_mu(mask,merge,op1,op2,31); +} + + +vint32m2_t test___riscv_vwmul_vv_i32m2_mu(vbool16_t mask,vint32m2_t merge,vint16m1_t op1,vint16m1_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i32m2_mu(mask,merge,op1,op2,31); +} + + +vint32m4_t test___riscv_vwmul_vv_i32m4_mu(vbool8_t mask,vint32m4_t merge,vint16m2_t op1,vint16m2_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i32m4_mu(mask,merge,op1,op2,31); +} + + +vint32m8_t test___riscv_vwmul_vv_i32m8_mu(vbool4_t mask,vint32m8_t merge,vint16m4_t op1,vint16m4_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i32m8_mu(mask,merge,op1,op2,31); +} + + +vint64m1_t test___riscv_vwmul_vv_i64m1_mu(vbool64_t mask,vint64m1_t merge,vint32mf2_t op1,vint32mf2_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i64m1_mu(mask,merge,op1,op2,31); +} + + +vint64m2_t test___riscv_vwmul_vv_i64m2_mu(vbool32_t mask,vint64m2_t merge,vint32m1_t op1,vint32m1_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i64m2_mu(mask,merge,op1,op2,31); +} + + +vint64m4_t test___riscv_vwmul_vv_i64m4_mu(vbool16_t mask,vint64m4_t merge,vint32m2_t op1,vint32m2_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i64m4_mu(mask,merge,op1,op2,31); +} + + +vint64m8_t test___riscv_vwmul_vv_i64m8_mu(vbool8_t mask,vint64m8_t merge,vint32m4_t op1,vint32m4_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i64m8_mu(mask,merge,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmul_vv_mu-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmul_vv_mu-3.c new file mode 100644 index 00000000000..28bc4f38c2a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmul_vv_mu-3.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwmul_vv_i16mf4_mu(vbool64_t mask,vint16mf4_t merge,vint8mf8_t op1,vint8mf8_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i16mf4_mu(mask,merge,op1,op2,32); +} + + +vint16mf2_t test___riscv_vwmul_vv_i16mf2_mu(vbool32_t mask,vint16mf2_t merge,vint8mf4_t op1,vint8mf4_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i16mf2_mu(mask,merge,op1,op2,32); +} + + +vint16m1_t test___riscv_vwmul_vv_i16m1_mu(vbool16_t mask,vint16m1_t merge,vint8mf2_t op1,vint8mf2_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i16m1_mu(mask,merge,op1,op2,32); +} + + +vint16m2_t test___riscv_vwmul_vv_i16m2_mu(vbool8_t mask,vint16m2_t merge,vint8m1_t op1,vint8m1_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i16m2_mu(mask,merge,op1,op2,32); +} + + +vint16m4_t test___riscv_vwmul_vv_i16m4_mu(vbool4_t mask,vint16m4_t merge,vint8m2_t op1,vint8m2_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i16m4_mu(mask,merge,op1,op2,32); +} + + +vint16m8_t test___riscv_vwmul_vv_i16m8_mu(vbool2_t mask,vint16m8_t merge,vint8m4_t op1,vint8m4_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i16m8_mu(mask,merge,op1,op2,32); +} + + +vint32mf2_t test___riscv_vwmul_vv_i32mf2_mu(vbool64_t mask,vint32mf2_t merge,vint16mf4_t op1,vint16mf4_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i32mf2_mu(mask,merge,op1,op2,32); +} + + +vint32m1_t test___riscv_vwmul_vv_i32m1_mu(vbool32_t mask,vint32m1_t merge,vint16mf2_t op1,vint16mf2_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i32m1_mu(mask,merge,op1,op2,32); +} + + +vint32m2_t test___riscv_vwmul_vv_i32m2_mu(vbool16_t mask,vint32m2_t merge,vint16m1_t op1,vint16m1_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i32m2_mu(mask,merge,op1,op2,32); +} + + +vint32m4_t test___riscv_vwmul_vv_i32m4_mu(vbool8_t mask,vint32m4_t merge,vint16m2_t op1,vint16m2_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i32m4_mu(mask,merge,op1,op2,32); +} + + +vint32m8_t test___riscv_vwmul_vv_i32m8_mu(vbool4_t mask,vint32m8_t merge,vint16m4_t op1,vint16m4_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i32m8_mu(mask,merge,op1,op2,32); +} + + +vint64m1_t test___riscv_vwmul_vv_i64m1_mu(vbool64_t mask,vint64m1_t merge,vint32mf2_t op1,vint32mf2_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i64m1_mu(mask,merge,op1,op2,32); +} + + +vint64m2_t test___riscv_vwmul_vv_i64m2_mu(vbool32_t mask,vint64m2_t merge,vint32m1_t op1,vint32m1_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i64m2_mu(mask,merge,op1,op2,32); +} + + +vint64m4_t test___riscv_vwmul_vv_i64m4_mu(vbool16_t mask,vint64m4_t merge,vint32m2_t op1,vint32m2_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i64m4_mu(mask,merge,op1,op2,32); +} + + +vint64m8_t test___riscv_vwmul_vv_i64m8_mu(vbool8_t mask,vint64m8_t merge,vint32m4_t op1,vint32m4_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i64m8_mu(mask,merge,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmul_vv_tu-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmul_vv_tu-1.c new file mode 100644 index 00000000000..2d8f8e91cf3 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmul_vv_tu-1.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwmul_vv_i16mf4_tu(vint16mf4_t merge,vint8mf8_t op1,vint8mf8_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i16mf4_tu(merge,op1,op2,vl); +} + + +vint16mf2_t test___riscv_vwmul_vv_i16mf2_tu(vint16mf2_t merge,vint8mf4_t op1,vint8mf4_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i16mf2_tu(merge,op1,op2,vl); +} + + +vint16m1_t test___riscv_vwmul_vv_i16m1_tu(vint16m1_t merge,vint8mf2_t op1,vint8mf2_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i16m1_tu(merge,op1,op2,vl); +} + + +vint16m2_t test___riscv_vwmul_vv_i16m2_tu(vint16m2_t merge,vint8m1_t op1,vint8m1_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i16m2_tu(merge,op1,op2,vl); +} + + +vint16m4_t test___riscv_vwmul_vv_i16m4_tu(vint16m4_t merge,vint8m2_t op1,vint8m2_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i16m4_tu(merge,op1,op2,vl); +} + + +vint16m8_t test___riscv_vwmul_vv_i16m8_tu(vint16m8_t merge,vint8m4_t op1,vint8m4_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i16m8_tu(merge,op1,op2,vl); +} + + +vint32mf2_t test___riscv_vwmul_vv_i32mf2_tu(vint32mf2_t merge,vint16mf4_t op1,vint16mf4_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i32mf2_tu(merge,op1,op2,vl); +} + + +vint32m1_t test___riscv_vwmul_vv_i32m1_tu(vint32m1_t merge,vint16mf2_t op1,vint16mf2_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i32m1_tu(merge,op1,op2,vl); +} + + +vint32m2_t test___riscv_vwmul_vv_i32m2_tu(vint32m2_t merge,vint16m1_t op1,vint16m1_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i32m2_tu(merge,op1,op2,vl); +} + + +vint32m4_t test___riscv_vwmul_vv_i32m4_tu(vint32m4_t merge,vint16m2_t op1,vint16m2_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i32m4_tu(merge,op1,op2,vl); +} + + +vint32m8_t test___riscv_vwmul_vv_i32m8_tu(vint32m8_t merge,vint16m4_t op1,vint16m4_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i32m8_tu(merge,op1,op2,vl); +} + + +vint64m1_t test___riscv_vwmul_vv_i64m1_tu(vint64m1_t merge,vint32mf2_t op1,vint32mf2_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i64m1_tu(merge,op1,op2,vl); +} + + +vint64m2_t test___riscv_vwmul_vv_i64m2_tu(vint64m2_t merge,vint32m1_t op1,vint32m1_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i64m2_tu(merge,op1,op2,vl); +} + + +vint64m4_t test___riscv_vwmul_vv_i64m4_tu(vint64m4_t merge,vint32m2_t op1,vint32m2_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i64m4_tu(merge,op1,op2,vl); +} + + +vint64m8_t test___riscv_vwmul_vv_i64m8_tu(vint64m8_t merge,vint32m4_t op1,vint32m4_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i64m8_tu(merge,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmul_vv_tu-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmul_vv_tu-2.c new file mode 100644 index 00000000000..b32c2fd734d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmul_vv_tu-2.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwmul_vv_i16mf4_tu(vint16mf4_t merge,vint8mf8_t op1,vint8mf8_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i16mf4_tu(merge,op1,op2,31); +} + + +vint16mf2_t test___riscv_vwmul_vv_i16mf2_tu(vint16mf2_t merge,vint8mf4_t op1,vint8mf4_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i16mf2_tu(merge,op1,op2,31); +} + + +vint16m1_t test___riscv_vwmul_vv_i16m1_tu(vint16m1_t merge,vint8mf2_t op1,vint8mf2_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i16m1_tu(merge,op1,op2,31); +} + + +vint16m2_t test___riscv_vwmul_vv_i16m2_tu(vint16m2_t merge,vint8m1_t op1,vint8m1_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i16m2_tu(merge,op1,op2,31); +} + + +vint16m4_t test___riscv_vwmul_vv_i16m4_tu(vint16m4_t merge,vint8m2_t op1,vint8m2_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i16m4_tu(merge,op1,op2,31); +} + + +vint16m8_t test___riscv_vwmul_vv_i16m8_tu(vint16m8_t merge,vint8m4_t op1,vint8m4_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i16m8_tu(merge,op1,op2,31); +} + + +vint32mf2_t test___riscv_vwmul_vv_i32mf2_tu(vint32mf2_t merge,vint16mf4_t op1,vint16mf4_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i32mf2_tu(merge,op1,op2,31); +} + + +vint32m1_t test___riscv_vwmul_vv_i32m1_tu(vint32m1_t merge,vint16mf2_t op1,vint16mf2_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i32m1_tu(merge,op1,op2,31); +} + + +vint32m2_t test___riscv_vwmul_vv_i32m2_tu(vint32m2_t merge,vint16m1_t op1,vint16m1_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i32m2_tu(merge,op1,op2,31); +} + + +vint32m4_t test___riscv_vwmul_vv_i32m4_tu(vint32m4_t merge,vint16m2_t op1,vint16m2_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i32m4_tu(merge,op1,op2,31); +} + + +vint32m8_t test___riscv_vwmul_vv_i32m8_tu(vint32m8_t merge,vint16m4_t op1,vint16m4_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i32m8_tu(merge,op1,op2,31); +} + + +vint64m1_t test___riscv_vwmul_vv_i64m1_tu(vint64m1_t merge,vint32mf2_t op1,vint32mf2_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i64m1_tu(merge,op1,op2,31); +} + + +vint64m2_t test___riscv_vwmul_vv_i64m2_tu(vint64m2_t merge,vint32m1_t op1,vint32m1_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i64m2_tu(merge,op1,op2,31); +} + + +vint64m4_t test___riscv_vwmul_vv_i64m4_tu(vint64m4_t merge,vint32m2_t op1,vint32m2_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i64m4_tu(merge,op1,op2,31); +} + + +vint64m8_t test___riscv_vwmul_vv_i64m8_tu(vint64m8_t merge,vint32m4_t op1,vint32m4_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i64m8_tu(merge,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmul_vv_tu-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmul_vv_tu-3.c new file mode 100644 index 00000000000..7b1ad987578 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmul_vv_tu-3.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwmul_vv_i16mf4_tu(vint16mf4_t merge,vint8mf8_t op1,vint8mf8_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i16mf4_tu(merge,op1,op2,32); +} + + +vint16mf2_t test___riscv_vwmul_vv_i16mf2_tu(vint16mf2_t merge,vint8mf4_t op1,vint8mf4_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i16mf2_tu(merge,op1,op2,32); +} + + +vint16m1_t test___riscv_vwmul_vv_i16m1_tu(vint16m1_t merge,vint8mf2_t op1,vint8mf2_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i16m1_tu(merge,op1,op2,32); +} + + +vint16m2_t test___riscv_vwmul_vv_i16m2_tu(vint16m2_t merge,vint8m1_t op1,vint8m1_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i16m2_tu(merge,op1,op2,32); +} + + +vint16m4_t test___riscv_vwmul_vv_i16m4_tu(vint16m4_t merge,vint8m2_t op1,vint8m2_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i16m4_tu(merge,op1,op2,32); +} + + +vint16m8_t test___riscv_vwmul_vv_i16m8_tu(vint16m8_t merge,vint8m4_t op1,vint8m4_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i16m8_tu(merge,op1,op2,32); +} + + +vint32mf2_t test___riscv_vwmul_vv_i32mf2_tu(vint32mf2_t merge,vint16mf4_t op1,vint16mf4_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i32mf2_tu(merge,op1,op2,32); +} + + +vint32m1_t test___riscv_vwmul_vv_i32m1_tu(vint32m1_t merge,vint16mf2_t op1,vint16mf2_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i32m1_tu(merge,op1,op2,32); +} + + +vint32m2_t test___riscv_vwmul_vv_i32m2_tu(vint32m2_t merge,vint16m1_t op1,vint16m1_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i32m2_tu(merge,op1,op2,32); +} + + +vint32m4_t test___riscv_vwmul_vv_i32m4_tu(vint32m4_t merge,vint16m2_t op1,vint16m2_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i32m4_tu(merge,op1,op2,32); +} + + +vint32m8_t test___riscv_vwmul_vv_i32m8_tu(vint32m8_t merge,vint16m4_t op1,vint16m4_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i32m8_tu(merge,op1,op2,32); +} + + +vint64m1_t test___riscv_vwmul_vv_i64m1_tu(vint64m1_t merge,vint32mf2_t op1,vint32mf2_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i64m1_tu(merge,op1,op2,32); +} + + +vint64m2_t test___riscv_vwmul_vv_i64m2_tu(vint64m2_t merge,vint32m1_t op1,vint32m1_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i64m2_tu(merge,op1,op2,32); +} + + +vint64m4_t test___riscv_vwmul_vv_i64m4_tu(vint64m4_t merge,vint32m2_t op1,vint32m2_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i64m4_tu(merge,op1,op2,32); +} + + +vint64m8_t test___riscv_vwmul_vv_i64m8_tu(vint64m8_t merge,vint32m4_t op1,vint32m4_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i64m8_tu(merge,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmul_vv_tum-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmul_vv_tum-1.c new file mode 100644 index 00000000000..bb8630997a7 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmul_vv_tum-1.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwmul_vv_i16mf4_tum(vbool64_t mask,vint16mf4_t merge,vint8mf8_t op1,vint8mf8_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i16mf4_tum(mask,merge,op1,op2,vl); +} + + +vint16mf2_t test___riscv_vwmul_vv_i16mf2_tum(vbool32_t mask,vint16mf2_t merge,vint8mf4_t op1,vint8mf4_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i16mf2_tum(mask,merge,op1,op2,vl); +} + + +vint16m1_t test___riscv_vwmul_vv_i16m1_tum(vbool16_t mask,vint16m1_t merge,vint8mf2_t op1,vint8mf2_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i16m1_tum(mask,merge,op1,op2,vl); +} + + +vint16m2_t test___riscv_vwmul_vv_i16m2_tum(vbool8_t mask,vint16m2_t merge,vint8m1_t op1,vint8m1_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i16m2_tum(mask,merge,op1,op2,vl); +} + + +vint16m4_t test___riscv_vwmul_vv_i16m4_tum(vbool4_t mask,vint16m4_t merge,vint8m2_t op1,vint8m2_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i16m4_tum(mask,merge,op1,op2,vl); +} + + +vint16m8_t test___riscv_vwmul_vv_i16m8_tum(vbool2_t mask,vint16m8_t merge,vint8m4_t op1,vint8m4_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i16m8_tum(mask,merge,op1,op2,vl); +} + + +vint32mf2_t test___riscv_vwmul_vv_i32mf2_tum(vbool64_t mask,vint32mf2_t merge,vint16mf4_t op1,vint16mf4_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i32mf2_tum(mask,merge,op1,op2,vl); +} + + +vint32m1_t test___riscv_vwmul_vv_i32m1_tum(vbool32_t mask,vint32m1_t merge,vint16mf2_t op1,vint16mf2_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i32m1_tum(mask,merge,op1,op2,vl); +} + + +vint32m2_t test___riscv_vwmul_vv_i32m2_tum(vbool16_t mask,vint32m2_t merge,vint16m1_t op1,vint16m1_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i32m2_tum(mask,merge,op1,op2,vl); +} + + +vint32m4_t test___riscv_vwmul_vv_i32m4_tum(vbool8_t mask,vint32m4_t merge,vint16m2_t op1,vint16m2_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i32m4_tum(mask,merge,op1,op2,vl); +} + + +vint32m8_t test___riscv_vwmul_vv_i32m8_tum(vbool4_t mask,vint32m8_t merge,vint16m4_t op1,vint16m4_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i32m8_tum(mask,merge,op1,op2,vl); +} + + +vint64m1_t test___riscv_vwmul_vv_i64m1_tum(vbool64_t mask,vint64m1_t merge,vint32mf2_t op1,vint32mf2_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i64m1_tum(mask,merge,op1,op2,vl); +} + + +vint64m2_t test___riscv_vwmul_vv_i64m2_tum(vbool32_t mask,vint64m2_t merge,vint32m1_t op1,vint32m1_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i64m2_tum(mask,merge,op1,op2,vl); +} + + +vint64m4_t test___riscv_vwmul_vv_i64m4_tum(vbool16_t mask,vint64m4_t merge,vint32m2_t op1,vint32m2_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i64m4_tum(mask,merge,op1,op2,vl); +} + + +vint64m8_t test___riscv_vwmul_vv_i64m8_tum(vbool8_t mask,vint64m8_t merge,vint32m4_t op1,vint32m4_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i64m8_tum(mask,merge,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmul_vv_tum-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmul_vv_tum-2.c new file mode 100644 index 00000000000..54c6870c2d0 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmul_vv_tum-2.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwmul_vv_i16mf4_tum(vbool64_t mask,vint16mf4_t merge,vint8mf8_t op1,vint8mf8_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i16mf4_tum(mask,merge,op1,op2,31); +} + + +vint16mf2_t test___riscv_vwmul_vv_i16mf2_tum(vbool32_t mask,vint16mf2_t merge,vint8mf4_t op1,vint8mf4_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i16mf2_tum(mask,merge,op1,op2,31); +} + + +vint16m1_t test___riscv_vwmul_vv_i16m1_tum(vbool16_t mask,vint16m1_t merge,vint8mf2_t op1,vint8mf2_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i16m1_tum(mask,merge,op1,op2,31); +} + + +vint16m2_t test___riscv_vwmul_vv_i16m2_tum(vbool8_t mask,vint16m2_t merge,vint8m1_t op1,vint8m1_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i16m2_tum(mask,merge,op1,op2,31); +} + + +vint16m4_t test___riscv_vwmul_vv_i16m4_tum(vbool4_t mask,vint16m4_t merge,vint8m2_t op1,vint8m2_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i16m4_tum(mask,merge,op1,op2,31); +} + + +vint16m8_t test___riscv_vwmul_vv_i16m8_tum(vbool2_t mask,vint16m8_t merge,vint8m4_t op1,vint8m4_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i16m8_tum(mask,merge,op1,op2,31); +} + + +vint32mf2_t test___riscv_vwmul_vv_i32mf2_tum(vbool64_t mask,vint32mf2_t merge,vint16mf4_t op1,vint16mf4_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i32mf2_tum(mask,merge,op1,op2,31); +} + + +vint32m1_t test___riscv_vwmul_vv_i32m1_tum(vbool32_t mask,vint32m1_t merge,vint16mf2_t op1,vint16mf2_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i32m1_tum(mask,merge,op1,op2,31); +} + + +vint32m2_t test___riscv_vwmul_vv_i32m2_tum(vbool16_t mask,vint32m2_t merge,vint16m1_t op1,vint16m1_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i32m2_tum(mask,merge,op1,op2,31); +} + + +vint32m4_t test___riscv_vwmul_vv_i32m4_tum(vbool8_t mask,vint32m4_t merge,vint16m2_t op1,vint16m2_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i32m4_tum(mask,merge,op1,op2,31); +} + + +vint32m8_t test___riscv_vwmul_vv_i32m8_tum(vbool4_t mask,vint32m8_t merge,vint16m4_t op1,vint16m4_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i32m8_tum(mask,merge,op1,op2,31); +} + + +vint64m1_t test___riscv_vwmul_vv_i64m1_tum(vbool64_t mask,vint64m1_t merge,vint32mf2_t op1,vint32mf2_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i64m1_tum(mask,merge,op1,op2,31); +} + + +vint64m2_t test___riscv_vwmul_vv_i64m2_tum(vbool32_t mask,vint64m2_t merge,vint32m1_t op1,vint32m1_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i64m2_tum(mask,merge,op1,op2,31); +} + + +vint64m4_t test___riscv_vwmul_vv_i64m4_tum(vbool16_t mask,vint64m4_t merge,vint32m2_t op1,vint32m2_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i64m4_tum(mask,merge,op1,op2,31); +} + + +vint64m8_t test___riscv_vwmul_vv_i64m8_tum(vbool8_t mask,vint64m8_t merge,vint32m4_t op1,vint32m4_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i64m8_tum(mask,merge,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmul_vv_tum-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmul_vv_tum-3.c new file mode 100644 index 00000000000..8ac3881d79d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmul_vv_tum-3.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwmul_vv_i16mf4_tum(vbool64_t mask,vint16mf4_t merge,vint8mf8_t op1,vint8mf8_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i16mf4_tum(mask,merge,op1,op2,32); +} + + +vint16mf2_t test___riscv_vwmul_vv_i16mf2_tum(vbool32_t mask,vint16mf2_t merge,vint8mf4_t op1,vint8mf4_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i16mf2_tum(mask,merge,op1,op2,32); +} + + +vint16m1_t test___riscv_vwmul_vv_i16m1_tum(vbool16_t mask,vint16m1_t merge,vint8mf2_t op1,vint8mf2_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i16m1_tum(mask,merge,op1,op2,32); +} + + +vint16m2_t test___riscv_vwmul_vv_i16m2_tum(vbool8_t mask,vint16m2_t merge,vint8m1_t op1,vint8m1_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i16m2_tum(mask,merge,op1,op2,32); +} + + +vint16m4_t test___riscv_vwmul_vv_i16m4_tum(vbool4_t mask,vint16m4_t merge,vint8m2_t op1,vint8m2_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i16m4_tum(mask,merge,op1,op2,32); +} + + +vint16m8_t test___riscv_vwmul_vv_i16m8_tum(vbool2_t mask,vint16m8_t merge,vint8m4_t op1,vint8m4_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i16m8_tum(mask,merge,op1,op2,32); +} + + +vint32mf2_t test___riscv_vwmul_vv_i32mf2_tum(vbool64_t mask,vint32mf2_t merge,vint16mf4_t op1,vint16mf4_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i32mf2_tum(mask,merge,op1,op2,32); +} + + +vint32m1_t test___riscv_vwmul_vv_i32m1_tum(vbool32_t mask,vint32m1_t merge,vint16mf2_t op1,vint16mf2_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i32m1_tum(mask,merge,op1,op2,32); +} + + +vint32m2_t test___riscv_vwmul_vv_i32m2_tum(vbool16_t mask,vint32m2_t merge,vint16m1_t op1,vint16m1_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i32m2_tum(mask,merge,op1,op2,32); +} + + +vint32m4_t test___riscv_vwmul_vv_i32m4_tum(vbool8_t mask,vint32m4_t merge,vint16m2_t op1,vint16m2_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i32m4_tum(mask,merge,op1,op2,32); +} + + +vint32m8_t test___riscv_vwmul_vv_i32m8_tum(vbool4_t mask,vint32m8_t merge,vint16m4_t op1,vint16m4_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i32m8_tum(mask,merge,op1,op2,32); +} + + +vint64m1_t test___riscv_vwmul_vv_i64m1_tum(vbool64_t mask,vint64m1_t merge,vint32mf2_t op1,vint32mf2_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i64m1_tum(mask,merge,op1,op2,32); +} + + +vint64m2_t test___riscv_vwmul_vv_i64m2_tum(vbool32_t mask,vint64m2_t merge,vint32m1_t op1,vint32m1_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i64m2_tum(mask,merge,op1,op2,32); +} + + +vint64m4_t test___riscv_vwmul_vv_i64m4_tum(vbool16_t mask,vint64m4_t merge,vint32m2_t op1,vint32m2_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i64m4_tum(mask,merge,op1,op2,32); +} + + +vint64m8_t test___riscv_vwmul_vv_i64m8_tum(vbool8_t mask,vint64m8_t merge,vint32m4_t op1,vint32m4_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i64m8_tum(mask,merge,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmul_vv_tumu-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmul_vv_tumu-1.c new file mode 100644 index 00000000000..bc9d79b446a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmul_vv_tumu-1.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwmul_vv_i16mf4_tumu(vbool64_t mask,vint16mf4_t merge,vint8mf8_t op1,vint8mf8_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i16mf4_tumu(mask,merge,op1,op2,vl); +} + + +vint16mf2_t test___riscv_vwmul_vv_i16mf2_tumu(vbool32_t mask,vint16mf2_t merge,vint8mf4_t op1,vint8mf4_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i16mf2_tumu(mask,merge,op1,op2,vl); +} + + +vint16m1_t test___riscv_vwmul_vv_i16m1_tumu(vbool16_t mask,vint16m1_t merge,vint8mf2_t op1,vint8mf2_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i16m1_tumu(mask,merge,op1,op2,vl); +} + + +vint16m2_t test___riscv_vwmul_vv_i16m2_tumu(vbool8_t mask,vint16m2_t merge,vint8m1_t op1,vint8m1_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i16m2_tumu(mask,merge,op1,op2,vl); +} + + +vint16m4_t test___riscv_vwmul_vv_i16m4_tumu(vbool4_t mask,vint16m4_t merge,vint8m2_t op1,vint8m2_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i16m4_tumu(mask,merge,op1,op2,vl); +} + + +vint16m8_t test___riscv_vwmul_vv_i16m8_tumu(vbool2_t mask,vint16m8_t merge,vint8m4_t op1,vint8m4_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i16m8_tumu(mask,merge,op1,op2,vl); +} + + +vint32mf2_t test___riscv_vwmul_vv_i32mf2_tumu(vbool64_t mask,vint32mf2_t merge,vint16mf4_t op1,vint16mf4_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i32mf2_tumu(mask,merge,op1,op2,vl); +} + + +vint32m1_t test___riscv_vwmul_vv_i32m1_tumu(vbool32_t mask,vint32m1_t merge,vint16mf2_t op1,vint16mf2_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i32m1_tumu(mask,merge,op1,op2,vl); +} + + +vint32m2_t test___riscv_vwmul_vv_i32m2_tumu(vbool16_t mask,vint32m2_t merge,vint16m1_t op1,vint16m1_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i32m2_tumu(mask,merge,op1,op2,vl); +} + + +vint32m4_t test___riscv_vwmul_vv_i32m4_tumu(vbool8_t mask,vint32m4_t merge,vint16m2_t op1,vint16m2_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i32m4_tumu(mask,merge,op1,op2,vl); +} + + +vint32m8_t test___riscv_vwmul_vv_i32m8_tumu(vbool4_t mask,vint32m8_t merge,vint16m4_t op1,vint16m4_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i32m8_tumu(mask,merge,op1,op2,vl); +} + + +vint64m1_t test___riscv_vwmul_vv_i64m1_tumu(vbool64_t mask,vint64m1_t merge,vint32mf2_t op1,vint32mf2_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i64m1_tumu(mask,merge,op1,op2,vl); +} + + +vint64m2_t test___riscv_vwmul_vv_i64m2_tumu(vbool32_t mask,vint64m2_t merge,vint32m1_t op1,vint32m1_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i64m2_tumu(mask,merge,op1,op2,vl); +} + + +vint64m4_t test___riscv_vwmul_vv_i64m4_tumu(vbool16_t mask,vint64m4_t merge,vint32m2_t op1,vint32m2_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i64m4_tumu(mask,merge,op1,op2,vl); +} + + +vint64m8_t test___riscv_vwmul_vv_i64m8_tumu(vbool8_t mask,vint64m8_t merge,vint32m4_t op1,vint32m4_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i64m8_tumu(mask,merge,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmul_vv_tumu-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmul_vv_tumu-2.c new file mode 100644 index 00000000000..3a2b88e9a0f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmul_vv_tumu-2.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwmul_vv_i16mf4_tumu(vbool64_t mask,vint16mf4_t merge,vint8mf8_t op1,vint8mf8_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i16mf4_tumu(mask,merge,op1,op2,31); +} + + +vint16mf2_t test___riscv_vwmul_vv_i16mf2_tumu(vbool32_t mask,vint16mf2_t merge,vint8mf4_t op1,vint8mf4_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i16mf2_tumu(mask,merge,op1,op2,31); +} + + +vint16m1_t test___riscv_vwmul_vv_i16m1_tumu(vbool16_t mask,vint16m1_t merge,vint8mf2_t op1,vint8mf2_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i16m1_tumu(mask,merge,op1,op2,31); +} + + +vint16m2_t test___riscv_vwmul_vv_i16m2_tumu(vbool8_t mask,vint16m2_t merge,vint8m1_t op1,vint8m1_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i16m2_tumu(mask,merge,op1,op2,31); +} + + +vint16m4_t test___riscv_vwmul_vv_i16m4_tumu(vbool4_t mask,vint16m4_t merge,vint8m2_t op1,vint8m2_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i16m4_tumu(mask,merge,op1,op2,31); +} + + +vint16m8_t test___riscv_vwmul_vv_i16m8_tumu(vbool2_t mask,vint16m8_t merge,vint8m4_t op1,vint8m4_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i16m8_tumu(mask,merge,op1,op2,31); +} + + +vint32mf2_t test___riscv_vwmul_vv_i32mf2_tumu(vbool64_t mask,vint32mf2_t merge,vint16mf4_t op1,vint16mf4_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i32mf2_tumu(mask,merge,op1,op2,31); +} + + +vint32m1_t test___riscv_vwmul_vv_i32m1_tumu(vbool32_t mask,vint32m1_t merge,vint16mf2_t op1,vint16mf2_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i32m1_tumu(mask,merge,op1,op2,31); +} + + +vint32m2_t test___riscv_vwmul_vv_i32m2_tumu(vbool16_t mask,vint32m2_t merge,vint16m1_t op1,vint16m1_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i32m2_tumu(mask,merge,op1,op2,31); +} + + +vint32m4_t test___riscv_vwmul_vv_i32m4_tumu(vbool8_t mask,vint32m4_t merge,vint16m2_t op1,vint16m2_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i32m4_tumu(mask,merge,op1,op2,31); +} + + +vint32m8_t test___riscv_vwmul_vv_i32m8_tumu(vbool4_t mask,vint32m8_t merge,vint16m4_t op1,vint16m4_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i32m8_tumu(mask,merge,op1,op2,31); +} + + +vint64m1_t test___riscv_vwmul_vv_i64m1_tumu(vbool64_t mask,vint64m1_t merge,vint32mf2_t op1,vint32mf2_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i64m1_tumu(mask,merge,op1,op2,31); +} + + +vint64m2_t test___riscv_vwmul_vv_i64m2_tumu(vbool32_t mask,vint64m2_t merge,vint32m1_t op1,vint32m1_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i64m2_tumu(mask,merge,op1,op2,31); +} + + +vint64m4_t test___riscv_vwmul_vv_i64m4_tumu(vbool16_t mask,vint64m4_t merge,vint32m2_t op1,vint32m2_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i64m4_tumu(mask,merge,op1,op2,31); +} + + +vint64m8_t test___riscv_vwmul_vv_i64m8_tumu(vbool8_t mask,vint64m8_t merge,vint32m4_t op1,vint32m4_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i64m8_tumu(mask,merge,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmul_vv_tumu-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmul_vv_tumu-3.c new file mode 100644 index 00000000000..5e8c263ce03 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmul_vv_tumu-3.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwmul_vv_i16mf4_tumu(vbool64_t mask,vint16mf4_t merge,vint8mf8_t op1,vint8mf8_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i16mf4_tumu(mask,merge,op1,op2,32); +} + + +vint16mf2_t test___riscv_vwmul_vv_i16mf2_tumu(vbool32_t mask,vint16mf2_t merge,vint8mf4_t op1,vint8mf4_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i16mf2_tumu(mask,merge,op1,op2,32); +} + + +vint16m1_t test___riscv_vwmul_vv_i16m1_tumu(vbool16_t mask,vint16m1_t merge,vint8mf2_t op1,vint8mf2_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i16m1_tumu(mask,merge,op1,op2,32); +} + + +vint16m2_t test___riscv_vwmul_vv_i16m2_tumu(vbool8_t mask,vint16m2_t merge,vint8m1_t op1,vint8m1_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i16m2_tumu(mask,merge,op1,op2,32); +} + + +vint16m4_t test___riscv_vwmul_vv_i16m4_tumu(vbool4_t mask,vint16m4_t merge,vint8m2_t op1,vint8m2_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i16m4_tumu(mask,merge,op1,op2,32); +} + + +vint16m8_t test___riscv_vwmul_vv_i16m8_tumu(vbool2_t mask,vint16m8_t merge,vint8m4_t op1,vint8m4_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i16m8_tumu(mask,merge,op1,op2,32); +} + + +vint32mf2_t test___riscv_vwmul_vv_i32mf2_tumu(vbool64_t mask,vint32mf2_t merge,vint16mf4_t op1,vint16mf4_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i32mf2_tumu(mask,merge,op1,op2,32); +} + + +vint32m1_t test___riscv_vwmul_vv_i32m1_tumu(vbool32_t mask,vint32m1_t merge,vint16mf2_t op1,vint16mf2_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i32m1_tumu(mask,merge,op1,op2,32); +} + + +vint32m2_t test___riscv_vwmul_vv_i32m2_tumu(vbool16_t mask,vint32m2_t merge,vint16m1_t op1,vint16m1_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i32m2_tumu(mask,merge,op1,op2,32); +} + + +vint32m4_t test___riscv_vwmul_vv_i32m4_tumu(vbool8_t mask,vint32m4_t merge,vint16m2_t op1,vint16m2_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i32m4_tumu(mask,merge,op1,op2,32); +} + + +vint32m8_t test___riscv_vwmul_vv_i32m8_tumu(vbool4_t mask,vint32m8_t merge,vint16m4_t op1,vint16m4_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i32m8_tumu(mask,merge,op1,op2,32); +} + + +vint64m1_t test___riscv_vwmul_vv_i64m1_tumu(vbool64_t mask,vint64m1_t merge,vint32mf2_t op1,vint32mf2_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i64m1_tumu(mask,merge,op1,op2,32); +} + + +vint64m2_t test___riscv_vwmul_vv_i64m2_tumu(vbool32_t mask,vint64m2_t merge,vint32m1_t op1,vint32m1_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i64m2_tumu(mask,merge,op1,op2,32); +} + + +vint64m4_t test___riscv_vwmul_vv_i64m4_tumu(vbool16_t mask,vint64m4_t merge,vint32m2_t op1,vint32m2_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i64m4_tumu(mask,merge,op1,op2,32); +} + + +vint64m8_t test___riscv_vwmul_vv_i64m8_tumu(vbool8_t mask,vint64m8_t merge,vint32m4_t op1,vint32m4_t op2,size_t vl) +{ + return __riscv_vwmul_vv_i64m8_tumu(mask,merge,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmul_vx-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmul_vx-1.c new file mode 100644 index 00000000000..8800d21e95f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmul_vx-1.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwmul_vx_i16mf4(vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i16mf4(op1,op2,vl); +} + + +vint16mf2_t test___riscv_vwmul_vx_i16mf2(vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i16mf2(op1,op2,vl); +} + + +vint16m1_t test___riscv_vwmul_vx_i16m1(vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i16m1(op1,op2,vl); +} + + +vint16m2_t test___riscv_vwmul_vx_i16m2(vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i16m2(op1,op2,vl); +} + + +vint16m4_t test___riscv_vwmul_vx_i16m4(vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i16m4(op1,op2,vl); +} + + +vint16m8_t test___riscv_vwmul_vx_i16m8(vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i16m8(op1,op2,vl); +} + + +vint32mf2_t test___riscv_vwmul_vx_i32mf2(vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i32mf2(op1,op2,vl); +} + + +vint32m1_t test___riscv_vwmul_vx_i32m1(vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i32m1(op1,op2,vl); +} + + +vint32m2_t test___riscv_vwmul_vx_i32m2(vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i32m2(op1,op2,vl); +} + + +vint32m4_t test___riscv_vwmul_vx_i32m4(vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i32m4(op1,op2,vl); +} + + +vint32m8_t test___riscv_vwmul_vx_i32m8(vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i32m8(op1,op2,vl); +} + + +vint64m1_t test___riscv_vwmul_vx_i64m1(vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i64m1(op1,op2,vl); +} + + +vint64m2_t test___riscv_vwmul_vx_i64m2(vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i64m2(op1,op2,vl); +} + + +vint64m4_t test___riscv_vwmul_vx_i64m4(vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i64m4(op1,op2,vl); +} + + +vint64m8_t test___riscv_vwmul_vx_i64m8(vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i64m8(op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmul_vx-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmul_vx-2.c new file mode 100644 index 00000000000..87ce345436b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmul_vx-2.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwmul_vx_i16mf4(vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i16mf4(op1,op2,31); +} + + +vint16mf2_t test___riscv_vwmul_vx_i16mf2(vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i16mf2(op1,op2,31); +} + + +vint16m1_t test___riscv_vwmul_vx_i16m1(vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i16m1(op1,op2,31); +} + + +vint16m2_t test___riscv_vwmul_vx_i16m2(vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i16m2(op1,op2,31); +} + + +vint16m4_t test___riscv_vwmul_vx_i16m4(vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i16m4(op1,op2,31); +} + + +vint16m8_t test___riscv_vwmul_vx_i16m8(vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i16m8(op1,op2,31); +} + + +vint32mf2_t test___riscv_vwmul_vx_i32mf2(vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i32mf2(op1,op2,31); +} + + +vint32m1_t test___riscv_vwmul_vx_i32m1(vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i32m1(op1,op2,31); +} + + +vint32m2_t test___riscv_vwmul_vx_i32m2(vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i32m2(op1,op2,31); +} + + +vint32m4_t test___riscv_vwmul_vx_i32m4(vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i32m4(op1,op2,31); +} + + +vint32m8_t test___riscv_vwmul_vx_i32m8(vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i32m8(op1,op2,31); +} + + +vint64m1_t test___riscv_vwmul_vx_i64m1(vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i64m1(op1,op2,31); +} + + +vint64m2_t test___riscv_vwmul_vx_i64m2(vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i64m2(op1,op2,31); +} + + +vint64m4_t test___riscv_vwmul_vx_i64m4(vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i64m4(op1,op2,31); +} + + +vint64m8_t test___riscv_vwmul_vx_i64m8(vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i64m8(op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmul_vx-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmul_vx-3.c new file mode 100644 index 00000000000..12872d51fa5 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmul_vx-3.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwmul_vx_i16mf4(vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i16mf4(op1,op2,32); +} + + +vint16mf2_t test___riscv_vwmul_vx_i16mf2(vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i16mf2(op1,op2,32); +} + + +vint16m1_t test___riscv_vwmul_vx_i16m1(vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i16m1(op1,op2,32); +} + + +vint16m2_t test___riscv_vwmul_vx_i16m2(vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i16m2(op1,op2,32); +} + + +vint16m4_t test___riscv_vwmul_vx_i16m4(vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i16m4(op1,op2,32); +} + + +vint16m8_t test___riscv_vwmul_vx_i16m8(vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i16m8(op1,op2,32); +} + + +vint32mf2_t test___riscv_vwmul_vx_i32mf2(vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i32mf2(op1,op2,32); +} + + +vint32m1_t test___riscv_vwmul_vx_i32m1(vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i32m1(op1,op2,32); +} + + +vint32m2_t test___riscv_vwmul_vx_i32m2(vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i32m2(op1,op2,32); +} + + +vint32m4_t test___riscv_vwmul_vx_i32m4(vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i32m4(op1,op2,32); +} + + +vint32m8_t test___riscv_vwmul_vx_i32m8(vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i32m8(op1,op2,32); +} + + +vint64m1_t test___riscv_vwmul_vx_i64m1(vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i64m1(op1,op2,32); +} + + +vint64m2_t test___riscv_vwmul_vx_i64m2(vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i64m2(op1,op2,32); +} + + +vint64m4_t test___riscv_vwmul_vx_i64m4(vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i64m4(op1,op2,32); +} + + +vint64m8_t test___riscv_vwmul_vx_i64m8(vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i64m8(op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmul_vx_m-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmul_vx_m-1.c new file mode 100644 index 00000000000..4a13f789843 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmul_vx_m-1.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwmul_vx_i16mf4_m(vbool64_t mask,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i16mf4_m(mask,op1,op2,vl); +} + + +vint16mf2_t test___riscv_vwmul_vx_i16mf2_m(vbool32_t mask,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i16mf2_m(mask,op1,op2,vl); +} + + +vint16m1_t test___riscv_vwmul_vx_i16m1_m(vbool16_t mask,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i16m1_m(mask,op1,op2,vl); +} + + +vint16m2_t test___riscv_vwmul_vx_i16m2_m(vbool8_t mask,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i16m2_m(mask,op1,op2,vl); +} + + +vint16m4_t test___riscv_vwmul_vx_i16m4_m(vbool4_t mask,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i16m4_m(mask,op1,op2,vl); +} + + +vint16m8_t test___riscv_vwmul_vx_i16m8_m(vbool2_t mask,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i16m8_m(mask,op1,op2,vl); +} + + +vint32mf2_t test___riscv_vwmul_vx_i32mf2_m(vbool64_t mask,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i32mf2_m(mask,op1,op2,vl); +} + + +vint32m1_t test___riscv_vwmul_vx_i32m1_m(vbool32_t mask,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i32m1_m(mask,op1,op2,vl); +} + + +vint32m2_t test___riscv_vwmul_vx_i32m2_m(vbool16_t mask,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i32m2_m(mask,op1,op2,vl); +} + + +vint32m4_t test___riscv_vwmul_vx_i32m4_m(vbool8_t mask,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i32m4_m(mask,op1,op2,vl); +} + + +vint32m8_t test___riscv_vwmul_vx_i32m8_m(vbool4_t mask,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i32m8_m(mask,op1,op2,vl); +} + + +vint64m1_t test___riscv_vwmul_vx_i64m1_m(vbool64_t mask,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i64m1_m(mask,op1,op2,vl); +} + + +vint64m2_t test___riscv_vwmul_vx_i64m2_m(vbool32_t mask,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i64m2_m(mask,op1,op2,vl); +} + + +vint64m4_t test___riscv_vwmul_vx_i64m4_m(vbool16_t mask,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i64m4_m(mask,op1,op2,vl); +} + + +vint64m8_t test___riscv_vwmul_vx_i64m8_m(vbool8_t mask,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i64m8_m(mask,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmul_vx_m-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmul_vx_m-2.c new file mode 100644 index 00000000000..bfde5422947 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmul_vx_m-2.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwmul_vx_i16mf4_m(vbool64_t mask,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i16mf4_m(mask,op1,op2,31); +} + + +vint16mf2_t test___riscv_vwmul_vx_i16mf2_m(vbool32_t mask,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i16mf2_m(mask,op1,op2,31); +} + + +vint16m1_t test___riscv_vwmul_vx_i16m1_m(vbool16_t mask,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i16m1_m(mask,op1,op2,31); +} + + +vint16m2_t test___riscv_vwmul_vx_i16m2_m(vbool8_t mask,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i16m2_m(mask,op1,op2,31); +} + + +vint16m4_t test___riscv_vwmul_vx_i16m4_m(vbool4_t mask,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i16m4_m(mask,op1,op2,31); +} + + +vint16m8_t test___riscv_vwmul_vx_i16m8_m(vbool2_t mask,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i16m8_m(mask,op1,op2,31); +} + + +vint32mf2_t test___riscv_vwmul_vx_i32mf2_m(vbool64_t mask,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i32mf2_m(mask,op1,op2,31); +} + + +vint32m1_t test___riscv_vwmul_vx_i32m1_m(vbool32_t mask,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i32m1_m(mask,op1,op2,31); +} + + +vint32m2_t test___riscv_vwmul_vx_i32m2_m(vbool16_t mask,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i32m2_m(mask,op1,op2,31); +} + + +vint32m4_t test___riscv_vwmul_vx_i32m4_m(vbool8_t mask,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i32m4_m(mask,op1,op2,31); +} + + +vint32m8_t test___riscv_vwmul_vx_i32m8_m(vbool4_t mask,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i32m8_m(mask,op1,op2,31); +} + + +vint64m1_t test___riscv_vwmul_vx_i64m1_m(vbool64_t mask,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i64m1_m(mask,op1,op2,31); +} + + +vint64m2_t test___riscv_vwmul_vx_i64m2_m(vbool32_t mask,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i64m2_m(mask,op1,op2,31); +} + + +vint64m4_t test___riscv_vwmul_vx_i64m4_m(vbool16_t mask,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i64m4_m(mask,op1,op2,31); +} + + +vint64m8_t test___riscv_vwmul_vx_i64m8_m(vbool8_t mask,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i64m8_m(mask,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmul_vx_m-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmul_vx_m-3.c new file mode 100644 index 00000000000..662754c611f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmul_vx_m-3.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwmul_vx_i16mf4_m(vbool64_t mask,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i16mf4_m(mask,op1,op2,32); +} + + +vint16mf2_t test___riscv_vwmul_vx_i16mf2_m(vbool32_t mask,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i16mf2_m(mask,op1,op2,32); +} + + +vint16m1_t test___riscv_vwmul_vx_i16m1_m(vbool16_t mask,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i16m1_m(mask,op1,op2,32); +} + + +vint16m2_t test___riscv_vwmul_vx_i16m2_m(vbool8_t mask,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i16m2_m(mask,op1,op2,32); +} + + +vint16m4_t test___riscv_vwmul_vx_i16m4_m(vbool4_t mask,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i16m4_m(mask,op1,op2,32); +} + + +vint16m8_t test___riscv_vwmul_vx_i16m8_m(vbool2_t mask,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i16m8_m(mask,op1,op2,32); +} + + +vint32mf2_t test___riscv_vwmul_vx_i32mf2_m(vbool64_t mask,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i32mf2_m(mask,op1,op2,32); +} + + +vint32m1_t test___riscv_vwmul_vx_i32m1_m(vbool32_t mask,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i32m1_m(mask,op1,op2,32); +} + + +vint32m2_t test___riscv_vwmul_vx_i32m2_m(vbool16_t mask,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i32m2_m(mask,op1,op2,32); +} + + +vint32m4_t test___riscv_vwmul_vx_i32m4_m(vbool8_t mask,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i32m4_m(mask,op1,op2,32); +} + + +vint32m8_t test___riscv_vwmul_vx_i32m8_m(vbool4_t mask,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i32m8_m(mask,op1,op2,32); +} + + +vint64m1_t test___riscv_vwmul_vx_i64m1_m(vbool64_t mask,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i64m1_m(mask,op1,op2,32); +} + + +vint64m2_t test___riscv_vwmul_vx_i64m2_m(vbool32_t mask,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i64m2_m(mask,op1,op2,32); +} + + +vint64m4_t test___riscv_vwmul_vx_i64m4_m(vbool16_t mask,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i64m4_m(mask,op1,op2,32); +} + + +vint64m8_t test___riscv_vwmul_vx_i64m8_m(vbool8_t mask,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i64m8_m(mask,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmul_vx_mu-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmul_vx_mu-1.c new file mode 100644 index 00000000000..97fe43ccea6 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmul_vx_mu-1.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwmul_vx_i16mf4_mu(vbool64_t mask,vint16mf4_t merge,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i16mf4_mu(mask,merge,op1,op2,vl); +} + + +vint16mf2_t test___riscv_vwmul_vx_i16mf2_mu(vbool32_t mask,vint16mf2_t merge,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i16mf2_mu(mask,merge,op1,op2,vl); +} + + +vint16m1_t test___riscv_vwmul_vx_i16m1_mu(vbool16_t mask,vint16m1_t merge,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i16m1_mu(mask,merge,op1,op2,vl); +} + + +vint16m2_t test___riscv_vwmul_vx_i16m2_mu(vbool8_t mask,vint16m2_t merge,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i16m2_mu(mask,merge,op1,op2,vl); +} + + +vint16m4_t test___riscv_vwmul_vx_i16m4_mu(vbool4_t mask,vint16m4_t merge,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i16m4_mu(mask,merge,op1,op2,vl); +} + + +vint16m8_t test___riscv_vwmul_vx_i16m8_mu(vbool2_t mask,vint16m8_t merge,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i16m8_mu(mask,merge,op1,op2,vl); +} + + +vint32mf2_t test___riscv_vwmul_vx_i32mf2_mu(vbool64_t mask,vint32mf2_t merge,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i32mf2_mu(mask,merge,op1,op2,vl); +} + + +vint32m1_t test___riscv_vwmul_vx_i32m1_mu(vbool32_t mask,vint32m1_t merge,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i32m1_mu(mask,merge,op1,op2,vl); +} + + +vint32m2_t test___riscv_vwmul_vx_i32m2_mu(vbool16_t mask,vint32m2_t merge,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i32m2_mu(mask,merge,op1,op2,vl); +} + + +vint32m4_t test___riscv_vwmul_vx_i32m4_mu(vbool8_t mask,vint32m4_t merge,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i32m4_mu(mask,merge,op1,op2,vl); +} + + +vint32m8_t test___riscv_vwmul_vx_i32m8_mu(vbool4_t mask,vint32m8_t merge,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i32m8_mu(mask,merge,op1,op2,vl); +} + + +vint64m1_t test___riscv_vwmul_vx_i64m1_mu(vbool64_t mask,vint64m1_t merge,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i64m1_mu(mask,merge,op1,op2,vl); +} + + +vint64m2_t test___riscv_vwmul_vx_i64m2_mu(vbool32_t mask,vint64m2_t merge,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i64m2_mu(mask,merge,op1,op2,vl); +} + + +vint64m4_t test___riscv_vwmul_vx_i64m4_mu(vbool16_t mask,vint64m4_t merge,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i64m4_mu(mask,merge,op1,op2,vl); +} + + +vint64m8_t test___riscv_vwmul_vx_i64m8_mu(vbool8_t mask,vint64m8_t merge,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i64m8_mu(mask,merge,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmul_vx_mu-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmul_vx_mu-2.c new file mode 100644 index 00000000000..554add8b096 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmul_vx_mu-2.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwmul_vx_i16mf4_mu(vbool64_t mask,vint16mf4_t merge,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i16mf4_mu(mask,merge,op1,op2,31); +} + + +vint16mf2_t test___riscv_vwmul_vx_i16mf2_mu(vbool32_t mask,vint16mf2_t merge,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i16mf2_mu(mask,merge,op1,op2,31); +} + + +vint16m1_t test___riscv_vwmul_vx_i16m1_mu(vbool16_t mask,vint16m1_t merge,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i16m1_mu(mask,merge,op1,op2,31); +} + + +vint16m2_t test___riscv_vwmul_vx_i16m2_mu(vbool8_t mask,vint16m2_t merge,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i16m2_mu(mask,merge,op1,op2,31); +} + + +vint16m4_t test___riscv_vwmul_vx_i16m4_mu(vbool4_t mask,vint16m4_t merge,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i16m4_mu(mask,merge,op1,op2,31); +} + + +vint16m8_t test___riscv_vwmul_vx_i16m8_mu(vbool2_t mask,vint16m8_t merge,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i16m8_mu(mask,merge,op1,op2,31); +} + + +vint32mf2_t test___riscv_vwmul_vx_i32mf2_mu(vbool64_t mask,vint32mf2_t merge,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i32mf2_mu(mask,merge,op1,op2,31); +} + + +vint32m1_t test___riscv_vwmul_vx_i32m1_mu(vbool32_t mask,vint32m1_t merge,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i32m1_mu(mask,merge,op1,op2,31); +} + + +vint32m2_t test___riscv_vwmul_vx_i32m2_mu(vbool16_t mask,vint32m2_t merge,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i32m2_mu(mask,merge,op1,op2,31); +} + + +vint32m4_t test___riscv_vwmul_vx_i32m4_mu(vbool8_t mask,vint32m4_t merge,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i32m4_mu(mask,merge,op1,op2,31); +} + + +vint32m8_t test___riscv_vwmul_vx_i32m8_mu(vbool4_t mask,vint32m8_t merge,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i32m8_mu(mask,merge,op1,op2,31); +} + + +vint64m1_t test___riscv_vwmul_vx_i64m1_mu(vbool64_t mask,vint64m1_t merge,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i64m1_mu(mask,merge,op1,op2,31); +} + + +vint64m2_t test___riscv_vwmul_vx_i64m2_mu(vbool32_t mask,vint64m2_t merge,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i64m2_mu(mask,merge,op1,op2,31); +} + + +vint64m4_t test___riscv_vwmul_vx_i64m4_mu(vbool16_t mask,vint64m4_t merge,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i64m4_mu(mask,merge,op1,op2,31); +} + + +vint64m8_t test___riscv_vwmul_vx_i64m8_mu(vbool8_t mask,vint64m8_t merge,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i64m8_mu(mask,merge,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmul_vx_mu-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmul_vx_mu-3.c new file mode 100644 index 00000000000..afff19695a3 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmul_vx_mu-3.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwmul_vx_i16mf4_mu(vbool64_t mask,vint16mf4_t merge,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i16mf4_mu(mask,merge,op1,op2,32); +} + + +vint16mf2_t test___riscv_vwmul_vx_i16mf2_mu(vbool32_t mask,vint16mf2_t merge,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i16mf2_mu(mask,merge,op1,op2,32); +} + + +vint16m1_t test___riscv_vwmul_vx_i16m1_mu(vbool16_t mask,vint16m1_t merge,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i16m1_mu(mask,merge,op1,op2,32); +} + + +vint16m2_t test___riscv_vwmul_vx_i16m2_mu(vbool8_t mask,vint16m2_t merge,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i16m2_mu(mask,merge,op1,op2,32); +} + + +vint16m4_t test___riscv_vwmul_vx_i16m4_mu(vbool4_t mask,vint16m4_t merge,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i16m4_mu(mask,merge,op1,op2,32); +} + + +vint16m8_t test___riscv_vwmul_vx_i16m8_mu(vbool2_t mask,vint16m8_t merge,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i16m8_mu(mask,merge,op1,op2,32); +} + + +vint32mf2_t test___riscv_vwmul_vx_i32mf2_mu(vbool64_t mask,vint32mf2_t merge,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i32mf2_mu(mask,merge,op1,op2,32); +} + + +vint32m1_t test___riscv_vwmul_vx_i32m1_mu(vbool32_t mask,vint32m1_t merge,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i32m1_mu(mask,merge,op1,op2,32); +} + + +vint32m2_t test___riscv_vwmul_vx_i32m2_mu(vbool16_t mask,vint32m2_t merge,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i32m2_mu(mask,merge,op1,op2,32); +} + + +vint32m4_t test___riscv_vwmul_vx_i32m4_mu(vbool8_t mask,vint32m4_t merge,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i32m4_mu(mask,merge,op1,op2,32); +} + + +vint32m8_t test___riscv_vwmul_vx_i32m8_mu(vbool4_t mask,vint32m8_t merge,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i32m8_mu(mask,merge,op1,op2,32); +} + + +vint64m1_t test___riscv_vwmul_vx_i64m1_mu(vbool64_t mask,vint64m1_t merge,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i64m1_mu(mask,merge,op1,op2,32); +} + + +vint64m2_t test___riscv_vwmul_vx_i64m2_mu(vbool32_t mask,vint64m2_t merge,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i64m2_mu(mask,merge,op1,op2,32); +} + + +vint64m4_t test___riscv_vwmul_vx_i64m4_mu(vbool16_t mask,vint64m4_t merge,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i64m4_mu(mask,merge,op1,op2,32); +} + + +vint64m8_t test___riscv_vwmul_vx_i64m8_mu(vbool8_t mask,vint64m8_t merge,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i64m8_mu(mask,merge,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmul_vx_tu-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmul_vx_tu-1.c new file mode 100644 index 00000000000..f503ab83cfa --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmul_vx_tu-1.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwmul_vx_i16mf4_tu(vint16mf4_t merge,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i16mf4_tu(merge,op1,op2,vl); +} + + +vint16mf2_t test___riscv_vwmul_vx_i16mf2_tu(vint16mf2_t merge,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i16mf2_tu(merge,op1,op2,vl); +} + + +vint16m1_t test___riscv_vwmul_vx_i16m1_tu(vint16m1_t merge,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i16m1_tu(merge,op1,op2,vl); +} + + +vint16m2_t test___riscv_vwmul_vx_i16m2_tu(vint16m2_t merge,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i16m2_tu(merge,op1,op2,vl); +} + + +vint16m4_t test___riscv_vwmul_vx_i16m4_tu(vint16m4_t merge,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i16m4_tu(merge,op1,op2,vl); +} + + +vint16m8_t test___riscv_vwmul_vx_i16m8_tu(vint16m8_t merge,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i16m8_tu(merge,op1,op2,vl); +} + + +vint32mf2_t test___riscv_vwmul_vx_i32mf2_tu(vint32mf2_t merge,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i32mf2_tu(merge,op1,op2,vl); +} + + +vint32m1_t test___riscv_vwmul_vx_i32m1_tu(vint32m1_t merge,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i32m1_tu(merge,op1,op2,vl); +} + + +vint32m2_t test___riscv_vwmul_vx_i32m2_tu(vint32m2_t merge,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i32m2_tu(merge,op1,op2,vl); +} + + +vint32m4_t test___riscv_vwmul_vx_i32m4_tu(vint32m4_t merge,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i32m4_tu(merge,op1,op2,vl); +} + + +vint32m8_t test___riscv_vwmul_vx_i32m8_tu(vint32m8_t merge,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i32m8_tu(merge,op1,op2,vl); +} + + +vint64m1_t test___riscv_vwmul_vx_i64m1_tu(vint64m1_t merge,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i64m1_tu(merge,op1,op2,vl); +} + + +vint64m2_t test___riscv_vwmul_vx_i64m2_tu(vint64m2_t merge,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i64m2_tu(merge,op1,op2,vl); +} + + +vint64m4_t test___riscv_vwmul_vx_i64m4_tu(vint64m4_t merge,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i64m4_tu(merge,op1,op2,vl); +} + + +vint64m8_t test___riscv_vwmul_vx_i64m8_tu(vint64m8_t merge,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i64m8_tu(merge,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmul_vx_tu-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmul_vx_tu-2.c new file mode 100644 index 00000000000..eb110342e82 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmul_vx_tu-2.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwmul_vx_i16mf4_tu(vint16mf4_t merge,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i16mf4_tu(merge,op1,op2,31); +} + + +vint16mf2_t test___riscv_vwmul_vx_i16mf2_tu(vint16mf2_t merge,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i16mf2_tu(merge,op1,op2,31); +} + + +vint16m1_t test___riscv_vwmul_vx_i16m1_tu(vint16m1_t merge,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i16m1_tu(merge,op1,op2,31); +} + + +vint16m2_t test___riscv_vwmul_vx_i16m2_tu(vint16m2_t merge,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i16m2_tu(merge,op1,op2,31); +} + + +vint16m4_t test___riscv_vwmul_vx_i16m4_tu(vint16m4_t merge,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i16m4_tu(merge,op1,op2,31); +} + + +vint16m8_t test___riscv_vwmul_vx_i16m8_tu(vint16m8_t merge,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i16m8_tu(merge,op1,op2,31); +} + + +vint32mf2_t test___riscv_vwmul_vx_i32mf2_tu(vint32mf2_t merge,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i32mf2_tu(merge,op1,op2,31); +} + + +vint32m1_t test___riscv_vwmul_vx_i32m1_tu(vint32m1_t merge,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i32m1_tu(merge,op1,op2,31); +} + + +vint32m2_t test___riscv_vwmul_vx_i32m2_tu(vint32m2_t merge,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i32m2_tu(merge,op1,op2,31); +} + + +vint32m4_t test___riscv_vwmul_vx_i32m4_tu(vint32m4_t merge,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i32m4_tu(merge,op1,op2,31); +} + + +vint32m8_t test___riscv_vwmul_vx_i32m8_tu(vint32m8_t merge,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i32m8_tu(merge,op1,op2,31); +} + + +vint64m1_t test___riscv_vwmul_vx_i64m1_tu(vint64m1_t merge,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i64m1_tu(merge,op1,op2,31); +} + + +vint64m2_t test___riscv_vwmul_vx_i64m2_tu(vint64m2_t merge,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i64m2_tu(merge,op1,op2,31); +} + + +vint64m4_t test___riscv_vwmul_vx_i64m4_tu(vint64m4_t merge,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i64m4_tu(merge,op1,op2,31); +} + + +vint64m8_t test___riscv_vwmul_vx_i64m8_tu(vint64m8_t merge,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i64m8_tu(merge,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmul_vx_tu-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmul_vx_tu-3.c new file mode 100644 index 00000000000..386b2e6667c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmul_vx_tu-3.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwmul_vx_i16mf4_tu(vint16mf4_t merge,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i16mf4_tu(merge,op1,op2,32); +} + + +vint16mf2_t test___riscv_vwmul_vx_i16mf2_tu(vint16mf2_t merge,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i16mf2_tu(merge,op1,op2,32); +} + + +vint16m1_t test___riscv_vwmul_vx_i16m1_tu(vint16m1_t merge,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i16m1_tu(merge,op1,op2,32); +} + + +vint16m2_t test___riscv_vwmul_vx_i16m2_tu(vint16m2_t merge,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i16m2_tu(merge,op1,op2,32); +} + + +vint16m4_t test___riscv_vwmul_vx_i16m4_tu(vint16m4_t merge,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i16m4_tu(merge,op1,op2,32); +} + + +vint16m8_t test___riscv_vwmul_vx_i16m8_tu(vint16m8_t merge,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i16m8_tu(merge,op1,op2,32); +} + + +vint32mf2_t test___riscv_vwmul_vx_i32mf2_tu(vint32mf2_t merge,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i32mf2_tu(merge,op1,op2,32); +} + + +vint32m1_t test___riscv_vwmul_vx_i32m1_tu(vint32m1_t merge,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i32m1_tu(merge,op1,op2,32); +} + + +vint32m2_t test___riscv_vwmul_vx_i32m2_tu(vint32m2_t merge,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i32m2_tu(merge,op1,op2,32); +} + + +vint32m4_t test___riscv_vwmul_vx_i32m4_tu(vint32m4_t merge,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i32m4_tu(merge,op1,op2,32); +} + + +vint32m8_t test___riscv_vwmul_vx_i32m8_tu(vint32m8_t merge,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i32m8_tu(merge,op1,op2,32); +} + + +vint64m1_t test___riscv_vwmul_vx_i64m1_tu(vint64m1_t merge,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i64m1_tu(merge,op1,op2,32); +} + + +vint64m2_t test___riscv_vwmul_vx_i64m2_tu(vint64m2_t merge,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i64m2_tu(merge,op1,op2,32); +} + + +vint64m4_t test___riscv_vwmul_vx_i64m4_tu(vint64m4_t merge,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i64m4_tu(merge,op1,op2,32); +} + + +vint64m8_t test___riscv_vwmul_vx_i64m8_tu(vint64m8_t merge,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i64m8_tu(merge,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmul_vx_tum-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmul_vx_tum-1.c new file mode 100644 index 00000000000..373702b0632 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmul_vx_tum-1.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwmul_vx_i16mf4_tum(vbool64_t mask,vint16mf4_t merge,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i16mf4_tum(mask,merge,op1,op2,vl); +} + + +vint16mf2_t test___riscv_vwmul_vx_i16mf2_tum(vbool32_t mask,vint16mf2_t merge,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i16mf2_tum(mask,merge,op1,op2,vl); +} + + +vint16m1_t test___riscv_vwmul_vx_i16m1_tum(vbool16_t mask,vint16m1_t merge,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i16m1_tum(mask,merge,op1,op2,vl); +} + + +vint16m2_t test___riscv_vwmul_vx_i16m2_tum(vbool8_t mask,vint16m2_t merge,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i16m2_tum(mask,merge,op1,op2,vl); +} + + +vint16m4_t test___riscv_vwmul_vx_i16m4_tum(vbool4_t mask,vint16m4_t merge,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i16m4_tum(mask,merge,op1,op2,vl); +} + + +vint16m8_t test___riscv_vwmul_vx_i16m8_tum(vbool2_t mask,vint16m8_t merge,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i16m8_tum(mask,merge,op1,op2,vl); +} + + +vint32mf2_t test___riscv_vwmul_vx_i32mf2_tum(vbool64_t mask,vint32mf2_t merge,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i32mf2_tum(mask,merge,op1,op2,vl); +} + + +vint32m1_t test___riscv_vwmul_vx_i32m1_tum(vbool32_t mask,vint32m1_t merge,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i32m1_tum(mask,merge,op1,op2,vl); +} + + +vint32m2_t test___riscv_vwmul_vx_i32m2_tum(vbool16_t mask,vint32m2_t merge,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i32m2_tum(mask,merge,op1,op2,vl); +} + + +vint32m4_t test___riscv_vwmul_vx_i32m4_tum(vbool8_t mask,vint32m4_t merge,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i32m4_tum(mask,merge,op1,op2,vl); +} + + +vint32m8_t test___riscv_vwmul_vx_i32m8_tum(vbool4_t mask,vint32m8_t merge,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i32m8_tum(mask,merge,op1,op2,vl); +} + + +vint64m1_t test___riscv_vwmul_vx_i64m1_tum(vbool64_t mask,vint64m1_t merge,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i64m1_tum(mask,merge,op1,op2,vl); +} + + +vint64m2_t test___riscv_vwmul_vx_i64m2_tum(vbool32_t mask,vint64m2_t merge,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i64m2_tum(mask,merge,op1,op2,vl); +} + + +vint64m4_t test___riscv_vwmul_vx_i64m4_tum(vbool16_t mask,vint64m4_t merge,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i64m4_tum(mask,merge,op1,op2,vl); +} + + +vint64m8_t test___riscv_vwmul_vx_i64m8_tum(vbool8_t mask,vint64m8_t merge,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i64m8_tum(mask,merge,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmul_vx_tum-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmul_vx_tum-2.c new file mode 100644 index 00000000000..4d5b10fbf6a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmul_vx_tum-2.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwmul_vx_i16mf4_tum(vbool64_t mask,vint16mf4_t merge,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i16mf4_tum(mask,merge,op1,op2,31); +} + + +vint16mf2_t test___riscv_vwmul_vx_i16mf2_tum(vbool32_t mask,vint16mf2_t merge,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i16mf2_tum(mask,merge,op1,op2,31); +} + + +vint16m1_t test___riscv_vwmul_vx_i16m1_tum(vbool16_t mask,vint16m1_t merge,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i16m1_tum(mask,merge,op1,op2,31); +} + + +vint16m2_t test___riscv_vwmul_vx_i16m2_tum(vbool8_t mask,vint16m2_t merge,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i16m2_tum(mask,merge,op1,op2,31); +} + + +vint16m4_t test___riscv_vwmul_vx_i16m4_tum(vbool4_t mask,vint16m4_t merge,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i16m4_tum(mask,merge,op1,op2,31); +} + + +vint16m8_t test___riscv_vwmul_vx_i16m8_tum(vbool2_t mask,vint16m8_t merge,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i16m8_tum(mask,merge,op1,op2,31); +} + + +vint32mf2_t test___riscv_vwmul_vx_i32mf2_tum(vbool64_t mask,vint32mf2_t merge,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i32mf2_tum(mask,merge,op1,op2,31); +} + + +vint32m1_t test___riscv_vwmul_vx_i32m1_tum(vbool32_t mask,vint32m1_t merge,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i32m1_tum(mask,merge,op1,op2,31); +} + + +vint32m2_t test___riscv_vwmul_vx_i32m2_tum(vbool16_t mask,vint32m2_t merge,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i32m2_tum(mask,merge,op1,op2,31); +} + + +vint32m4_t test___riscv_vwmul_vx_i32m4_tum(vbool8_t mask,vint32m4_t merge,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i32m4_tum(mask,merge,op1,op2,31); +} + + +vint32m8_t test___riscv_vwmul_vx_i32m8_tum(vbool4_t mask,vint32m8_t merge,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i32m8_tum(mask,merge,op1,op2,31); +} + + +vint64m1_t test___riscv_vwmul_vx_i64m1_tum(vbool64_t mask,vint64m1_t merge,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i64m1_tum(mask,merge,op1,op2,31); +} + + +vint64m2_t test___riscv_vwmul_vx_i64m2_tum(vbool32_t mask,vint64m2_t merge,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i64m2_tum(mask,merge,op1,op2,31); +} + + +vint64m4_t test___riscv_vwmul_vx_i64m4_tum(vbool16_t mask,vint64m4_t merge,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i64m4_tum(mask,merge,op1,op2,31); +} + + +vint64m8_t test___riscv_vwmul_vx_i64m8_tum(vbool8_t mask,vint64m8_t merge,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i64m8_tum(mask,merge,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmul_vx_tum-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmul_vx_tum-3.c new file mode 100644 index 00000000000..5ea4ec60cf2 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmul_vx_tum-3.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwmul_vx_i16mf4_tum(vbool64_t mask,vint16mf4_t merge,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i16mf4_tum(mask,merge,op1,op2,32); +} + + +vint16mf2_t test___riscv_vwmul_vx_i16mf2_tum(vbool32_t mask,vint16mf2_t merge,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i16mf2_tum(mask,merge,op1,op2,32); +} + + +vint16m1_t test___riscv_vwmul_vx_i16m1_tum(vbool16_t mask,vint16m1_t merge,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i16m1_tum(mask,merge,op1,op2,32); +} + + +vint16m2_t test___riscv_vwmul_vx_i16m2_tum(vbool8_t mask,vint16m2_t merge,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i16m2_tum(mask,merge,op1,op2,32); +} + + +vint16m4_t test___riscv_vwmul_vx_i16m4_tum(vbool4_t mask,vint16m4_t merge,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i16m4_tum(mask,merge,op1,op2,32); +} + + +vint16m8_t test___riscv_vwmul_vx_i16m8_tum(vbool2_t mask,vint16m8_t merge,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i16m8_tum(mask,merge,op1,op2,32); +} + + +vint32mf2_t test___riscv_vwmul_vx_i32mf2_tum(vbool64_t mask,vint32mf2_t merge,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i32mf2_tum(mask,merge,op1,op2,32); +} + + +vint32m1_t test___riscv_vwmul_vx_i32m1_tum(vbool32_t mask,vint32m1_t merge,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i32m1_tum(mask,merge,op1,op2,32); +} + + +vint32m2_t test___riscv_vwmul_vx_i32m2_tum(vbool16_t mask,vint32m2_t merge,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i32m2_tum(mask,merge,op1,op2,32); +} + + +vint32m4_t test___riscv_vwmul_vx_i32m4_tum(vbool8_t mask,vint32m4_t merge,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i32m4_tum(mask,merge,op1,op2,32); +} + + +vint32m8_t test___riscv_vwmul_vx_i32m8_tum(vbool4_t mask,vint32m8_t merge,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i32m8_tum(mask,merge,op1,op2,32); +} + + +vint64m1_t test___riscv_vwmul_vx_i64m1_tum(vbool64_t mask,vint64m1_t merge,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i64m1_tum(mask,merge,op1,op2,32); +} + + +vint64m2_t test___riscv_vwmul_vx_i64m2_tum(vbool32_t mask,vint64m2_t merge,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i64m2_tum(mask,merge,op1,op2,32); +} + + +vint64m4_t test___riscv_vwmul_vx_i64m4_tum(vbool16_t mask,vint64m4_t merge,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i64m4_tum(mask,merge,op1,op2,32); +} + + +vint64m8_t test___riscv_vwmul_vx_i64m8_tum(vbool8_t mask,vint64m8_t merge,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i64m8_tum(mask,merge,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmul_vx_tumu-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmul_vx_tumu-1.c new file mode 100644 index 00000000000..745000c6385 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmul_vx_tumu-1.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwmul_vx_i16mf4_tumu(vbool64_t mask,vint16mf4_t merge,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i16mf4_tumu(mask,merge,op1,op2,vl); +} + + +vint16mf2_t test___riscv_vwmul_vx_i16mf2_tumu(vbool32_t mask,vint16mf2_t merge,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i16mf2_tumu(mask,merge,op1,op2,vl); +} + + +vint16m1_t test___riscv_vwmul_vx_i16m1_tumu(vbool16_t mask,vint16m1_t merge,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i16m1_tumu(mask,merge,op1,op2,vl); +} + + +vint16m2_t test___riscv_vwmul_vx_i16m2_tumu(vbool8_t mask,vint16m2_t merge,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i16m2_tumu(mask,merge,op1,op2,vl); +} + + +vint16m4_t test___riscv_vwmul_vx_i16m4_tumu(vbool4_t mask,vint16m4_t merge,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i16m4_tumu(mask,merge,op1,op2,vl); +} + + +vint16m8_t test___riscv_vwmul_vx_i16m8_tumu(vbool2_t mask,vint16m8_t merge,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i16m8_tumu(mask,merge,op1,op2,vl); +} + + +vint32mf2_t test___riscv_vwmul_vx_i32mf2_tumu(vbool64_t mask,vint32mf2_t merge,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i32mf2_tumu(mask,merge,op1,op2,vl); +} + + +vint32m1_t test___riscv_vwmul_vx_i32m1_tumu(vbool32_t mask,vint32m1_t merge,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i32m1_tumu(mask,merge,op1,op2,vl); +} + + +vint32m2_t test___riscv_vwmul_vx_i32m2_tumu(vbool16_t mask,vint32m2_t merge,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i32m2_tumu(mask,merge,op1,op2,vl); +} + + +vint32m4_t test___riscv_vwmul_vx_i32m4_tumu(vbool8_t mask,vint32m4_t merge,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i32m4_tumu(mask,merge,op1,op2,vl); +} + + +vint32m8_t test___riscv_vwmul_vx_i32m8_tumu(vbool4_t mask,vint32m8_t merge,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i32m8_tumu(mask,merge,op1,op2,vl); +} + + +vint64m1_t test___riscv_vwmul_vx_i64m1_tumu(vbool64_t mask,vint64m1_t merge,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i64m1_tumu(mask,merge,op1,op2,vl); +} + + +vint64m2_t test___riscv_vwmul_vx_i64m2_tumu(vbool32_t mask,vint64m2_t merge,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i64m2_tumu(mask,merge,op1,op2,vl); +} + + +vint64m4_t test___riscv_vwmul_vx_i64m4_tumu(vbool16_t mask,vint64m4_t merge,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i64m4_tumu(mask,merge,op1,op2,vl); +} + + +vint64m8_t test___riscv_vwmul_vx_i64m8_tumu(vbool8_t mask,vint64m8_t merge,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i64m8_tumu(mask,merge,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmul_vx_tumu-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmul_vx_tumu-2.c new file mode 100644 index 00000000000..a40ef991c22 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmul_vx_tumu-2.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwmul_vx_i16mf4_tumu(vbool64_t mask,vint16mf4_t merge,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i16mf4_tumu(mask,merge,op1,op2,31); +} + + +vint16mf2_t test___riscv_vwmul_vx_i16mf2_tumu(vbool32_t mask,vint16mf2_t merge,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i16mf2_tumu(mask,merge,op1,op2,31); +} + + +vint16m1_t test___riscv_vwmul_vx_i16m1_tumu(vbool16_t mask,vint16m1_t merge,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i16m1_tumu(mask,merge,op1,op2,31); +} + + +vint16m2_t test___riscv_vwmul_vx_i16m2_tumu(vbool8_t mask,vint16m2_t merge,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i16m2_tumu(mask,merge,op1,op2,31); +} + + +vint16m4_t test___riscv_vwmul_vx_i16m4_tumu(vbool4_t mask,vint16m4_t merge,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i16m4_tumu(mask,merge,op1,op2,31); +} + + +vint16m8_t test___riscv_vwmul_vx_i16m8_tumu(vbool2_t mask,vint16m8_t merge,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i16m8_tumu(mask,merge,op1,op2,31); +} + + +vint32mf2_t test___riscv_vwmul_vx_i32mf2_tumu(vbool64_t mask,vint32mf2_t merge,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i32mf2_tumu(mask,merge,op1,op2,31); +} + + +vint32m1_t test___riscv_vwmul_vx_i32m1_tumu(vbool32_t mask,vint32m1_t merge,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i32m1_tumu(mask,merge,op1,op2,31); +} + + +vint32m2_t test___riscv_vwmul_vx_i32m2_tumu(vbool16_t mask,vint32m2_t merge,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i32m2_tumu(mask,merge,op1,op2,31); +} + + +vint32m4_t test___riscv_vwmul_vx_i32m4_tumu(vbool8_t mask,vint32m4_t merge,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i32m4_tumu(mask,merge,op1,op2,31); +} + + +vint32m8_t test___riscv_vwmul_vx_i32m8_tumu(vbool4_t mask,vint32m8_t merge,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i32m8_tumu(mask,merge,op1,op2,31); +} + + +vint64m1_t test___riscv_vwmul_vx_i64m1_tumu(vbool64_t mask,vint64m1_t merge,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i64m1_tumu(mask,merge,op1,op2,31); +} + + +vint64m2_t test___riscv_vwmul_vx_i64m2_tumu(vbool32_t mask,vint64m2_t merge,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i64m2_tumu(mask,merge,op1,op2,31); +} + + +vint64m4_t test___riscv_vwmul_vx_i64m4_tumu(vbool16_t mask,vint64m4_t merge,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i64m4_tumu(mask,merge,op1,op2,31); +} + + +vint64m8_t test___riscv_vwmul_vx_i64m8_tumu(vbool8_t mask,vint64m8_t merge,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i64m8_tumu(mask,merge,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmul_vx_tumu-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmul_vx_tumu-3.c new file mode 100644 index 00000000000..a440f17aeaa --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmul_vx_tumu-3.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwmul_vx_i16mf4_tumu(vbool64_t mask,vint16mf4_t merge,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i16mf4_tumu(mask,merge,op1,op2,32); +} + + +vint16mf2_t test___riscv_vwmul_vx_i16mf2_tumu(vbool32_t mask,vint16mf2_t merge,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i16mf2_tumu(mask,merge,op1,op2,32); +} + + +vint16m1_t test___riscv_vwmul_vx_i16m1_tumu(vbool16_t mask,vint16m1_t merge,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i16m1_tumu(mask,merge,op1,op2,32); +} + + +vint16m2_t test___riscv_vwmul_vx_i16m2_tumu(vbool8_t mask,vint16m2_t merge,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i16m2_tumu(mask,merge,op1,op2,32); +} + + +vint16m4_t test___riscv_vwmul_vx_i16m4_tumu(vbool4_t mask,vint16m4_t merge,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i16m4_tumu(mask,merge,op1,op2,32); +} + + +vint16m8_t test___riscv_vwmul_vx_i16m8_tumu(vbool2_t mask,vint16m8_t merge,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i16m8_tumu(mask,merge,op1,op2,32); +} + + +vint32mf2_t test___riscv_vwmul_vx_i32mf2_tumu(vbool64_t mask,vint32mf2_t merge,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i32mf2_tumu(mask,merge,op1,op2,32); +} + + +vint32m1_t test___riscv_vwmul_vx_i32m1_tumu(vbool32_t mask,vint32m1_t merge,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i32m1_tumu(mask,merge,op1,op2,32); +} + + +vint32m2_t test___riscv_vwmul_vx_i32m2_tumu(vbool16_t mask,vint32m2_t merge,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i32m2_tumu(mask,merge,op1,op2,32); +} + + +vint32m4_t test___riscv_vwmul_vx_i32m4_tumu(vbool8_t mask,vint32m4_t merge,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i32m4_tumu(mask,merge,op1,op2,32); +} + + +vint32m8_t test___riscv_vwmul_vx_i32m8_tumu(vbool4_t mask,vint32m8_t merge,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i32m8_tumu(mask,merge,op1,op2,32); +} + + +vint64m1_t test___riscv_vwmul_vx_i64m1_tumu(vbool64_t mask,vint64m1_t merge,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i64m1_tumu(mask,merge,op1,op2,32); +} + + +vint64m2_t test___riscv_vwmul_vx_i64m2_tumu(vbool32_t mask,vint64m2_t merge,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i64m2_tumu(mask,merge,op1,op2,32); +} + + +vint64m4_t test___riscv_vwmul_vx_i64m4_tumu(vbool16_t mask,vint64m4_t merge,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i64m4_tumu(mask,merge,op1,op2,32); +} + + +vint64m8_t test___riscv_vwmul_vx_i64m8_tumu(vbool8_t mask,vint64m8_t merge,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwmul_vx_i64m8_tumu(mask,merge,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */