diff mbox series

RISC-V: Add vwsub.wv C API tests

Message ID 20230207062554.36985-1-juzhe.zhong@rivai.ai
State Committed
Commit 14ac33c8e03cd9b1006a2fbb04ec47d32f50b742
Headers
Series RISC-V: Add vwsub.wv C API tests |

Commit Message

钟居哲 Feb. 7, 2023, 6:25 a.m. UTC 
  From: Ju-Zhe Zhong <juzhe.zhong@rivai.ai>

gcc/testsuite/ChangeLog:

        * gcc.target/riscv/rvv/base/vwsub_wv-1.c: New test.
        * gcc.target/riscv/rvv/base/vwsub_wv-2.c: New test.
        * gcc.target/riscv/rvv/base/vwsub_wv-3.c: New test.
        * gcc.target/riscv/rvv/base/vwsub_wv_m-1.c: New test.
        * gcc.target/riscv/rvv/base/vwsub_wv_m-2.c: New test.
        * gcc.target/riscv/rvv/base/vwsub_wv_m-3.c: New test.
        * gcc.target/riscv/rvv/base/vwsub_wv_mu-1.c: New test.
        * gcc.target/riscv/rvv/base/vwsub_wv_mu-2.c: New test.
        * gcc.target/riscv/rvv/base/vwsub_wv_mu-3.c: New test.
        * gcc.target/riscv/rvv/base/vwsub_wv_tu-1.c: New test.
        * gcc.target/riscv/rvv/base/vwsub_wv_tu-2.c: New test.
        * gcc.target/riscv/rvv/base/vwsub_wv_tu-3.c: New test.
        * gcc.target/riscv/rvv/base/vwsub_wv_tum-1.c: New test.
        * gcc.target/riscv/rvv/base/vwsub_wv_tum-2.c: New test.
        * gcc.target/riscv/rvv/base/vwsub_wv_tum-3.c: New test.
        * gcc.target/riscv/rvv/base/vwsub_wv_tumu-1.c: New test.
        * gcc.target/riscv/rvv/base/vwsub_wv_tumu-2.c: New test.
        * gcc.target/riscv/rvv/base/vwsub_wv_tumu-3.c: New test.


---
 .../gcc.target/riscv/rvv/base/vwsub_wv-1.c    | 111 ++++++++++++++++++
 .../gcc.target/riscv/rvv/base/vwsub_wv-2.c    | 111 ++++++++++++++++++
 .../gcc.target/riscv/rvv/base/vwsub_wv-3.c    | 111 ++++++++++++++++++
 .../gcc.target/riscv/rvv/base/vwsub_wv_m-1.c  | 111 ++++++++++++++++++
 .../gcc.target/riscv/rvv/base/vwsub_wv_m-2.c  | 111 ++++++++++++++++++
 .../gcc.target/riscv/rvv/base/vwsub_wv_m-3.c  | 111 ++++++++++++++++++
 .../gcc.target/riscv/rvv/base/vwsub_wv_mu-1.c | 111 ++++++++++++++++++
 .../gcc.target/riscv/rvv/base/vwsub_wv_mu-2.c | 111 ++++++++++++++++++
 .../gcc.target/riscv/rvv/base/vwsub_wv_mu-3.c | 111 ++++++++++++++++++
 .../gcc.target/riscv/rvv/base/vwsub_wv_tu-1.c | 111 ++++++++++++++++++
 .../gcc.target/riscv/rvv/base/vwsub_wv_tu-2.c | 111 ++++++++++++++++++
 .../gcc.target/riscv/rvv/base/vwsub_wv_tu-3.c | 111 ++++++++++++++++++
 .../riscv/rvv/base/vwsub_wv_tum-1.c           | 111 ++++++++++++++++++
 .../riscv/rvv/base/vwsub_wv_tum-2.c           | 111 ++++++++++++++++++
 .../riscv/rvv/base/vwsub_wv_tum-3.c           | 111 ++++++++++++++++++
 .../riscv/rvv/base/vwsub_wv_tumu-1.c          | 111 ++++++++++++++++++
 .../riscv/rvv/base/vwsub_wv_tumu-2.c          | 111 ++++++++++++++++++
 .../riscv/rvv/base/vwsub_wv_tumu-3.c          | 111 ++++++++++++++++++
 18 files changed, 1998 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsub_wv-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsub_wv-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsub_wv-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsub_wv_m-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsub_wv_m-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsub_wv_m-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsub_wv_mu-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsub_wv_mu-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsub_wv_mu-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsub_wv_tu-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsub_wv_tu-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsub_wv_tu-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsub_wv_tum-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsub_wv_tum-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsub_wv_tum-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsub_wv_tumu-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsub_wv_tumu-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsub_wv_tumu-3.c
diff mbox series

Patch

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwsub_wv-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwsub_wv-1.c
new file mode 100644
index 00000000000..31bbaf4bcc8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwsub_wv-1.c
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwsub_wv_i16mf4(vint16mf4_t op1,vint8mf8_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i16mf4(op1,op2,vl);
+}
+
+
+vint16mf2_t test___riscv_vwsub_wv_i16mf2(vint16mf2_t op1,vint8mf4_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i16mf2(op1,op2,vl);
+}
+
+
+vint16m1_t test___riscv_vwsub_wv_i16m1(vint16m1_t op1,vint8mf2_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i16m1(op1,op2,vl);
+}
+
+
+vint16m2_t test___riscv_vwsub_wv_i16m2(vint16m2_t op1,vint8m1_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i16m2(op1,op2,vl);
+}
+
+
+vint16m4_t test___riscv_vwsub_wv_i16m4(vint16m4_t op1,vint8m2_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i16m4(op1,op2,vl);
+}
+
+
+vint16m8_t test___riscv_vwsub_wv_i16m8(vint16m8_t op1,vint8m4_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i16m8(op1,op2,vl);
+}
+
+
+vint32mf2_t test___riscv_vwsub_wv_i32mf2(vint32mf2_t op1,vint16mf4_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i32mf2(op1,op2,vl);
+}
+
+
+vint32m1_t test___riscv_vwsub_wv_i32m1(vint32m1_t op1,vint16mf2_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i32m1(op1,op2,vl);
+}
+
+
+vint32m2_t test___riscv_vwsub_wv_i32m2(vint32m2_t op1,vint16m1_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i32m2(op1,op2,vl);
+}
+
+
+vint32m4_t test___riscv_vwsub_wv_i32m4(vint32m4_t op1,vint16m2_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i32m4(op1,op2,vl);
+}
+
+
+vint32m8_t test___riscv_vwsub_wv_i32m8(vint32m8_t op1,vint16m4_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i32m8(op1,op2,vl);
+}
+
+
+vint64m1_t test___riscv_vwsub_wv_i64m1(vint64m1_t op1,vint32mf2_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i64m1(op1,op2,vl);
+}
+
+
+vint64m2_t test___riscv_vwsub_wv_i64m2(vint64m2_t op1,vint32m1_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i64m2(op1,op2,vl);
+}
+
+
+vint64m4_t test___riscv_vwsub_wv_i64m4(vint64m4_t op1,vint32m2_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i64m4(op1,op2,vl);
+}
+
+
+vint64m8_t test___riscv_vwsub_wv_i64m8(vint64m8_t op1,vint32m4_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i64m8(op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwsub_wv-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwsub_wv-2.c
new file mode 100644
index 00000000000..2a598558572
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwsub_wv-2.c
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwsub_wv_i16mf4(vint16mf4_t op1,vint8mf8_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i16mf4(op1,op2,31);
+}
+
+
+vint16mf2_t test___riscv_vwsub_wv_i16mf2(vint16mf2_t op1,vint8mf4_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i16mf2(op1,op2,31);
+}
+
+
+vint16m1_t test___riscv_vwsub_wv_i16m1(vint16m1_t op1,vint8mf2_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i16m1(op1,op2,31);
+}
+
+
+vint16m2_t test___riscv_vwsub_wv_i16m2(vint16m2_t op1,vint8m1_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i16m2(op1,op2,31);
+}
+
+
+vint16m4_t test___riscv_vwsub_wv_i16m4(vint16m4_t op1,vint8m2_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i16m4(op1,op2,31);
+}
+
+
+vint16m8_t test___riscv_vwsub_wv_i16m8(vint16m8_t op1,vint8m4_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i16m8(op1,op2,31);
+}
+
+
+vint32mf2_t test___riscv_vwsub_wv_i32mf2(vint32mf2_t op1,vint16mf4_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i32mf2(op1,op2,31);
+}
+
+
+vint32m1_t test___riscv_vwsub_wv_i32m1(vint32m1_t op1,vint16mf2_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i32m1(op1,op2,31);
+}
+
+
+vint32m2_t test___riscv_vwsub_wv_i32m2(vint32m2_t op1,vint16m1_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i32m2(op1,op2,31);
+}
+
+
+vint32m4_t test___riscv_vwsub_wv_i32m4(vint32m4_t op1,vint16m2_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i32m4(op1,op2,31);
+}
+
+
+vint32m8_t test___riscv_vwsub_wv_i32m8(vint32m8_t op1,vint16m4_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i32m8(op1,op2,31);
+}
+
+
+vint64m1_t test___riscv_vwsub_wv_i64m1(vint64m1_t op1,vint32mf2_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i64m1(op1,op2,31);
+}
+
+
+vint64m2_t test___riscv_vwsub_wv_i64m2(vint64m2_t op1,vint32m1_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i64m2(op1,op2,31);
+}
+
+
+vint64m4_t test___riscv_vwsub_wv_i64m4(vint64m4_t op1,vint32m2_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i64m4(op1,op2,31);
+}
+
+
+vint64m8_t test___riscv_vwsub_wv_i64m8(vint64m8_t op1,vint32m4_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i64m8(op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwsub_wv-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwsub_wv-3.c
new file mode 100644
index 00000000000..2a63a084a7c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwsub_wv-3.c
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwsub_wv_i16mf4(vint16mf4_t op1,vint8mf8_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i16mf4(op1,op2,32);
+}
+
+
+vint16mf2_t test___riscv_vwsub_wv_i16mf2(vint16mf2_t op1,vint8mf4_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i16mf2(op1,op2,32);
+}
+
+
+vint16m1_t test___riscv_vwsub_wv_i16m1(vint16m1_t op1,vint8mf2_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i16m1(op1,op2,32);
+}
+
+
+vint16m2_t test___riscv_vwsub_wv_i16m2(vint16m2_t op1,vint8m1_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i16m2(op1,op2,32);
+}
+
+
+vint16m4_t test___riscv_vwsub_wv_i16m4(vint16m4_t op1,vint8m2_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i16m4(op1,op2,32);
+}
+
+
+vint16m8_t test___riscv_vwsub_wv_i16m8(vint16m8_t op1,vint8m4_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i16m8(op1,op2,32);
+}
+
+
+vint32mf2_t test___riscv_vwsub_wv_i32mf2(vint32mf2_t op1,vint16mf4_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i32mf2(op1,op2,32);
+}
+
+
+vint32m1_t test___riscv_vwsub_wv_i32m1(vint32m1_t op1,vint16mf2_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i32m1(op1,op2,32);
+}
+
+
+vint32m2_t test___riscv_vwsub_wv_i32m2(vint32m2_t op1,vint16m1_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i32m2(op1,op2,32);
+}
+
+
+vint32m4_t test___riscv_vwsub_wv_i32m4(vint32m4_t op1,vint16m2_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i32m4(op1,op2,32);
+}
+
+
+vint32m8_t test___riscv_vwsub_wv_i32m8(vint32m8_t op1,vint16m4_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i32m8(op1,op2,32);
+}
+
+
+vint64m1_t test___riscv_vwsub_wv_i64m1(vint64m1_t op1,vint32mf2_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i64m1(op1,op2,32);
+}
+
+
+vint64m2_t test___riscv_vwsub_wv_i64m2(vint64m2_t op1,vint32m1_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i64m2(op1,op2,32);
+}
+
+
+vint64m4_t test___riscv_vwsub_wv_i64m4(vint64m4_t op1,vint32m2_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i64m4(op1,op2,32);
+}
+
+
+vint64m8_t test___riscv_vwsub_wv_i64m8(vint64m8_t op1,vint32m4_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i64m8(op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwsub_wv_m-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwsub_wv_m-1.c
new file mode 100644
index 00000000000..61b156c9bf0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwsub_wv_m-1.c
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwsub_wv_i16mf4_m(vbool64_t mask,vint16mf4_t op1,vint8mf8_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i16mf4_m(mask,op1,op2,vl);
+}
+
+
+vint16mf2_t test___riscv_vwsub_wv_i16mf2_m(vbool32_t mask,vint16mf2_t op1,vint8mf4_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i16mf2_m(mask,op1,op2,vl);
+}
+
+
+vint16m1_t test___riscv_vwsub_wv_i16m1_m(vbool16_t mask,vint16m1_t op1,vint8mf2_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i16m1_m(mask,op1,op2,vl);
+}
+
+
+vint16m2_t test___riscv_vwsub_wv_i16m2_m(vbool8_t mask,vint16m2_t op1,vint8m1_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i16m2_m(mask,op1,op2,vl);
+}
+
+
+vint16m4_t test___riscv_vwsub_wv_i16m4_m(vbool4_t mask,vint16m4_t op1,vint8m2_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i16m4_m(mask,op1,op2,vl);
+}
+
+
+vint16m8_t test___riscv_vwsub_wv_i16m8_m(vbool2_t mask,vint16m8_t op1,vint8m4_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i16m8_m(mask,op1,op2,vl);
+}
+
+
+vint32mf2_t test___riscv_vwsub_wv_i32mf2_m(vbool64_t mask,vint32mf2_t op1,vint16mf4_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i32mf2_m(mask,op1,op2,vl);
+}
+
+
+vint32m1_t test___riscv_vwsub_wv_i32m1_m(vbool32_t mask,vint32m1_t op1,vint16mf2_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i32m1_m(mask,op1,op2,vl);
+}
+
+
+vint32m2_t test___riscv_vwsub_wv_i32m2_m(vbool16_t mask,vint32m2_t op1,vint16m1_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i32m2_m(mask,op1,op2,vl);
+}
+
+
+vint32m4_t test___riscv_vwsub_wv_i32m4_m(vbool8_t mask,vint32m4_t op1,vint16m2_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i32m4_m(mask,op1,op2,vl);
+}
+
+
+vint32m8_t test___riscv_vwsub_wv_i32m8_m(vbool4_t mask,vint32m8_t op1,vint16m4_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i32m8_m(mask,op1,op2,vl);
+}
+
+
+vint64m1_t test___riscv_vwsub_wv_i64m1_m(vbool64_t mask,vint64m1_t op1,vint32mf2_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i64m1_m(mask,op1,op2,vl);
+}
+
+
+vint64m2_t test___riscv_vwsub_wv_i64m2_m(vbool32_t mask,vint64m2_t op1,vint32m1_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i64m2_m(mask,op1,op2,vl);
+}
+
+
+vint64m4_t test___riscv_vwsub_wv_i64m4_m(vbool16_t mask,vint64m4_t op1,vint32m2_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i64m4_m(mask,op1,op2,vl);
+}
+
+
+vint64m8_t test___riscv_vwsub_wv_i64m8_m(vbool8_t mask,vint64m8_t op1,vint32m4_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i64m8_m(mask,op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwsub_wv_m-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwsub_wv_m-2.c
new file mode 100644
index 00000000000..0545e101c23
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwsub_wv_m-2.c
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwsub_wv_i16mf4_m(vbool64_t mask,vint16mf4_t op1,vint8mf8_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i16mf4_m(mask,op1,op2,31);
+}
+
+
+vint16mf2_t test___riscv_vwsub_wv_i16mf2_m(vbool32_t mask,vint16mf2_t op1,vint8mf4_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i16mf2_m(mask,op1,op2,31);
+}
+
+
+vint16m1_t test___riscv_vwsub_wv_i16m1_m(vbool16_t mask,vint16m1_t op1,vint8mf2_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i16m1_m(mask,op1,op2,31);
+}
+
+
+vint16m2_t test___riscv_vwsub_wv_i16m2_m(vbool8_t mask,vint16m2_t op1,vint8m1_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i16m2_m(mask,op1,op2,31);
+}
+
+
+vint16m4_t test___riscv_vwsub_wv_i16m4_m(vbool4_t mask,vint16m4_t op1,vint8m2_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i16m4_m(mask,op1,op2,31);
+}
+
+
+vint16m8_t test___riscv_vwsub_wv_i16m8_m(vbool2_t mask,vint16m8_t op1,vint8m4_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i16m8_m(mask,op1,op2,31);
+}
+
+
+vint32mf2_t test___riscv_vwsub_wv_i32mf2_m(vbool64_t mask,vint32mf2_t op1,vint16mf4_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i32mf2_m(mask,op1,op2,31);
+}
+
+
+vint32m1_t test___riscv_vwsub_wv_i32m1_m(vbool32_t mask,vint32m1_t op1,vint16mf2_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i32m1_m(mask,op1,op2,31);
+}
+
+
+vint32m2_t test___riscv_vwsub_wv_i32m2_m(vbool16_t mask,vint32m2_t op1,vint16m1_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i32m2_m(mask,op1,op2,31);
+}
+
+
+vint32m4_t test___riscv_vwsub_wv_i32m4_m(vbool8_t mask,vint32m4_t op1,vint16m2_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i32m4_m(mask,op1,op2,31);
+}
+
+
+vint32m8_t test___riscv_vwsub_wv_i32m8_m(vbool4_t mask,vint32m8_t op1,vint16m4_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i32m8_m(mask,op1,op2,31);
+}
+
+
+vint64m1_t test___riscv_vwsub_wv_i64m1_m(vbool64_t mask,vint64m1_t op1,vint32mf2_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i64m1_m(mask,op1,op2,31);
+}
+
+
+vint64m2_t test___riscv_vwsub_wv_i64m2_m(vbool32_t mask,vint64m2_t op1,vint32m1_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i64m2_m(mask,op1,op2,31);
+}
+
+
+vint64m4_t test___riscv_vwsub_wv_i64m4_m(vbool16_t mask,vint64m4_t op1,vint32m2_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i64m4_m(mask,op1,op2,31);
+}
+
+
+vint64m8_t test___riscv_vwsub_wv_i64m8_m(vbool8_t mask,vint64m8_t op1,vint32m4_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i64m8_m(mask,op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwsub_wv_m-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwsub_wv_m-3.c
new file mode 100644
index 00000000000..5ecfe92db19
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwsub_wv_m-3.c
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwsub_wv_i16mf4_m(vbool64_t mask,vint16mf4_t op1,vint8mf8_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i16mf4_m(mask,op1,op2,32);
+}
+
+
+vint16mf2_t test___riscv_vwsub_wv_i16mf2_m(vbool32_t mask,vint16mf2_t op1,vint8mf4_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i16mf2_m(mask,op1,op2,32);
+}
+
+
+vint16m1_t test___riscv_vwsub_wv_i16m1_m(vbool16_t mask,vint16m1_t op1,vint8mf2_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i16m1_m(mask,op1,op2,32);
+}
+
+
+vint16m2_t test___riscv_vwsub_wv_i16m2_m(vbool8_t mask,vint16m2_t op1,vint8m1_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i16m2_m(mask,op1,op2,32);
+}
+
+
+vint16m4_t test___riscv_vwsub_wv_i16m4_m(vbool4_t mask,vint16m4_t op1,vint8m2_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i16m4_m(mask,op1,op2,32);
+}
+
+
+vint16m8_t test___riscv_vwsub_wv_i16m8_m(vbool2_t mask,vint16m8_t op1,vint8m4_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i16m8_m(mask,op1,op2,32);
+}
+
+
+vint32mf2_t test___riscv_vwsub_wv_i32mf2_m(vbool64_t mask,vint32mf2_t op1,vint16mf4_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i32mf2_m(mask,op1,op2,32);
+}
+
+
+vint32m1_t test___riscv_vwsub_wv_i32m1_m(vbool32_t mask,vint32m1_t op1,vint16mf2_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i32m1_m(mask,op1,op2,32);
+}
+
+
+vint32m2_t test___riscv_vwsub_wv_i32m2_m(vbool16_t mask,vint32m2_t op1,vint16m1_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i32m2_m(mask,op1,op2,32);
+}
+
+
+vint32m4_t test___riscv_vwsub_wv_i32m4_m(vbool8_t mask,vint32m4_t op1,vint16m2_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i32m4_m(mask,op1,op2,32);
+}
+
+
+vint32m8_t test___riscv_vwsub_wv_i32m8_m(vbool4_t mask,vint32m8_t op1,vint16m4_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i32m8_m(mask,op1,op2,32);
+}
+
+
+vint64m1_t test___riscv_vwsub_wv_i64m1_m(vbool64_t mask,vint64m1_t op1,vint32mf2_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i64m1_m(mask,op1,op2,32);
+}
+
+
+vint64m2_t test___riscv_vwsub_wv_i64m2_m(vbool32_t mask,vint64m2_t op1,vint32m1_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i64m2_m(mask,op1,op2,32);
+}
+
+
+vint64m4_t test___riscv_vwsub_wv_i64m4_m(vbool16_t mask,vint64m4_t op1,vint32m2_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i64m4_m(mask,op1,op2,32);
+}
+
+
+vint64m8_t test___riscv_vwsub_wv_i64m8_m(vbool8_t mask,vint64m8_t op1,vint32m4_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i64m8_m(mask,op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwsub_wv_mu-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwsub_wv_mu-1.c
new file mode 100644
index 00000000000..f054e3fa4b0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwsub_wv_mu-1.c
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwsub_wv_i16mf4_mu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,vint8mf8_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i16mf4_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint16mf2_t test___riscv_vwsub_wv_i16mf2_mu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,vint8mf4_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i16mf2_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint16m1_t test___riscv_vwsub_wv_i16m1_mu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,vint8mf2_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i16m1_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint16m2_t test___riscv_vwsub_wv_i16m2_mu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,vint8m1_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i16m2_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint16m4_t test___riscv_vwsub_wv_i16m4_mu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,vint8m2_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i16m4_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint16m8_t test___riscv_vwsub_wv_i16m8_mu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,vint8m4_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i16m8_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint32mf2_t test___riscv_vwsub_wv_i32mf2_mu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,vint16mf4_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i32mf2_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint32m1_t test___riscv_vwsub_wv_i32m1_mu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,vint16mf2_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i32m1_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint32m2_t test___riscv_vwsub_wv_i32m2_mu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,vint16m1_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i32m2_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint32m4_t test___riscv_vwsub_wv_i32m4_mu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,vint16m2_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i32m4_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint32m8_t test___riscv_vwsub_wv_i32m8_mu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,vint16m4_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i32m8_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint64m1_t test___riscv_vwsub_wv_i64m1_mu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,vint32mf2_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i64m1_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint64m2_t test___riscv_vwsub_wv_i64m2_mu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,vint32m1_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i64m2_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint64m4_t test___riscv_vwsub_wv_i64m4_mu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,vint32m2_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i64m4_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint64m8_t test___riscv_vwsub_wv_i64m8_mu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,vint32m4_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i64m8_mu(mask,merge,op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwsub_wv_mu-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwsub_wv_mu-2.c
new file mode 100644
index 00000000000..55a982fa98d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwsub_wv_mu-2.c
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwsub_wv_i16mf4_mu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,vint8mf8_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i16mf4_mu(mask,merge,op1,op2,31);
+}
+
+
+vint16mf2_t test___riscv_vwsub_wv_i16mf2_mu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,vint8mf4_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i16mf2_mu(mask,merge,op1,op2,31);
+}
+
+
+vint16m1_t test___riscv_vwsub_wv_i16m1_mu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,vint8mf2_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i16m1_mu(mask,merge,op1,op2,31);
+}
+
+
+vint16m2_t test___riscv_vwsub_wv_i16m2_mu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,vint8m1_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i16m2_mu(mask,merge,op1,op2,31);
+}
+
+
+vint16m4_t test___riscv_vwsub_wv_i16m4_mu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,vint8m2_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i16m4_mu(mask,merge,op1,op2,31);
+}
+
+
+vint16m8_t test___riscv_vwsub_wv_i16m8_mu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,vint8m4_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i16m8_mu(mask,merge,op1,op2,31);
+}
+
+
+vint32mf2_t test___riscv_vwsub_wv_i32mf2_mu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,vint16mf4_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i32mf2_mu(mask,merge,op1,op2,31);
+}
+
+
+vint32m1_t test___riscv_vwsub_wv_i32m1_mu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,vint16mf2_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i32m1_mu(mask,merge,op1,op2,31);
+}
+
+
+vint32m2_t test___riscv_vwsub_wv_i32m2_mu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,vint16m1_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i32m2_mu(mask,merge,op1,op2,31);
+}
+
+
+vint32m4_t test___riscv_vwsub_wv_i32m4_mu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,vint16m2_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i32m4_mu(mask,merge,op1,op2,31);
+}
+
+
+vint32m8_t test___riscv_vwsub_wv_i32m8_mu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,vint16m4_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i32m8_mu(mask,merge,op1,op2,31);
+}
+
+
+vint64m1_t test___riscv_vwsub_wv_i64m1_mu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,vint32mf2_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i64m1_mu(mask,merge,op1,op2,31);
+}
+
+
+vint64m2_t test___riscv_vwsub_wv_i64m2_mu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,vint32m1_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i64m2_mu(mask,merge,op1,op2,31);
+}
+
+
+vint64m4_t test___riscv_vwsub_wv_i64m4_mu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,vint32m2_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i64m4_mu(mask,merge,op1,op2,31);
+}
+
+
+vint64m8_t test___riscv_vwsub_wv_i64m8_mu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,vint32m4_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i64m8_mu(mask,merge,op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwsub_wv_mu-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwsub_wv_mu-3.c
new file mode 100644
index 00000000000..6b1b7f35fa9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwsub_wv_mu-3.c
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwsub_wv_i16mf4_mu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,vint8mf8_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i16mf4_mu(mask,merge,op1,op2,32);
+}
+
+
+vint16mf2_t test___riscv_vwsub_wv_i16mf2_mu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,vint8mf4_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i16mf2_mu(mask,merge,op1,op2,32);
+}
+
+
+vint16m1_t test___riscv_vwsub_wv_i16m1_mu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,vint8mf2_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i16m1_mu(mask,merge,op1,op2,32);
+}
+
+
+vint16m2_t test___riscv_vwsub_wv_i16m2_mu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,vint8m1_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i16m2_mu(mask,merge,op1,op2,32);
+}
+
+
+vint16m4_t test___riscv_vwsub_wv_i16m4_mu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,vint8m2_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i16m4_mu(mask,merge,op1,op2,32);
+}
+
+
+vint16m8_t test___riscv_vwsub_wv_i16m8_mu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,vint8m4_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i16m8_mu(mask,merge,op1,op2,32);
+}
+
+
+vint32mf2_t test___riscv_vwsub_wv_i32mf2_mu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,vint16mf4_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i32mf2_mu(mask,merge,op1,op2,32);
+}
+
+
+vint32m1_t test___riscv_vwsub_wv_i32m1_mu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,vint16mf2_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i32m1_mu(mask,merge,op1,op2,32);
+}
+
+
+vint32m2_t test___riscv_vwsub_wv_i32m2_mu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,vint16m1_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i32m2_mu(mask,merge,op1,op2,32);
+}
+
+
+vint32m4_t test___riscv_vwsub_wv_i32m4_mu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,vint16m2_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i32m4_mu(mask,merge,op1,op2,32);
+}
+
+
+vint32m8_t test___riscv_vwsub_wv_i32m8_mu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,vint16m4_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i32m8_mu(mask,merge,op1,op2,32);
+}
+
+
+vint64m1_t test___riscv_vwsub_wv_i64m1_mu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,vint32mf2_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i64m1_mu(mask,merge,op1,op2,32);
+}
+
+
+vint64m2_t test___riscv_vwsub_wv_i64m2_mu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,vint32m1_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i64m2_mu(mask,merge,op1,op2,32);
+}
+
+
+vint64m4_t test___riscv_vwsub_wv_i64m4_mu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,vint32m2_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i64m4_mu(mask,merge,op1,op2,32);
+}
+
+
+vint64m8_t test___riscv_vwsub_wv_i64m8_mu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,vint32m4_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i64m8_mu(mask,merge,op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwsub_wv_tu-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwsub_wv_tu-1.c
new file mode 100644
index 00000000000..f2328f43ac3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwsub_wv_tu-1.c
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwsub_wv_i16mf4_tu(vint16mf4_t merge,vint16mf4_t op1,vint8mf8_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i16mf4_tu(merge,op1,op2,vl);
+}
+
+
+vint16mf2_t test___riscv_vwsub_wv_i16mf2_tu(vint16mf2_t merge,vint16mf2_t op1,vint8mf4_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i16mf2_tu(merge,op1,op2,vl);
+}
+
+
+vint16m1_t test___riscv_vwsub_wv_i16m1_tu(vint16m1_t merge,vint16m1_t op1,vint8mf2_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i16m1_tu(merge,op1,op2,vl);
+}
+
+
+vint16m2_t test___riscv_vwsub_wv_i16m2_tu(vint16m2_t merge,vint16m2_t op1,vint8m1_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i16m2_tu(merge,op1,op2,vl);
+}
+
+
+vint16m4_t test___riscv_vwsub_wv_i16m4_tu(vint16m4_t merge,vint16m4_t op1,vint8m2_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i16m4_tu(merge,op1,op2,vl);
+}
+
+
+vint16m8_t test___riscv_vwsub_wv_i16m8_tu(vint16m8_t merge,vint16m8_t op1,vint8m4_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i16m8_tu(merge,op1,op2,vl);
+}
+
+
+vint32mf2_t test___riscv_vwsub_wv_i32mf2_tu(vint32mf2_t merge,vint32mf2_t op1,vint16mf4_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i32mf2_tu(merge,op1,op2,vl);
+}
+
+
+vint32m1_t test___riscv_vwsub_wv_i32m1_tu(vint32m1_t merge,vint32m1_t op1,vint16mf2_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i32m1_tu(merge,op1,op2,vl);
+}
+
+
+vint32m2_t test___riscv_vwsub_wv_i32m2_tu(vint32m2_t merge,vint32m2_t op1,vint16m1_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i32m2_tu(merge,op1,op2,vl);
+}
+
+
+vint32m4_t test___riscv_vwsub_wv_i32m4_tu(vint32m4_t merge,vint32m4_t op1,vint16m2_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i32m4_tu(merge,op1,op2,vl);
+}
+
+
+vint32m8_t test___riscv_vwsub_wv_i32m8_tu(vint32m8_t merge,vint32m8_t op1,vint16m4_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i32m8_tu(merge,op1,op2,vl);
+}
+
+
+vint64m1_t test___riscv_vwsub_wv_i64m1_tu(vint64m1_t merge,vint64m1_t op1,vint32mf2_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i64m1_tu(merge,op1,op2,vl);
+}
+
+
+vint64m2_t test___riscv_vwsub_wv_i64m2_tu(vint64m2_t merge,vint64m2_t op1,vint32m1_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i64m2_tu(merge,op1,op2,vl);
+}
+
+
+vint64m4_t test___riscv_vwsub_wv_i64m4_tu(vint64m4_t merge,vint64m4_t op1,vint32m2_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i64m4_tu(merge,op1,op2,vl);
+}
+
+
+vint64m8_t test___riscv_vwsub_wv_i64m8_tu(vint64m8_t merge,vint64m8_t op1,vint32m4_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i64m8_tu(merge,op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwsub_wv_tu-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwsub_wv_tu-2.c
new file mode 100644
index 00000000000..939df35b8fb
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwsub_wv_tu-2.c
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwsub_wv_i16mf4_tu(vint16mf4_t merge,vint16mf4_t op1,vint8mf8_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i16mf4_tu(merge,op1,op2,31);
+}
+
+
+vint16mf2_t test___riscv_vwsub_wv_i16mf2_tu(vint16mf2_t merge,vint16mf2_t op1,vint8mf4_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i16mf2_tu(merge,op1,op2,31);
+}
+
+
+vint16m1_t test___riscv_vwsub_wv_i16m1_tu(vint16m1_t merge,vint16m1_t op1,vint8mf2_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i16m1_tu(merge,op1,op2,31);
+}
+
+
+vint16m2_t test___riscv_vwsub_wv_i16m2_tu(vint16m2_t merge,vint16m2_t op1,vint8m1_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i16m2_tu(merge,op1,op2,31);
+}
+
+
+vint16m4_t test___riscv_vwsub_wv_i16m4_tu(vint16m4_t merge,vint16m4_t op1,vint8m2_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i16m4_tu(merge,op1,op2,31);
+}
+
+
+vint16m8_t test___riscv_vwsub_wv_i16m8_tu(vint16m8_t merge,vint16m8_t op1,vint8m4_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i16m8_tu(merge,op1,op2,31);
+}
+
+
+vint32mf2_t test___riscv_vwsub_wv_i32mf2_tu(vint32mf2_t merge,vint32mf2_t op1,vint16mf4_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i32mf2_tu(merge,op1,op2,31);
+}
+
+
+vint32m1_t test___riscv_vwsub_wv_i32m1_tu(vint32m1_t merge,vint32m1_t op1,vint16mf2_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i32m1_tu(merge,op1,op2,31);
+}
+
+
+vint32m2_t test___riscv_vwsub_wv_i32m2_tu(vint32m2_t merge,vint32m2_t op1,vint16m1_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i32m2_tu(merge,op1,op2,31);
+}
+
+
+vint32m4_t test___riscv_vwsub_wv_i32m4_tu(vint32m4_t merge,vint32m4_t op1,vint16m2_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i32m4_tu(merge,op1,op2,31);
+}
+
+
+vint32m8_t test___riscv_vwsub_wv_i32m8_tu(vint32m8_t merge,vint32m8_t op1,vint16m4_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i32m8_tu(merge,op1,op2,31);
+}
+
+
+vint64m1_t test___riscv_vwsub_wv_i64m1_tu(vint64m1_t merge,vint64m1_t op1,vint32mf2_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i64m1_tu(merge,op1,op2,31);
+}
+
+
+vint64m2_t test___riscv_vwsub_wv_i64m2_tu(vint64m2_t merge,vint64m2_t op1,vint32m1_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i64m2_tu(merge,op1,op2,31);
+}
+
+
+vint64m4_t test___riscv_vwsub_wv_i64m4_tu(vint64m4_t merge,vint64m4_t op1,vint32m2_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i64m4_tu(merge,op1,op2,31);
+}
+
+
+vint64m8_t test___riscv_vwsub_wv_i64m8_tu(vint64m8_t merge,vint64m8_t op1,vint32m4_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i64m8_tu(merge,op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwsub_wv_tu-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwsub_wv_tu-3.c
new file mode 100644
index 00000000000..faa70af8bdb
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwsub_wv_tu-3.c
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwsub_wv_i16mf4_tu(vint16mf4_t merge,vint16mf4_t op1,vint8mf8_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i16mf4_tu(merge,op1,op2,32);
+}
+
+
+vint16mf2_t test___riscv_vwsub_wv_i16mf2_tu(vint16mf2_t merge,vint16mf2_t op1,vint8mf4_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i16mf2_tu(merge,op1,op2,32);
+}
+
+
+vint16m1_t test___riscv_vwsub_wv_i16m1_tu(vint16m1_t merge,vint16m1_t op1,vint8mf2_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i16m1_tu(merge,op1,op2,32);
+}
+
+
+vint16m2_t test___riscv_vwsub_wv_i16m2_tu(vint16m2_t merge,vint16m2_t op1,vint8m1_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i16m2_tu(merge,op1,op2,32);
+}
+
+
+vint16m4_t test___riscv_vwsub_wv_i16m4_tu(vint16m4_t merge,vint16m4_t op1,vint8m2_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i16m4_tu(merge,op1,op2,32);
+}
+
+
+vint16m8_t test___riscv_vwsub_wv_i16m8_tu(vint16m8_t merge,vint16m8_t op1,vint8m4_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i16m8_tu(merge,op1,op2,32);
+}
+
+
+vint32mf2_t test___riscv_vwsub_wv_i32mf2_tu(vint32mf2_t merge,vint32mf2_t op1,vint16mf4_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i32mf2_tu(merge,op1,op2,32);
+}
+
+
+vint32m1_t test___riscv_vwsub_wv_i32m1_tu(vint32m1_t merge,vint32m1_t op1,vint16mf2_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i32m1_tu(merge,op1,op2,32);
+}
+
+
+vint32m2_t test___riscv_vwsub_wv_i32m2_tu(vint32m2_t merge,vint32m2_t op1,vint16m1_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i32m2_tu(merge,op1,op2,32);
+}
+
+
+vint32m4_t test___riscv_vwsub_wv_i32m4_tu(vint32m4_t merge,vint32m4_t op1,vint16m2_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i32m4_tu(merge,op1,op2,32);
+}
+
+
+vint32m8_t test___riscv_vwsub_wv_i32m8_tu(vint32m8_t merge,vint32m8_t op1,vint16m4_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i32m8_tu(merge,op1,op2,32);
+}
+
+
+vint64m1_t test___riscv_vwsub_wv_i64m1_tu(vint64m1_t merge,vint64m1_t op1,vint32mf2_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i64m1_tu(merge,op1,op2,32);
+}
+
+
+vint64m2_t test___riscv_vwsub_wv_i64m2_tu(vint64m2_t merge,vint64m2_t op1,vint32m1_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i64m2_tu(merge,op1,op2,32);
+}
+
+
+vint64m4_t test___riscv_vwsub_wv_i64m4_tu(vint64m4_t merge,vint64m4_t op1,vint32m2_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i64m4_tu(merge,op1,op2,32);
+}
+
+
+vint64m8_t test___riscv_vwsub_wv_i64m8_tu(vint64m8_t merge,vint64m8_t op1,vint32m4_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i64m8_tu(merge,op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwsub_wv_tum-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwsub_wv_tum-1.c
new file mode 100644
index 00000000000..956928f4aa1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwsub_wv_tum-1.c
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwsub_wv_i16mf4_tum(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,vint8mf8_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i16mf4_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint16mf2_t test___riscv_vwsub_wv_i16mf2_tum(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,vint8mf4_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i16mf2_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint16m1_t test___riscv_vwsub_wv_i16m1_tum(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,vint8mf2_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i16m1_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint16m2_t test___riscv_vwsub_wv_i16m2_tum(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,vint8m1_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i16m2_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint16m4_t test___riscv_vwsub_wv_i16m4_tum(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,vint8m2_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i16m4_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint16m8_t test___riscv_vwsub_wv_i16m8_tum(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,vint8m4_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i16m8_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint32mf2_t test___riscv_vwsub_wv_i32mf2_tum(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,vint16mf4_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i32mf2_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint32m1_t test___riscv_vwsub_wv_i32m1_tum(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,vint16mf2_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i32m1_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint32m2_t test___riscv_vwsub_wv_i32m2_tum(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,vint16m1_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i32m2_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint32m4_t test___riscv_vwsub_wv_i32m4_tum(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,vint16m2_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i32m4_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint32m8_t test___riscv_vwsub_wv_i32m8_tum(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,vint16m4_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i32m8_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint64m1_t test___riscv_vwsub_wv_i64m1_tum(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,vint32mf2_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i64m1_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint64m2_t test___riscv_vwsub_wv_i64m2_tum(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,vint32m1_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i64m2_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint64m4_t test___riscv_vwsub_wv_i64m4_tum(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,vint32m2_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i64m4_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint64m8_t test___riscv_vwsub_wv_i64m8_tum(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,vint32m4_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i64m8_tum(mask,merge,op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwsub_wv_tum-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwsub_wv_tum-2.c
new file mode 100644
index 00000000000..77e532a62ee
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwsub_wv_tum-2.c
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwsub_wv_i16mf4_tum(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,vint8mf8_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i16mf4_tum(mask,merge,op1,op2,31);
+}
+
+
+vint16mf2_t test___riscv_vwsub_wv_i16mf2_tum(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,vint8mf4_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i16mf2_tum(mask,merge,op1,op2,31);
+}
+
+
+vint16m1_t test___riscv_vwsub_wv_i16m1_tum(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,vint8mf2_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i16m1_tum(mask,merge,op1,op2,31);
+}
+
+
+vint16m2_t test___riscv_vwsub_wv_i16m2_tum(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,vint8m1_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i16m2_tum(mask,merge,op1,op2,31);
+}
+
+
+vint16m4_t test___riscv_vwsub_wv_i16m4_tum(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,vint8m2_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i16m4_tum(mask,merge,op1,op2,31);
+}
+
+
+vint16m8_t test___riscv_vwsub_wv_i16m8_tum(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,vint8m4_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i16m8_tum(mask,merge,op1,op2,31);
+}
+
+
+vint32mf2_t test___riscv_vwsub_wv_i32mf2_tum(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,vint16mf4_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i32mf2_tum(mask,merge,op1,op2,31);
+}
+
+
+vint32m1_t test___riscv_vwsub_wv_i32m1_tum(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,vint16mf2_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i32m1_tum(mask,merge,op1,op2,31);
+}
+
+
+vint32m2_t test___riscv_vwsub_wv_i32m2_tum(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,vint16m1_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i32m2_tum(mask,merge,op1,op2,31);
+}
+
+
+vint32m4_t test___riscv_vwsub_wv_i32m4_tum(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,vint16m2_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i32m4_tum(mask,merge,op1,op2,31);
+}
+
+
+vint32m8_t test___riscv_vwsub_wv_i32m8_tum(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,vint16m4_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i32m8_tum(mask,merge,op1,op2,31);
+}
+
+
+vint64m1_t test___riscv_vwsub_wv_i64m1_tum(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,vint32mf2_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i64m1_tum(mask,merge,op1,op2,31);
+}
+
+
+vint64m2_t test___riscv_vwsub_wv_i64m2_tum(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,vint32m1_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i64m2_tum(mask,merge,op1,op2,31);
+}
+
+
+vint64m4_t test___riscv_vwsub_wv_i64m4_tum(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,vint32m2_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i64m4_tum(mask,merge,op1,op2,31);
+}
+
+
+vint64m8_t test___riscv_vwsub_wv_i64m8_tum(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,vint32m4_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i64m8_tum(mask,merge,op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwsub_wv_tum-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwsub_wv_tum-3.c
new file mode 100644
index 00000000000..5f06dc19978
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwsub_wv_tum-3.c
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwsub_wv_i16mf4_tum(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,vint8mf8_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i16mf4_tum(mask,merge,op1,op2,32);
+}
+
+
+vint16mf2_t test___riscv_vwsub_wv_i16mf2_tum(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,vint8mf4_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i16mf2_tum(mask,merge,op1,op2,32);
+}
+
+
+vint16m1_t test___riscv_vwsub_wv_i16m1_tum(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,vint8mf2_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i16m1_tum(mask,merge,op1,op2,32);
+}
+
+
+vint16m2_t test___riscv_vwsub_wv_i16m2_tum(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,vint8m1_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i16m2_tum(mask,merge,op1,op2,32);
+}
+
+
+vint16m4_t test___riscv_vwsub_wv_i16m4_tum(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,vint8m2_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i16m4_tum(mask,merge,op1,op2,32);
+}
+
+
+vint16m8_t test___riscv_vwsub_wv_i16m8_tum(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,vint8m4_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i16m8_tum(mask,merge,op1,op2,32);
+}
+
+
+vint32mf2_t test___riscv_vwsub_wv_i32mf2_tum(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,vint16mf4_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i32mf2_tum(mask,merge,op1,op2,32);
+}
+
+
+vint32m1_t test___riscv_vwsub_wv_i32m1_tum(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,vint16mf2_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i32m1_tum(mask,merge,op1,op2,32);
+}
+
+
+vint32m2_t test___riscv_vwsub_wv_i32m2_tum(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,vint16m1_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i32m2_tum(mask,merge,op1,op2,32);
+}
+
+
+vint32m4_t test___riscv_vwsub_wv_i32m4_tum(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,vint16m2_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i32m4_tum(mask,merge,op1,op2,32);
+}
+
+
+vint32m8_t test___riscv_vwsub_wv_i32m8_tum(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,vint16m4_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i32m8_tum(mask,merge,op1,op2,32);
+}
+
+
+vint64m1_t test___riscv_vwsub_wv_i64m1_tum(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,vint32mf2_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i64m1_tum(mask,merge,op1,op2,32);
+}
+
+
+vint64m2_t test___riscv_vwsub_wv_i64m2_tum(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,vint32m1_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i64m2_tum(mask,merge,op1,op2,32);
+}
+
+
+vint64m4_t test___riscv_vwsub_wv_i64m4_tum(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,vint32m2_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i64m4_tum(mask,merge,op1,op2,32);
+}
+
+
+vint64m8_t test___riscv_vwsub_wv_i64m8_tum(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,vint32m4_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i64m8_tum(mask,merge,op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwsub_wv_tumu-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwsub_wv_tumu-1.c
new file mode 100644
index 00000000000..42b37dfb5ac
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwsub_wv_tumu-1.c
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwsub_wv_i16mf4_tumu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,vint8mf8_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i16mf4_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint16mf2_t test___riscv_vwsub_wv_i16mf2_tumu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,vint8mf4_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i16mf2_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint16m1_t test___riscv_vwsub_wv_i16m1_tumu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,vint8mf2_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i16m1_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint16m2_t test___riscv_vwsub_wv_i16m2_tumu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,vint8m1_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i16m2_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint16m4_t test___riscv_vwsub_wv_i16m4_tumu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,vint8m2_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i16m4_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint16m8_t test___riscv_vwsub_wv_i16m8_tumu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,vint8m4_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i16m8_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint32mf2_t test___riscv_vwsub_wv_i32mf2_tumu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,vint16mf4_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i32mf2_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint32m1_t test___riscv_vwsub_wv_i32m1_tumu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,vint16mf2_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i32m1_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint32m2_t test___riscv_vwsub_wv_i32m2_tumu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,vint16m1_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i32m2_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint32m4_t test___riscv_vwsub_wv_i32m4_tumu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,vint16m2_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i32m4_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint32m8_t test___riscv_vwsub_wv_i32m8_tumu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,vint16m4_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i32m8_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint64m1_t test___riscv_vwsub_wv_i64m1_tumu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,vint32mf2_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i64m1_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint64m2_t test___riscv_vwsub_wv_i64m2_tumu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,vint32m1_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i64m2_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint64m4_t test___riscv_vwsub_wv_i64m4_tumu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,vint32m2_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i64m4_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint64m8_t test___riscv_vwsub_wv_i64m8_tumu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,vint32m4_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i64m8_tumu(mask,merge,op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwsub_wv_tumu-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwsub_wv_tumu-2.c
new file mode 100644
index 00000000000..338f9680a06
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwsub_wv_tumu-2.c
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwsub_wv_i16mf4_tumu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,vint8mf8_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i16mf4_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint16mf2_t test___riscv_vwsub_wv_i16mf2_tumu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,vint8mf4_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i16mf2_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint16m1_t test___riscv_vwsub_wv_i16m1_tumu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,vint8mf2_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i16m1_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint16m2_t test___riscv_vwsub_wv_i16m2_tumu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,vint8m1_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i16m2_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint16m4_t test___riscv_vwsub_wv_i16m4_tumu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,vint8m2_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i16m4_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint16m8_t test___riscv_vwsub_wv_i16m8_tumu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,vint8m4_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i16m8_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint32mf2_t test___riscv_vwsub_wv_i32mf2_tumu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,vint16mf4_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i32mf2_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint32m1_t test___riscv_vwsub_wv_i32m1_tumu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,vint16mf2_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i32m1_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint32m2_t test___riscv_vwsub_wv_i32m2_tumu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,vint16m1_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i32m2_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint32m4_t test___riscv_vwsub_wv_i32m4_tumu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,vint16m2_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i32m4_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint32m8_t test___riscv_vwsub_wv_i32m8_tumu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,vint16m4_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i32m8_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint64m1_t test___riscv_vwsub_wv_i64m1_tumu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,vint32mf2_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i64m1_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint64m2_t test___riscv_vwsub_wv_i64m2_tumu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,vint32m1_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i64m2_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint64m4_t test___riscv_vwsub_wv_i64m4_tumu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,vint32m2_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i64m4_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint64m8_t test___riscv_vwsub_wv_i64m8_tumu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,vint32m4_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i64m8_tumu(mask,merge,op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwsub_wv_tumu-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwsub_wv_tumu-3.c
new file mode 100644
index 00000000000..a8efaf7c2ae
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwsub_wv_tumu-3.c
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwsub_wv_i16mf4_tumu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,vint8mf8_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i16mf4_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint16mf2_t test___riscv_vwsub_wv_i16mf2_tumu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,vint8mf4_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i16mf2_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint16m1_t test___riscv_vwsub_wv_i16m1_tumu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,vint8mf2_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i16m1_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint16m2_t test___riscv_vwsub_wv_i16m2_tumu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,vint8m1_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i16m2_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint16m4_t test___riscv_vwsub_wv_i16m4_tumu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,vint8m2_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i16m4_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint16m8_t test___riscv_vwsub_wv_i16m8_tumu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,vint8m4_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i16m8_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint32mf2_t test___riscv_vwsub_wv_i32mf2_tumu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,vint16mf4_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i32mf2_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint32m1_t test___riscv_vwsub_wv_i32m1_tumu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,vint16mf2_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i32m1_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint32m2_t test___riscv_vwsub_wv_i32m2_tumu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,vint16m1_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i32m2_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint32m4_t test___riscv_vwsub_wv_i32m4_tumu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,vint16m2_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i32m4_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint32m8_t test___riscv_vwsub_wv_i32m8_tumu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,vint16m4_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i32m8_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint64m1_t test___riscv_vwsub_wv_i64m1_tumu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,vint32mf2_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i64m1_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint64m2_t test___riscv_vwsub_wv_i64m2_tumu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,vint32m1_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i64m2_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint64m4_t test___riscv_vwsub_wv_i64m4_tumu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,vint32m2_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i64m4_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint64m8_t test___riscv_vwsub_wv_i64m8_tumu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,vint32m4_t op2,size_t vl)
+{
+    return __riscv_vwsub_wv_i64m8_tumu(mask,merge,op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */