From patchwork Tue Feb 7 06:17:12 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "juzhe.zhong@rivai.ai" X-Patchwork-Id: 64405 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 913D23858017 for ; Tue, 7 Feb 2023 06:17:45 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from smtpbgeu2.qq.com (smtpbgeu2.qq.com [18.194.254.142]) by sourceware.org (Postfix) with ESMTPS id 6BD903858D1E for ; Tue, 7 Feb 2023 06:17:20 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 6BD903858D1E Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivai.ai Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivai.ai X-QQ-mid: bizesmtp76t1675750633tsam1s78 Received: from server1.localdomain ( [58.60.1.22]) by bizesmtp.qq.com (ESMTP) with id ; Tue, 07 Feb 2023 14:17:12 +0800 (CST) X-QQ-SSF: 01400000000000E0L000000A0000000 X-QQ-FEAT: FmjKyZQYvyAtAhQNN/3dXx+Gn+oZmVaAdGhTetLXWeEYyGpuEV/mTmbgLirkw Yv38Wyt1m3xbrHI0Ho6XY35BXxVbDSfq31JdnXvsGmx+1VSzAs/xhMOHXvWSZzNFRlrpb3T DmnEUXw2dYDJzZWU3jkMMEBesnO65CAHvq1ZsK+7NlwJh6lHdkmr5e6nfPl+2ed0+meBz3G gRBotXptandf3KfWUR0eMSvIK6eQMjdgLNZL0teGWi18KVQyA3xspJkG9Xc13lkD37R52Xk vrTFqabX4YTaDqt+CYTOkXH4TU8ij4yu9+vxVyM2PjAYGMOAfxdy5NweuhzGV1puSuBclRL Zg5XFqmZ16kLeHM6ET4RVn5AkYl1wnXtfKXphseeag4XpstcQT0fx5XB0UnfPMOvE9JavAV X-QQ-GoodBg: 2 From: juzhe.zhong@rivai.ai To: gcc-patches@gcc.gnu.org Cc: kito.cheng@gmail.com, Ju-Zhe Zhong Subject: [PATCH] RISC-V: Add vwsubu.wx C API tests Date: Tue, 7 Feb 2023 14:17:12 +0800 Message-Id: <20230207061712.33613-1-juzhe.zhong@rivai.ai> X-Mailer: git-send-email 2.36.1 MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:rivai.ai:qybglogicsvr:qybglogicsvr7 X-Spam-Status: No, score=-10.9 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, KAM_SHORT, RCVD_IN_BARRACUDACENTRAL, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_PASS, TXREP, T_SPF_HELO_TEMPERROR autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" From: Ju-Zhe Zhong gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/vwsubu_wv-1.c: New test. * gcc.target/riscv/rvv/base/vwsubu_wv-2.c: New test. * gcc.target/riscv/rvv/base/vwsubu_wv-3.c: New test. * gcc.target/riscv/rvv/base/vwsubu_wv_m-1.c: New test. * gcc.target/riscv/rvv/base/vwsubu_wv_m-2.c: New test. * gcc.target/riscv/rvv/base/vwsubu_wv_m-3.c: New test. * gcc.target/riscv/rvv/base/vwsubu_wv_mu-1.c: New test. * gcc.target/riscv/rvv/base/vwsubu_wv_mu-2.c: New test. * gcc.target/riscv/rvv/base/vwsubu_wv_mu-3.c: New test. * gcc.target/riscv/rvv/base/vwsubu_wv_tu-1.c: New test. * gcc.target/riscv/rvv/base/vwsubu_wv_tu-2.c: New test. * gcc.target/riscv/rvv/base/vwsubu_wv_tu-3.c: New test. * gcc.target/riscv/rvv/base/vwsubu_wv_tum-1.c: New test. * gcc.target/riscv/rvv/base/vwsubu_wv_tum-2.c: New test. * gcc.target/riscv/rvv/base/vwsubu_wv_tum-3.c: New test. * gcc.target/riscv/rvv/base/vwsubu_wv_tumu-1.c: New test. * gcc.target/riscv/rvv/base/vwsubu_wv_tumu-2.c: New test. * gcc.target/riscv/rvv/base/vwsubu_wv_tumu-3.c: New test. --- .../gcc.target/riscv/rvv/base/vwsubu_wv-1.c | 111 ++++++++++++++++++ .../gcc.target/riscv/rvv/base/vwsubu_wv-2.c | 111 ++++++++++++++++++ .../gcc.target/riscv/rvv/base/vwsubu_wv-3.c | 111 ++++++++++++++++++ .../gcc.target/riscv/rvv/base/vwsubu_wv_m-1.c | 111 ++++++++++++++++++ .../gcc.target/riscv/rvv/base/vwsubu_wv_m-2.c | 111 ++++++++++++++++++ .../gcc.target/riscv/rvv/base/vwsubu_wv_m-3.c | 111 ++++++++++++++++++ .../riscv/rvv/base/vwsubu_wv_mu-1.c | 111 ++++++++++++++++++ .../riscv/rvv/base/vwsubu_wv_mu-2.c | 111 ++++++++++++++++++ .../riscv/rvv/base/vwsubu_wv_mu-3.c | 111 ++++++++++++++++++ .../riscv/rvv/base/vwsubu_wv_tu-1.c | 111 ++++++++++++++++++ .../riscv/rvv/base/vwsubu_wv_tu-2.c | 111 ++++++++++++++++++ .../riscv/rvv/base/vwsubu_wv_tu-3.c | 111 ++++++++++++++++++ .../riscv/rvv/base/vwsubu_wv_tum-1.c | 111 ++++++++++++++++++ .../riscv/rvv/base/vwsubu_wv_tum-2.c | 111 ++++++++++++++++++ .../riscv/rvv/base/vwsubu_wv_tum-3.c | 111 ++++++++++++++++++ .../riscv/rvv/base/vwsubu_wv_tumu-1.c | 111 ++++++++++++++++++ .../riscv/rvv/base/vwsubu_wv_tumu-2.c | 111 ++++++++++++++++++ .../riscv/rvv/base/vwsubu_wv_tumu-3.c | 111 ++++++++++++++++++ 18 files changed, 1998 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wv-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wv-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wv-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wv_m-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wv_m-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wv_m-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wv_mu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wv_mu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wv_mu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wv_tu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wv_tu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wv_tu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wv_tum-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wv_tum-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wv_tum-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wv_tumu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wv_tumu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wv_tumu-3.c diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wv-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wv-1.c new file mode 100644 index 00000000000..73d261cc78b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wv-1.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwsubu_wv_u16mf4(vuint16mf4_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u16mf4(op1,op2,vl); +} + + +vuint16mf2_t test___riscv_vwsubu_wv_u16mf2(vuint16mf2_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u16mf2(op1,op2,vl); +} + + +vuint16m1_t test___riscv_vwsubu_wv_u16m1(vuint16m1_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u16m1(op1,op2,vl); +} + + +vuint16m2_t test___riscv_vwsubu_wv_u16m2(vuint16m2_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u16m2(op1,op2,vl); +} + + +vuint16m4_t test___riscv_vwsubu_wv_u16m4(vuint16m4_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u16m4(op1,op2,vl); +} + + +vuint16m8_t test___riscv_vwsubu_wv_u16m8(vuint16m8_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u16m8(op1,op2,vl); +} + + +vuint32mf2_t test___riscv_vwsubu_wv_u32mf2(vuint32mf2_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u32mf2(op1,op2,vl); +} + + +vuint32m1_t test___riscv_vwsubu_wv_u32m1(vuint32m1_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u32m1(op1,op2,vl); +} + + +vuint32m2_t test___riscv_vwsubu_wv_u32m2(vuint32m2_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u32m2(op1,op2,vl); +} + + +vuint32m4_t test___riscv_vwsubu_wv_u32m4(vuint32m4_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u32m4(op1,op2,vl); +} + + +vuint32m8_t test___riscv_vwsubu_wv_u32m8(vuint32m8_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u32m8(op1,op2,vl); +} + + +vuint64m1_t test___riscv_vwsubu_wv_u64m1(vuint64m1_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u64m1(op1,op2,vl); +} + + +vuint64m2_t test___riscv_vwsubu_wv_u64m2(vuint64m2_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u64m2(op1,op2,vl); +} + + +vuint64m4_t test___riscv_vwsubu_wv_u64m4(vuint64m4_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u64m4(op1,op2,vl); +} + + +vuint64m8_t test___riscv_vwsubu_wv_u64m8(vuint64m8_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u64m8(op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wv-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wv-2.c new file mode 100644 index 00000000000..9866b9b1533 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wv-2.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwsubu_wv_u16mf4(vuint16mf4_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u16mf4(op1,op2,31); +} + + +vuint16mf2_t test___riscv_vwsubu_wv_u16mf2(vuint16mf2_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u16mf2(op1,op2,31); +} + + +vuint16m1_t test___riscv_vwsubu_wv_u16m1(vuint16m1_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u16m1(op1,op2,31); +} + + +vuint16m2_t test___riscv_vwsubu_wv_u16m2(vuint16m2_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u16m2(op1,op2,31); +} + + +vuint16m4_t test___riscv_vwsubu_wv_u16m4(vuint16m4_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u16m4(op1,op2,31); +} + + +vuint16m8_t test___riscv_vwsubu_wv_u16m8(vuint16m8_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u16m8(op1,op2,31); +} + + +vuint32mf2_t test___riscv_vwsubu_wv_u32mf2(vuint32mf2_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u32mf2(op1,op2,31); +} + + +vuint32m1_t test___riscv_vwsubu_wv_u32m1(vuint32m1_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u32m1(op1,op2,31); +} + + +vuint32m2_t test___riscv_vwsubu_wv_u32m2(vuint32m2_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u32m2(op1,op2,31); +} + + +vuint32m4_t test___riscv_vwsubu_wv_u32m4(vuint32m4_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u32m4(op1,op2,31); +} + + +vuint32m8_t test___riscv_vwsubu_wv_u32m8(vuint32m8_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u32m8(op1,op2,31); +} + + +vuint64m1_t test___riscv_vwsubu_wv_u64m1(vuint64m1_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u64m1(op1,op2,31); +} + + +vuint64m2_t test___riscv_vwsubu_wv_u64m2(vuint64m2_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u64m2(op1,op2,31); +} + + +vuint64m4_t test___riscv_vwsubu_wv_u64m4(vuint64m4_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u64m4(op1,op2,31); +} + + +vuint64m8_t test___riscv_vwsubu_wv_u64m8(vuint64m8_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u64m8(op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wv-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wv-3.c new file mode 100644 index 00000000000..a4db286ed97 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wv-3.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwsubu_wv_u16mf4(vuint16mf4_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u16mf4(op1,op2,32); +} + + +vuint16mf2_t test___riscv_vwsubu_wv_u16mf2(vuint16mf2_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u16mf2(op1,op2,32); +} + + +vuint16m1_t test___riscv_vwsubu_wv_u16m1(vuint16m1_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u16m1(op1,op2,32); +} + + +vuint16m2_t test___riscv_vwsubu_wv_u16m2(vuint16m2_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u16m2(op1,op2,32); +} + + +vuint16m4_t test___riscv_vwsubu_wv_u16m4(vuint16m4_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u16m4(op1,op2,32); +} + + +vuint16m8_t test___riscv_vwsubu_wv_u16m8(vuint16m8_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u16m8(op1,op2,32); +} + + +vuint32mf2_t test___riscv_vwsubu_wv_u32mf2(vuint32mf2_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u32mf2(op1,op2,32); +} + + +vuint32m1_t test___riscv_vwsubu_wv_u32m1(vuint32m1_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u32m1(op1,op2,32); +} + + +vuint32m2_t test___riscv_vwsubu_wv_u32m2(vuint32m2_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u32m2(op1,op2,32); +} + + +vuint32m4_t test___riscv_vwsubu_wv_u32m4(vuint32m4_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u32m4(op1,op2,32); +} + + +vuint32m8_t test___riscv_vwsubu_wv_u32m8(vuint32m8_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u32m8(op1,op2,32); +} + + +vuint64m1_t test___riscv_vwsubu_wv_u64m1(vuint64m1_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u64m1(op1,op2,32); +} + + +vuint64m2_t test___riscv_vwsubu_wv_u64m2(vuint64m2_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u64m2(op1,op2,32); +} + + +vuint64m4_t test___riscv_vwsubu_wv_u64m4(vuint64m4_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u64m4(op1,op2,32); +} + + +vuint64m8_t test___riscv_vwsubu_wv_u64m8(vuint64m8_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u64m8(op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wv_m-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wv_m-1.c new file mode 100644 index 00000000000..34dc24aadb1 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wv_m-1.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwsubu_wv_u16mf4_m(vbool64_t mask,vuint16mf4_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u16mf4_m(mask,op1,op2,vl); +} + + +vuint16mf2_t test___riscv_vwsubu_wv_u16mf2_m(vbool32_t mask,vuint16mf2_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u16mf2_m(mask,op1,op2,vl); +} + + +vuint16m1_t test___riscv_vwsubu_wv_u16m1_m(vbool16_t mask,vuint16m1_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u16m1_m(mask,op1,op2,vl); +} + + +vuint16m2_t test___riscv_vwsubu_wv_u16m2_m(vbool8_t mask,vuint16m2_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u16m2_m(mask,op1,op2,vl); +} + + +vuint16m4_t test___riscv_vwsubu_wv_u16m4_m(vbool4_t mask,vuint16m4_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u16m4_m(mask,op1,op2,vl); +} + + +vuint16m8_t test___riscv_vwsubu_wv_u16m8_m(vbool2_t mask,vuint16m8_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u16m8_m(mask,op1,op2,vl); +} + + +vuint32mf2_t test___riscv_vwsubu_wv_u32mf2_m(vbool64_t mask,vuint32mf2_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u32mf2_m(mask,op1,op2,vl); +} + + +vuint32m1_t test___riscv_vwsubu_wv_u32m1_m(vbool32_t mask,vuint32m1_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u32m1_m(mask,op1,op2,vl); +} + + +vuint32m2_t test___riscv_vwsubu_wv_u32m2_m(vbool16_t mask,vuint32m2_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u32m2_m(mask,op1,op2,vl); +} + + +vuint32m4_t test___riscv_vwsubu_wv_u32m4_m(vbool8_t mask,vuint32m4_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u32m4_m(mask,op1,op2,vl); +} + + +vuint32m8_t test___riscv_vwsubu_wv_u32m8_m(vbool4_t mask,vuint32m8_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u32m8_m(mask,op1,op2,vl); +} + + +vuint64m1_t test___riscv_vwsubu_wv_u64m1_m(vbool64_t mask,vuint64m1_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u64m1_m(mask,op1,op2,vl); +} + + +vuint64m2_t test___riscv_vwsubu_wv_u64m2_m(vbool32_t mask,vuint64m2_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u64m2_m(mask,op1,op2,vl); +} + + +vuint64m4_t test___riscv_vwsubu_wv_u64m4_m(vbool16_t mask,vuint64m4_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u64m4_m(mask,op1,op2,vl); +} + + +vuint64m8_t test___riscv_vwsubu_wv_u64m8_m(vbool8_t mask,vuint64m8_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u64m8_m(mask,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wv_m-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wv_m-2.c new file mode 100644 index 00000000000..abcfc4b7c64 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wv_m-2.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwsubu_wv_u16mf4_m(vbool64_t mask,vuint16mf4_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u16mf4_m(mask,op1,op2,31); +} + + +vuint16mf2_t test___riscv_vwsubu_wv_u16mf2_m(vbool32_t mask,vuint16mf2_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u16mf2_m(mask,op1,op2,31); +} + + +vuint16m1_t test___riscv_vwsubu_wv_u16m1_m(vbool16_t mask,vuint16m1_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u16m1_m(mask,op1,op2,31); +} + + +vuint16m2_t test___riscv_vwsubu_wv_u16m2_m(vbool8_t mask,vuint16m2_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u16m2_m(mask,op1,op2,31); +} + + +vuint16m4_t test___riscv_vwsubu_wv_u16m4_m(vbool4_t mask,vuint16m4_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u16m4_m(mask,op1,op2,31); +} + + +vuint16m8_t test___riscv_vwsubu_wv_u16m8_m(vbool2_t mask,vuint16m8_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u16m8_m(mask,op1,op2,31); +} + + +vuint32mf2_t test___riscv_vwsubu_wv_u32mf2_m(vbool64_t mask,vuint32mf2_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u32mf2_m(mask,op1,op2,31); +} + + +vuint32m1_t test___riscv_vwsubu_wv_u32m1_m(vbool32_t mask,vuint32m1_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u32m1_m(mask,op1,op2,31); +} + + +vuint32m2_t test___riscv_vwsubu_wv_u32m2_m(vbool16_t mask,vuint32m2_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u32m2_m(mask,op1,op2,31); +} + + +vuint32m4_t test___riscv_vwsubu_wv_u32m4_m(vbool8_t mask,vuint32m4_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u32m4_m(mask,op1,op2,31); +} + + +vuint32m8_t test___riscv_vwsubu_wv_u32m8_m(vbool4_t mask,vuint32m8_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u32m8_m(mask,op1,op2,31); +} + + +vuint64m1_t test___riscv_vwsubu_wv_u64m1_m(vbool64_t mask,vuint64m1_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u64m1_m(mask,op1,op2,31); +} + + +vuint64m2_t test___riscv_vwsubu_wv_u64m2_m(vbool32_t mask,vuint64m2_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u64m2_m(mask,op1,op2,31); +} + + +vuint64m4_t test___riscv_vwsubu_wv_u64m4_m(vbool16_t mask,vuint64m4_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u64m4_m(mask,op1,op2,31); +} + + +vuint64m8_t test___riscv_vwsubu_wv_u64m8_m(vbool8_t mask,vuint64m8_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u64m8_m(mask,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wv_m-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wv_m-3.c new file mode 100644 index 00000000000..28d38a81aec --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wv_m-3.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwsubu_wv_u16mf4_m(vbool64_t mask,vuint16mf4_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u16mf4_m(mask,op1,op2,32); +} + + +vuint16mf2_t test___riscv_vwsubu_wv_u16mf2_m(vbool32_t mask,vuint16mf2_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u16mf2_m(mask,op1,op2,32); +} + + +vuint16m1_t test___riscv_vwsubu_wv_u16m1_m(vbool16_t mask,vuint16m1_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u16m1_m(mask,op1,op2,32); +} + + +vuint16m2_t test___riscv_vwsubu_wv_u16m2_m(vbool8_t mask,vuint16m2_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u16m2_m(mask,op1,op2,32); +} + + +vuint16m4_t test___riscv_vwsubu_wv_u16m4_m(vbool4_t mask,vuint16m4_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u16m4_m(mask,op1,op2,32); +} + + +vuint16m8_t test___riscv_vwsubu_wv_u16m8_m(vbool2_t mask,vuint16m8_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u16m8_m(mask,op1,op2,32); +} + + +vuint32mf2_t test___riscv_vwsubu_wv_u32mf2_m(vbool64_t mask,vuint32mf2_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u32mf2_m(mask,op1,op2,32); +} + + +vuint32m1_t test___riscv_vwsubu_wv_u32m1_m(vbool32_t mask,vuint32m1_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u32m1_m(mask,op1,op2,32); +} + + +vuint32m2_t test___riscv_vwsubu_wv_u32m2_m(vbool16_t mask,vuint32m2_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u32m2_m(mask,op1,op2,32); +} + + +vuint32m4_t test___riscv_vwsubu_wv_u32m4_m(vbool8_t mask,vuint32m4_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u32m4_m(mask,op1,op2,32); +} + + +vuint32m8_t test___riscv_vwsubu_wv_u32m8_m(vbool4_t mask,vuint32m8_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u32m8_m(mask,op1,op2,32); +} + + +vuint64m1_t test___riscv_vwsubu_wv_u64m1_m(vbool64_t mask,vuint64m1_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u64m1_m(mask,op1,op2,32); +} + + +vuint64m2_t test___riscv_vwsubu_wv_u64m2_m(vbool32_t mask,vuint64m2_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u64m2_m(mask,op1,op2,32); +} + + +vuint64m4_t test___riscv_vwsubu_wv_u64m4_m(vbool16_t mask,vuint64m4_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u64m4_m(mask,op1,op2,32); +} + + +vuint64m8_t test___riscv_vwsubu_wv_u64m8_m(vbool8_t mask,vuint64m8_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u64m8_m(mask,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wv_mu-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wv_mu-1.c new file mode 100644 index 00000000000..ad02613d4dc --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wv_mu-1.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwsubu_wv_u16mf4_mu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u16mf4_mu(mask,merge,op1,op2,vl); +} + + +vuint16mf2_t test___riscv_vwsubu_wv_u16mf2_mu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u16mf2_mu(mask,merge,op1,op2,vl); +} + + +vuint16m1_t test___riscv_vwsubu_wv_u16m1_mu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u16m1_mu(mask,merge,op1,op2,vl); +} + + +vuint16m2_t test___riscv_vwsubu_wv_u16m2_mu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u16m2_mu(mask,merge,op1,op2,vl); +} + + +vuint16m4_t test___riscv_vwsubu_wv_u16m4_mu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u16m4_mu(mask,merge,op1,op2,vl); +} + + +vuint16m8_t test___riscv_vwsubu_wv_u16m8_mu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u16m8_mu(mask,merge,op1,op2,vl); +} + + +vuint32mf2_t test___riscv_vwsubu_wv_u32mf2_mu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u32mf2_mu(mask,merge,op1,op2,vl); +} + + +vuint32m1_t test___riscv_vwsubu_wv_u32m1_mu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u32m1_mu(mask,merge,op1,op2,vl); +} + + +vuint32m2_t test___riscv_vwsubu_wv_u32m2_mu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u32m2_mu(mask,merge,op1,op2,vl); +} + + +vuint32m4_t test___riscv_vwsubu_wv_u32m4_mu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u32m4_mu(mask,merge,op1,op2,vl); +} + + +vuint32m8_t test___riscv_vwsubu_wv_u32m8_mu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u32m8_mu(mask,merge,op1,op2,vl); +} + + +vuint64m1_t test___riscv_vwsubu_wv_u64m1_mu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u64m1_mu(mask,merge,op1,op2,vl); +} + + +vuint64m2_t test___riscv_vwsubu_wv_u64m2_mu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u64m2_mu(mask,merge,op1,op2,vl); +} + + +vuint64m4_t test___riscv_vwsubu_wv_u64m4_mu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u64m4_mu(mask,merge,op1,op2,vl); +} + + +vuint64m8_t test___riscv_vwsubu_wv_u64m8_mu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u64m8_mu(mask,merge,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wv_mu-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wv_mu-2.c new file mode 100644 index 00000000000..f63b57d5d23 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wv_mu-2.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwsubu_wv_u16mf4_mu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u16mf4_mu(mask,merge,op1,op2,31); +} + + +vuint16mf2_t test___riscv_vwsubu_wv_u16mf2_mu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u16mf2_mu(mask,merge,op1,op2,31); +} + + +vuint16m1_t test___riscv_vwsubu_wv_u16m1_mu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u16m1_mu(mask,merge,op1,op2,31); +} + + +vuint16m2_t test___riscv_vwsubu_wv_u16m2_mu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u16m2_mu(mask,merge,op1,op2,31); +} + + +vuint16m4_t test___riscv_vwsubu_wv_u16m4_mu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u16m4_mu(mask,merge,op1,op2,31); +} + + +vuint16m8_t test___riscv_vwsubu_wv_u16m8_mu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u16m8_mu(mask,merge,op1,op2,31); +} + + +vuint32mf2_t test___riscv_vwsubu_wv_u32mf2_mu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u32mf2_mu(mask,merge,op1,op2,31); +} + + +vuint32m1_t test___riscv_vwsubu_wv_u32m1_mu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u32m1_mu(mask,merge,op1,op2,31); +} + + +vuint32m2_t test___riscv_vwsubu_wv_u32m2_mu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u32m2_mu(mask,merge,op1,op2,31); +} + + +vuint32m4_t test___riscv_vwsubu_wv_u32m4_mu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u32m4_mu(mask,merge,op1,op2,31); +} + + +vuint32m8_t test___riscv_vwsubu_wv_u32m8_mu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u32m8_mu(mask,merge,op1,op2,31); +} + + +vuint64m1_t test___riscv_vwsubu_wv_u64m1_mu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u64m1_mu(mask,merge,op1,op2,31); +} + + +vuint64m2_t test___riscv_vwsubu_wv_u64m2_mu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u64m2_mu(mask,merge,op1,op2,31); +} + + +vuint64m4_t test___riscv_vwsubu_wv_u64m4_mu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u64m4_mu(mask,merge,op1,op2,31); +} + + +vuint64m8_t test___riscv_vwsubu_wv_u64m8_mu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u64m8_mu(mask,merge,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wv_mu-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wv_mu-3.c new file mode 100644 index 00000000000..4c62e72141b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wv_mu-3.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwsubu_wv_u16mf4_mu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u16mf4_mu(mask,merge,op1,op2,32); +} + + +vuint16mf2_t test___riscv_vwsubu_wv_u16mf2_mu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u16mf2_mu(mask,merge,op1,op2,32); +} + + +vuint16m1_t test___riscv_vwsubu_wv_u16m1_mu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u16m1_mu(mask,merge,op1,op2,32); +} + + +vuint16m2_t test___riscv_vwsubu_wv_u16m2_mu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u16m2_mu(mask,merge,op1,op2,32); +} + + +vuint16m4_t test___riscv_vwsubu_wv_u16m4_mu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u16m4_mu(mask,merge,op1,op2,32); +} + + +vuint16m8_t test___riscv_vwsubu_wv_u16m8_mu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u16m8_mu(mask,merge,op1,op2,32); +} + + +vuint32mf2_t test___riscv_vwsubu_wv_u32mf2_mu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u32mf2_mu(mask,merge,op1,op2,32); +} + + +vuint32m1_t test___riscv_vwsubu_wv_u32m1_mu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u32m1_mu(mask,merge,op1,op2,32); +} + + +vuint32m2_t test___riscv_vwsubu_wv_u32m2_mu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u32m2_mu(mask,merge,op1,op2,32); +} + + +vuint32m4_t test___riscv_vwsubu_wv_u32m4_mu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u32m4_mu(mask,merge,op1,op2,32); +} + + +vuint32m8_t test___riscv_vwsubu_wv_u32m8_mu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u32m8_mu(mask,merge,op1,op2,32); +} + + +vuint64m1_t test___riscv_vwsubu_wv_u64m1_mu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u64m1_mu(mask,merge,op1,op2,32); +} + + +vuint64m2_t test___riscv_vwsubu_wv_u64m2_mu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u64m2_mu(mask,merge,op1,op2,32); +} + + +vuint64m4_t test___riscv_vwsubu_wv_u64m4_mu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u64m4_mu(mask,merge,op1,op2,32); +} + + +vuint64m8_t test___riscv_vwsubu_wv_u64m8_mu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u64m8_mu(mask,merge,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wv_tu-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wv_tu-1.c new file mode 100644 index 00000000000..5bd36f109dc --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wv_tu-1.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwsubu_wv_u16mf4_tu(vuint16mf4_t merge,vuint16mf4_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u16mf4_tu(merge,op1,op2,vl); +} + + +vuint16mf2_t test___riscv_vwsubu_wv_u16mf2_tu(vuint16mf2_t merge,vuint16mf2_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u16mf2_tu(merge,op1,op2,vl); +} + + +vuint16m1_t test___riscv_vwsubu_wv_u16m1_tu(vuint16m1_t merge,vuint16m1_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u16m1_tu(merge,op1,op2,vl); +} + + +vuint16m2_t test___riscv_vwsubu_wv_u16m2_tu(vuint16m2_t merge,vuint16m2_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u16m2_tu(merge,op1,op2,vl); +} + + +vuint16m4_t test___riscv_vwsubu_wv_u16m4_tu(vuint16m4_t merge,vuint16m4_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u16m4_tu(merge,op1,op2,vl); +} + + +vuint16m8_t test___riscv_vwsubu_wv_u16m8_tu(vuint16m8_t merge,vuint16m8_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u16m8_tu(merge,op1,op2,vl); +} + + +vuint32mf2_t test___riscv_vwsubu_wv_u32mf2_tu(vuint32mf2_t merge,vuint32mf2_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u32mf2_tu(merge,op1,op2,vl); +} + + +vuint32m1_t test___riscv_vwsubu_wv_u32m1_tu(vuint32m1_t merge,vuint32m1_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u32m1_tu(merge,op1,op2,vl); +} + + +vuint32m2_t test___riscv_vwsubu_wv_u32m2_tu(vuint32m2_t merge,vuint32m2_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u32m2_tu(merge,op1,op2,vl); +} + + +vuint32m4_t test___riscv_vwsubu_wv_u32m4_tu(vuint32m4_t merge,vuint32m4_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u32m4_tu(merge,op1,op2,vl); +} + + +vuint32m8_t test___riscv_vwsubu_wv_u32m8_tu(vuint32m8_t merge,vuint32m8_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u32m8_tu(merge,op1,op2,vl); +} + + +vuint64m1_t test___riscv_vwsubu_wv_u64m1_tu(vuint64m1_t merge,vuint64m1_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u64m1_tu(merge,op1,op2,vl); +} + + +vuint64m2_t test___riscv_vwsubu_wv_u64m2_tu(vuint64m2_t merge,vuint64m2_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u64m2_tu(merge,op1,op2,vl); +} + + +vuint64m4_t test___riscv_vwsubu_wv_u64m4_tu(vuint64m4_t merge,vuint64m4_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u64m4_tu(merge,op1,op2,vl); +} + + +vuint64m8_t test___riscv_vwsubu_wv_u64m8_tu(vuint64m8_t merge,vuint64m8_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u64m8_tu(merge,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wv_tu-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wv_tu-2.c new file mode 100644 index 00000000000..6b19c2784f7 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wv_tu-2.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwsubu_wv_u16mf4_tu(vuint16mf4_t merge,vuint16mf4_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u16mf4_tu(merge,op1,op2,31); +} + + +vuint16mf2_t test___riscv_vwsubu_wv_u16mf2_tu(vuint16mf2_t merge,vuint16mf2_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u16mf2_tu(merge,op1,op2,31); +} + + +vuint16m1_t test___riscv_vwsubu_wv_u16m1_tu(vuint16m1_t merge,vuint16m1_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u16m1_tu(merge,op1,op2,31); +} + + +vuint16m2_t test___riscv_vwsubu_wv_u16m2_tu(vuint16m2_t merge,vuint16m2_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u16m2_tu(merge,op1,op2,31); +} + + +vuint16m4_t test___riscv_vwsubu_wv_u16m4_tu(vuint16m4_t merge,vuint16m4_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u16m4_tu(merge,op1,op2,31); +} + + +vuint16m8_t test___riscv_vwsubu_wv_u16m8_tu(vuint16m8_t merge,vuint16m8_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u16m8_tu(merge,op1,op2,31); +} + + +vuint32mf2_t test___riscv_vwsubu_wv_u32mf2_tu(vuint32mf2_t merge,vuint32mf2_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u32mf2_tu(merge,op1,op2,31); +} + + +vuint32m1_t test___riscv_vwsubu_wv_u32m1_tu(vuint32m1_t merge,vuint32m1_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u32m1_tu(merge,op1,op2,31); +} + + +vuint32m2_t test___riscv_vwsubu_wv_u32m2_tu(vuint32m2_t merge,vuint32m2_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u32m2_tu(merge,op1,op2,31); +} + + +vuint32m4_t test___riscv_vwsubu_wv_u32m4_tu(vuint32m4_t merge,vuint32m4_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u32m4_tu(merge,op1,op2,31); +} + + +vuint32m8_t test___riscv_vwsubu_wv_u32m8_tu(vuint32m8_t merge,vuint32m8_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u32m8_tu(merge,op1,op2,31); +} + + +vuint64m1_t test___riscv_vwsubu_wv_u64m1_tu(vuint64m1_t merge,vuint64m1_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u64m1_tu(merge,op1,op2,31); +} + + +vuint64m2_t test___riscv_vwsubu_wv_u64m2_tu(vuint64m2_t merge,vuint64m2_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u64m2_tu(merge,op1,op2,31); +} + + +vuint64m4_t test___riscv_vwsubu_wv_u64m4_tu(vuint64m4_t merge,vuint64m4_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u64m4_tu(merge,op1,op2,31); +} + + +vuint64m8_t test___riscv_vwsubu_wv_u64m8_tu(vuint64m8_t merge,vuint64m8_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u64m8_tu(merge,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wv_tu-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wv_tu-3.c new file mode 100644 index 00000000000..0c2378384e7 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wv_tu-3.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwsubu_wv_u16mf4_tu(vuint16mf4_t merge,vuint16mf4_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u16mf4_tu(merge,op1,op2,32); +} + + +vuint16mf2_t test___riscv_vwsubu_wv_u16mf2_tu(vuint16mf2_t merge,vuint16mf2_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u16mf2_tu(merge,op1,op2,32); +} + + +vuint16m1_t test___riscv_vwsubu_wv_u16m1_tu(vuint16m1_t merge,vuint16m1_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u16m1_tu(merge,op1,op2,32); +} + + +vuint16m2_t test___riscv_vwsubu_wv_u16m2_tu(vuint16m2_t merge,vuint16m2_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u16m2_tu(merge,op1,op2,32); +} + + +vuint16m4_t test___riscv_vwsubu_wv_u16m4_tu(vuint16m4_t merge,vuint16m4_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u16m4_tu(merge,op1,op2,32); +} + + +vuint16m8_t test___riscv_vwsubu_wv_u16m8_tu(vuint16m8_t merge,vuint16m8_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u16m8_tu(merge,op1,op2,32); +} + + +vuint32mf2_t test___riscv_vwsubu_wv_u32mf2_tu(vuint32mf2_t merge,vuint32mf2_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u32mf2_tu(merge,op1,op2,32); +} + + +vuint32m1_t test___riscv_vwsubu_wv_u32m1_tu(vuint32m1_t merge,vuint32m1_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u32m1_tu(merge,op1,op2,32); +} + + +vuint32m2_t test___riscv_vwsubu_wv_u32m2_tu(vuint32m2_t merge,vuint32m2_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u32m2_tu(merge,op1,op2,32); +} + + +vuint32m4_t test___riscv_vwsubu_wv_u32m4_tu(vuint32m4_t merge,vuint32m4_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u32m4_tu(merge,op1,op2,32); +} + + +vuint32m8_t test___riscv_vwsubu_wv_u32m8_tu(vuint32m8_t merge,vuint32m8_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u32m8_tu(merge,op1,op2,32); +} + + +vuint64m1_t test___riscv_vwsubu_wv_u64m1_tu(vuint64m1_t merge,vuint64m1_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u64m1_tu(merge,op1,op2,32); +} + + +vuint64m2_t test___riscv_vwsubu_wv_u64m2_tu(vuint64m2_t merge,vuint64m2_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u64m2_tu(merge,op1,op2,32); +} + + +vuint64m4_t test___riscv_vwsubu_wv_u64m4_tu(vuint64m4_t merge,vuint64m4_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u64m4_tu(merge,op1,op2,32); +} + + +vuint64m8_t test___riscv_vwsubu_wv_u64m8_tu(vuint64m8_t merge,vuint64m8_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u64m8_tu(merge,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wv_tum-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wv_tum-1.c new file mode 100644 index 00000000000..6645e70aac6 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wv_tum-1.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwsubu_wv_u16mf4_tum(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u16mf4_tum(mask,merge,op1,op2,vl); +} + + +vuint16mf2_t test___riscv_vwsubu_wv_u16mf2_tum(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u16mf2_tum(mask,merge,op1,op2,vl); +} + + +vuint16m1_t test___riscv_vwsubu_wv_u16m1_tum(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u16m1_tum(mask,merge,op1,op2,vl); +} + + +vuint16m2_t test___riscv_vwsubu_wv_u16m2_tum(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u16m2_tum(mask,merge,op1,op2,vl); +} + + +vuint16m4_t test___riscv_vwsubu_wv_u16m4_tum(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u16m4_tum(mask,merge,op1,op2,vl); +} + + +vuint16m8_t test___riscv_vwsubu_wv_u16m8_tum(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u16m8_tum(mask,merge,op1,op2,vl); +} + + +vuint32mf2_t test___riscv_vwsubu_wv_u32mf2_tum(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u32mf2_tum(mask,merge,op1,op2,vl); +} + + +vuint32m1_t test___riscv_vwsubu_wv_u32m1_tum(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u32m1_tum(mask,merge,op1,op2,vl); +} + + +vuint32m2_t test___riscv_vwsubu_wv_u32m2_tum(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u32m2_tum(mask,merge,op1,op2,vl); +} + + +vuint32m4_t test___riscv_vwsubu_wv_u32m4_tum(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u32m4_tum(mask,merge,op1,op2,vl); +} + + +vuint32m8_t test___riscv_vwsubu_wv_u32m8_tum(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u32m8_tum(mask,merge,op1,op2,vl); +} + + +vuint64m1_t test___riscv_vwsubu_wv_u64m1_tum(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u64m1_tum(mask,merge,op1,op2,vl); +} + + +vuint64m2_t test___riscv_vwsubu_wv_u64m2_tum(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u64m2_tum(mask,merge,op1,op2,vl); +} + + +vuint64m4_t test___riscv_vwsubu_wv_u64m4_tum(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u64m4_tum(mask,merge,op1,op2,vl); +} + + +vuint64m8_t test___riscv_vwsubu_wv_u64m8_tum(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u64m8_tum(mask,merge,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wv_tum-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wv_tum-2.c new file mode 100644 index 00000000000..2f39fda0e31 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wv_tum-2.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwsubu_wv_u16mf4_tum(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u16mf4_tum(mask,merge,op1,op2,31); +} + + +vuint16mf2_t test___riscv_vwsubu_wv_u16mf2_tum(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u16mf2_tum(mask,merge,op1,op2,31); +} + + +vuint16m1_t test___riscv_vwsubu_wv_u16m1_tum(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u16m1_tum(mask,merge,op1,op2,31); +} + + +vuint16m2_t test___riscv_vwsubu_wv_u16m2_tum(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u16m2_tum(mask,merge,op1,op2,31); +} + + +vuint16m4_t test___riscv_vwsubu_wv_u16m4_tum(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u16m4_tum(mask,merge,op1,op2,31); +} + + +vuint16m8_t test___riscv_vwsubu_wv_u16m8_tum(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u16m8_tum(mask,merge,op1,op2,31); +} + + +vuint32mf2_t test___riscv_vwsubu_wv_u32mf2_tum(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u32mf2_tum(mask,merge,op1,op2,31); +} + + +vuint32m1_t test___riscv_vwsubu_wv_u32m1_tum(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u32m1_tum(mask,merge,op1,op2,31); +} + + +vuint32m2_t test___riscv_vwsubu_wv_u32m2_tum(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u32m2_tum(mask,merge,op1,op2,31); +} + + +vuint32m4_t test___riscv_vwsubu_wv_u32m4_tum(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u32m4_tum(mask,merge,op1,op2,31); +} + + +vuint32m8_t test___riscv_vwsubu_wv_u32m8_tum(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u32m8_tum(mask,merge,op1,op2,31); +} + + +vuint64m1_t test___riscv_vwsubu_wv_u64m1_tum(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u64m1_tum(mask,merge,op1,op2,31); +} + + +vuint64m2_t test___riscv_vwsubu_wv_u64m2_tum(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u64m2_tum(mask,merge,op1,op2,31); +} + + +vuint64m4_t test___riscv_vwsubu_wv_u64m4_tum(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u64m4_tum(mask,merge,op1,op2,31); +} + + +vuint64m8_t test___riscv_vwsubu_wv_u64m8_tum(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u64m8_tum(mask,merge,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wv_tum-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wv_tum-3.c new file mode 100644 index 00000000000..5cdec869dd4 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wv_tum-3.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwsubu_wv_u16mf4_tum(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u16mf4_tum(mask,merge,op1,op2,32); +} + + +vuint16mf2_t test___riscv_vwsubu_wv_u16mf2_tum(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u16mf2_tum(mask,merge,op1,op2,32); +} + + +vuint16m1_t test___riscv_vwsubu_wv_u16m1_tum(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u16m1_tum(mask,merge,op1,op2,32); +} + + +vuint16m2_t test___riscv_vwsubu_wv_u16m2_tum(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u16m2_tum(mask,merge,op1,op2,32); +} + + +vuint16m4_t test___riscv_vwsubu_wv_u16m4_tum(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u16m4_tum(mask,merge,op1,op2,32); +} + + +vuint16m8_t test___riscv_vwsubu_wv_u16m8_tum(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u16m8_tum(mask,merge,op1,op2,32); +} + + +vuint32mf2_t test___riscv_vwsubu_wv_u32mf2_tum(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u32mf2_tum(mask,merge,op1,op2,32); +} + + +vuint32m1_t test___riscv_vwsubu_wv_u32m1_tum(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u32m1_tum(mask,merge,op1,op2,32); +} + + +vuint32m2_t test___riscv_vwsubu_wv_u32m2_tum(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u32m2_tum(mask,merge,op1,op2,32); +} + + +vuint32m4_t test___riscv_vwsubu_wv_u32m4_tum(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u32m4_tum(mask,merge,op1,op2,32); +} + + +vuint32m8_t test___riscv_vwsubu_wv_u32m8_tum(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u32m8_tum(mask,merge,op1,op2,32); +} + + +vuint64m1_t test___riscv_vwsubu_wv_u64m1_tum(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u64m1_tum(mask,merge,op1,op2,32); +} + + +vuint64m2_t test___riscv_vwsubu_wv_u64m2_tum(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u64m2_tum(mask,merge,op1,op2,32); +} + + +vuint64m4_t test___riscv_vwsubu_wv_u64m4_tum(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u64m4_tum(mask,merge,op1,op2,32); +} + + +vuint64m8_t test___riscv_vwsubu_wv_u64m8_tum(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u64m8_tum(mask,merge,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wv_tumu-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wv_tumu-1.c new file mode 100644 index 00000000000..69851b0a48a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wv_tumu-1.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwsubu_wv_u16mf4_tumu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u16mf4_tumu(mask,merge,op1,op2,vl); +} + + +vuint16mf2_t test___riscv_vwsubu_wv_u16mf2_tumu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u16mf2_tumu(mask,merge,op1,op2,vl); +} + + +vuint16m1_t test___riscv_vwsubu_wv_u16m1_tumu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u16m1_tumu(mask,merge,op1,op2,vl); +} + + +vuint16m2_t test___riscv_vwsubu_wv_u16m2_tumu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u16m2_tumu(mask,merge,op1,op2,vl); +} + + +vuint16m4_t test___riscv_vwsubu_wv_u16m4_tumu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u16m4_tumu(mask,merge,op1,op2,vl); +} + + +vuint16m8_t test___riscv_vwsubu_wv_u16m8_tumu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u16m8_tumu(mask,merge,op1,op2,vl); +} + + +vuint32mf2_t test___riscv_vwsubu_wv_u32mf2_tumu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u32mf2_tumu(mask,merge,op1,op2,vl); +} + + +vuint32m1_t test___riscv_vwsubu_wv_u32m1_tumu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u32m1_tumu(mask,merge,op1,op2,vl); +} + + +vuint32m2_t test___riscv_vwsubu_wv_u32m2_tumu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u32m2_tumu(mask,merge,op1,op2,vl); +} + + +vuint32m4_t test___riscv_vwsubu_wv_u32m4_tumu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u32m4_tumu(mask,merge,op1,op2,vl); +} + + +vuint32m8_t test___riscv_vwsubu_wv_u32m8_tumu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u32m8_tumu(mask,merge,op1,op2,vl); +} + + +vuint64m1_t test___riscv_vwsubu_wv_u64m1_tumu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u64m1_tumu(mask,merge,op1,op2,vl); +} + + +vuint64m2_t test___riscv_vwsubu_wv_u64m2_tumu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u64m2_tumu(mask,merge,op1,op2,vl); +} + + +vuint64m4_t test___riscv_vwsubu_wv_u64m4_tumu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u64m4_tumu(mask,merge,op1,op2,vl); +} + + +vuint64m8_t test___riscv_vwsubu_wv_u64m8_tumu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u64m8_tumu(mask,merge,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wv_tumu-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wv_tumu-2.c new file mode 100644 index 00000000000..285a84c1ad7 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wv_tumu-2.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwsubu_wv_u16mf4_tumu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u16mf4_tumu(mask,merge,op1,op2,31); +} + + +vuint16mf2_t test___riscv_vwsubu_wv_u16mf2_tumu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u16mf2_tumu(mask,merge,op1,op2,31); +} + + +vuint16m1_t test___riscv_vwsubu_wv_u16m1_tumu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u16m1_tumu(mask,merge,op1,op2,31); +} + + +vuint16m2_t test___riscv_vwsubu_wv_u16m2_tumu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u16m2_tumu(mask,merge,op1,op2,31); +} + + +vuint16m4_t test___riscv_vwsubu_wv_u16m4_tumu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u16m4_tumu(mask,merge,op1,op2,31); +} + + +vuint16m8_t test___riscv_vwsubu_wv_u16m8_tumu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u16m8_tumu(mask,merge,op1,op2,31); +} + + +vuint32mf2_t test___riscv_vwsubu_wv_u32mf2_tumu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u32mf2_tumu(mask,merge,op1,op2,31); +} + + +vuint32m1_t test___riscv_vwsubu_wv_u32m1_tumu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u32m1_tumu(mask,merge,op1,op2,31); +} + + +vuint32m2_t test___riscv_vwsubu_wv_u32m2_tumu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u32m2_tumu(mask,merge,op1,op2,31); +} + + +vuint32m4_t test___riscv_vwsubu_wv_u32m4_tumu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u32m4_tumu(mask,merge,op1,op2,31); +} + + +vuint32m8_t test___riscv_vwsubu_wv_u32m8_tumu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u32m8_tumu(mask,merge,op1,op2,31); +} + + +vuint64m1_t test___riscv_vwsubu_wv_u64m1_tumu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u64m1_tumu(mask,merge,op1,op2,31); +} + + +vuint64m2_t test___riscv_vwsubu_wv_u64m2_tumu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u64m2_tumu(mask,merge,op1,op2,31); +} + + +vuint64m4_t test___riscv_vwsubu_wv_u64m4_tumu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u64m4_tumu(mask,merge,op1,op2,31); +} + + +vuint64m8_t test___riscv_vwsubu_wv_u64m8_tumu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u64m8_tumu(mask,merge,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wv_tumu-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wv_tumu-3.c new file mode 100644 index 00000000000..1c61045e3c6 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wv_tumu-3.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwsubu_wv_u16mf4_tumu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u16mf4_tumu(mask,merge,op1,op2,32); +} + + +vuint16mf2_t test___riscv_vwsubu_wv_u16mf2_tumu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u16mf2_tumu(mask,merge,op1,op2,32); +} + + +vuint16m1_t test___riscv_vwsubu_wv_u16m1_tumu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u16m1_tumu(mask,merge,op1,op2,32); +} + + +vuint16m2_t test___riscv_vwsubu_wv_u16m2_tumu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u16m2_tumu(mask,merge,op1,op2,32); +} + + +vuint16m4_t test___riscv_vwsubu_wv_u16m4_tumu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u16m4_tumu(mask,merge,op1,op2,32); +} + + +vuint16m8_t test___riscv_vwsubu_wv_u16m8_tumu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u16m8_tumu(mask,merge,op1,op2,32); +} + + +vuint32mf2_t test___riscv_vwsubu_wv_u32mf2_tumu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u32mf2_tumu(mask,merge,op1,op2,32); +} + + +vuint32m1_t test___riscv_vwsubu_wv_u32m1_tumu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u32m1_tumu(mask,merge,op1,op2,32); +} + + +vuint32m2_t test___riscv_vwsubu_wv_u32m2_tumu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u32m2_tumu(mask,merge,op1,op2,32); +} + + +vuint32m4_t test___riscv_vwsubu_wv_u32m4_tumu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u32m4_tumu(mask,merge,op1,op2,32); +} + + +vuint32m8_t test___riscv_vwsubu_wv_u32m8_tumu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u32m8_tumu(mask,merge,op1,op2,32); +} + + +vuint64m1_t test___riscv_vwsubu_wv_u64m1_tumu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u64m1_tumu(mask,merge,op1,op2,32); +} + + +vuint64m2_t test___riscv_vwsubu_wv_u64m2_tumu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u64m2_tumu(mask,merge,op1,op2,32); +} + + +vuint64m4_t test___riscv_vwsubu_wv_u64m4_tumu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u64m4_tumu(mask,merge,op1,op2,32); +} + + +vuint64m8_t test___riscv_vwsubu_wv_u64m8_tumu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vwsubu_wv_u64m8_tumu(mask,merge,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */