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[58.60.1.22]) by bizesmtp.qq.com (ESMTP) with id ; Mon, 06 Feb 2023 20:08:43 +0800 (CST) X-QQ-SSF: 01400000000000E0L000000A0000000 X-QQ-FEAT: JHEaxJLXE2ERxBwzlg5V7aiT3gv6trk7yjXubtEB3tXzS2DAcVJ+17/hNG7Zg kc6hYAAr2xkupyh7TSFLSXD2wBH/Ylbzg629WY3LH+E7no7uMz0t0VOmQsfr7tKfWW0MZ7B O8VTFjBo2Po3kX6nP43MTB16s3bUapug52S4FPmJROOX5E2ZBPEHu1m0tAv7y8SAjzCvKYX d6YyP7S4Lapl7IZmHRZzpXjYTauba9JynkDzXHoBYBb3TMLY+Tpi/Gob3dbaLUeyhXDnOae 658zdYUjB4RXHub9EnbICUr24/n39AiN7/MWi0M+uDlPPqO87Cgj49n3IEpmDtw5bFxg7zv k8zM8hAB08zzmaeiGuctmc/8RieKY7bBVsskItJ8ent6LDZoZhfl4ijV5bANCfM1ksv2NZ2 X-QQ-GoodBg: 2 From: juzhe.zhong@rivai.ai To: gcc-patches@gcc.gnu.org Cc: kito.cheng@gmail.com, Ju-Zhe Zhong Subject: [PATCH] RISC-V: Add vmulhsu.vx C API tests Date: Mon, 6 Feb 2023 20:08:42 +0800 Message-Id: <20230206120842.49589-1-juzhe.zhong@rivai.ai> X-Mailer: git-send-email 2.36.1 MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:rivai.ai:qybglogicsvr:qybglogicsvr7 X-Spam-Status: No, score=-10.9 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, KAM_SHORT, RCVD_IN_BARRACUDACENTRAL, RCVD_IN_DNSWL_NONE, SPF_HELO_PASS, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" From: Ju-Zhe Zhong gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/vmulhsu_vx_m_rv32-1.c: New test. * gcc.target/riscv/rvv/base/vmulhsu_vx_m_rv32-2.c: New test. * gcc.target/riscv/rvv/base/vmulhsu_vx_m_rv32-3.c: New test. * gcc.target/riscv/rvv/base/vmulhsu_vx_m_rv64-1.c: New test. * gcc.target/riscv/rvv/base/vmulhsu_vx_m_rv64-2.c: New test. * gcc.target/riscv/rvv/base/vmulhsu_vx_m_rv64-3.c: New test. * gcc.target/riscv/rvv/base/vmulhsu_vx_mu_rv32-1.c: New test. * gcc.target/riscv/rvv/base/vmulhsu_vx_mu_rv32-2.c: New test. * gcc.target/riscv/rvv/base/vmulhsu_vx_mu_rv32-3.c: New test. * gcc.target/riscv/rvv/base/vmulhsu_vx_mu_rv64-1.c: New test. * gcc.target/riscv/rvv/base/vmulhsu_vx_mu_rv64-2.c: New test. * gcc.target/riscv/rvv/base/vmulhsu_vx_mu_rv64-3.c: New test. * gcc.target/riscv/rvv/base/vmulhsu_vx_rv32-1.c: New test. * gcc.target/riscv/rvv/base/vmulhsu_vx_rv32-2.c: New test. * gcc.target/riscv/rvv/base/vmulhsu_vx_rv32-3.c: New test. * gcc.target/riscv/rvv/base/vmulhsu_vx_rv64-1.c: New test. * gcc.target/riscv/rvv/base/vmulhsu_vx_rv64-2.c: New test. * gcc.target/riscv/rvv/base/vmulhsu_vx_rv64-3.c: New test. * gcc.target/riscv/rvv/base/vmulhsu_vx_tu_rv32-1.c: New test. * gcc.target/riscv/rvv/base/vmulhsu_vx_tu_rv32-2.c: New test. * gcc.target/riscv/rvv/base/vmulhsu_vx_tu_rv32-3.c: New test. * gcc.target/riscv/rvv/base/vmulhsu_vx_tu_rv64-1.c: New test. * gcc.target/riscv/rvv/base/vmulhsu_vx_tu_rv64-2.c: New test. * gcc.target/riscv/rvv/base/vmulhsu_vx_tu_rv64-3.c: New test. * gcc.target/riscv/rvv/base/vmulhsu_vx_tum_rv32-1.c: New test. * gcc.target/riscv/rvv/base/vmulhsu_vx_tum_rv32-2.c: New test. * gcc.target/riscv/rvv/base/vmulhsu_vx_tum_rv32-3.c: New test. * gcc.target/riscv/rvv/base/vmulhsu_vx_tum_rv64-1.c: New test. * gcc.target/riscv/rvv/base/vmulhsu_vx_tum_rv64-2.c: New test. * gcc.target/riscv/rvv/base/vmulhsu_vx_tum_rv64-3.c: New test. * gcc.target/riscv/rvv/base/vmulhsu_vx_tumu_rv32-1.c: New test. * gcc.target/riscv/rvv/base/vmulhsu_vx_tumu_rv32-2.c: New test. * gcc.target/riscv/rvv/base/vmulhsu_vx_tumu_rv32-3.c: New test. * gcc.target/riscv/rvv/base/vmulhsu_vx_tumu_rv64-1.c: New test. * gcc.target/riscv/rvv/base/vmulhsu_vx_tumu_rv64-2.c: New test. * gcc.target/riscv/rvv/base/vmulhsu_vx_tumu_rv64-3.c: New test. --- .../riscv/rvv/base/vmulhsu_vx_m_rv32-1.c | 157 +++++++++++++++++ .../riscv/rvv/base/vmulhsu_vx_m_rv32-2.c | 157 +++++++++++++++++ .../riscv/rvv/base/vmulhsu_vx_m_rv32-3.c | 157 +++++++++++++++++ .../riscv/rvv/base/vmulhsu_vx_m_rv64-1.c | 160 ++++++++++++++++++ .../riscv/rvv/base/vmulhsu_vx_m_rv64-2.c | 160 ++++++++++++++++++ .../riscv/rvv/base/vmulhsu_vx_m_rv64-3.c | 160 ++++++++++++++++++ .../riscv/rvv/base/vmulhsu_vx_mu_rv32-1.c | 157 +++++++++++++++++ .../riscv/rvv/base/vmulhsu_vx_mu_rv32-2.c | 157 +++++++++++++++++ .../riscv/rvv/base/vmulhsu_vx_mu_rv32-3.c | 157 +++++++++++++++++ .../riscv/rvv/base/vmulhsu_vx_mu_rv64-1.c | 160 ++++++++++++++++++ .../riscv/rvv/base/vmulhsu_vx_mu_rv64-2.c | 160 ++++++++++++++++++ .../riscv/rvv/base/vmulhsu_vx_mu_rv64-3.c | 160 ++++++++++++++++++ .../riscv/rvv/base/vmulhsu_vx_rv32-1.c | 157 +++++++++++++++++ .../riscv/rvv/base/vmulhsu_vx_rv32-2.c | 157 +++++++++++++++++ .../riscv/rvv/base/vmulhsu_vx_rv32-3.c | 157 +++++++++++++++++ .../riscv/rvv/base/vmulhsu_vx_rv64-1.c | 160 ++++++++++++++++++ .../riscv/rvv/base/vmulhsu_vx_rv64-2.c | 160 ++++++++++++++++++ .../riscv/rvv/base/vmulhsu_vx_rv64-3.c | 160 ++++++++++++++++++ .../riscv/rvv/base/vmulhsu_vx_tu_rv32-1.c | 157 +++++++++++++++++ .../riscv/rvv/base/vmulhsu_vx_tu_rv32-2.c | 157 +++++++++++++++++ .../riscv/rvv/base/vmulhsu_vx_tu_rv32-3.c | 157 +++++++++++++++++ .../riscv/rvv/base/vmulhsu_vx_tu_rv64-1.c | 160 ++++++++++++++++++ .../riscv/rvv/base/vmulhsu_vx_tu_rv64-2.c | 160 ++++++++++++++++++ .../riscv/rvv/base/vmulhsu_vx_tu_rv64-3.c | 160 ++++++++++++++++++ .../riscv/rvv/base/vmulhsu_vx_tum_rv32-1.c | 157 +++++++++++++++++ .../riscv/rvv/base/vmulhsu_vx_tum_rv32-2.c | 157 +++++++++++++++++ .../riscv/rvv/base/vmulhsu_vx_tum_rv32-3.c | 157 +++++++++++++++++ .../riscv/rvv/base/vmulhsu_vx_tum_rv64-1.c | 160 ++++++++++++++++++ .../riscv/rvv/base/vmulhsu_vx_tum_rv64-2.c | 160 ++++++++++++++++++ .../riscv/rvv/base/vmulhsu_vx_tum_rv64-3.c | 160 ++++++++++++++++++ .../riscv/rvv/base/vmulhsu_vx_tumu_rv32-1.c | 157 +++++++++++++++++ .../riscv/rvv/base/vmulhsu_vx_tumu_rv32-2.c | 157 +++++++++++++++++ .../riscv/rvv/base/vmulhsu_vx_tumu_rv32-3.c | 157 +++++++++++++++++ .../riscv/rvv/base/vmulhsu_vx_tumu_rv64-1.c | 160 ++++++++++++++++++ .../riscv/rvv/base/vmulhsu_vx_tumu_rv64-2.c | 160 ++++++++++++++++++ .../riscv/rvv/base/vmulhsu_vx_tumu_rv64-3.c | 160 ++++++++++++++++++ 36 files changed, 5706 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmulhsu_vx_m_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmulhsu_vx_m_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmulhsu_vx_m_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmulhsu_vx_m_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmulhsu_vx_m_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmulhsu_vx_m_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmulhsu_vx_mu_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmulhsu_vx_mu_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmulhsu_vx_mu_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmulhsu_vx_mu_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmulhsu_vx_mu_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmulhsu_vx_mu_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmulhsu_vx_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmulhsu_vx_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmulhsu_vx_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmulhsu_vx_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmulhsu_vx_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmulhsu_vx_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmulhsu_vx_tu_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmulhsu_vx_tu_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmulhsu_vx_tu_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmulhsu_vx_tu_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmulhsu_vx_tu_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmulhsu_vx_tu_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmulhsu_vx_tum_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmulhsu_vx_tum_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmulhsu_vx_tum_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmulhsu_vx_tum_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmulhsu_vx_tum_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmulhsu_vx_tum_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmulhsu_vx_tumu_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmulhsu_vx_tumu_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmulhsu_vx_tumu_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmulhsu_vx_tumu_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmulhsu_vx_tumu_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmulhsu_vx_tumu_rv64-3.c diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmulhsu_vx_m_rv32-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmulhsu_vx_m_rv32-1.c new file mode 100644 index 00000000000..64f06aa0d20 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmulhsu_vx_m_rv32-1.c @@ -0,0 +1,157 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vmulhsu_vx_i8mf8_m(vbool64_t mask,vint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i8mf8_m(mask,op1,op2,vl); +} + + +vint8mf4_t test___riscv_vmulhsu_vx_i8mf4_m(vbool32_t mask,vint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i8mf4_m(mask,op1,op2,vl); +} + + +vint8mf2_t test___riscv_vmulhsu_vx_i8mf2_m(vbool16_t mask,vint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i8mf2_m(mask,op1,op2,vl); +} + + +vint8m1_t test___riscv_vmulhsu_vx_i8m1_m(vbool8_t mask,vint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i8m1_m(mask,op1,op2,vl); +} + + +vint8m2_t test___riscv_vmulhsu_vx_i8m2_m(vbool4_t mask,vint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i8m2_m(mask,op1,op2,vl); +} + + +vint8m4_t test___riscv_vmulhsu_vx_i8m4_m(vbool2_t mask,vint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i8m4_m(mask,op1,op2,vl); +} + + +vint8m8_t test___riscv_vmulhsu_vx_i8m8_m(vbool1_t mask,vint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i8m8_m(mask,op1,op2,vl); +} + + +vint16mf4_t test___riscv_vmulhsu_vx_i16mf4_m(vbool64_t mask,vint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i16mf4_m(mask,op1,op2,vl); +} + + +vint16mf2_t test___riscv_vmulhsu_vx_i16mf2_m(vbool32_t mask,vint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i16mf2_m(mask,op1,op2,vl); +} + + +vint16m1_t test___riscv_vmulhsu_vx_i16m1_m(vbool16_t mask,vint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i16m1_m(mask,op1,op2,vl); +} + + +vint16m2_t test___riscv_vmulhsu_vx_i16m2_m(vbool8_t mask,vint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i16m2_m(mask,op1,op2,vl); +} + + +vint16m4_t test___riscv_vmulhsu_vx_i16m4_m(vbool4_t mask,vint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i16m4_m(mask,op1,op2,vl); +} + + +vint16m8_t test___riscv_vmulhsu_vx_i16m8_m(vbool2_t mask,vint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i16m8_m(mask,op1,op2,vl); +} + + +vint32mf2_t test___riscv_vmulhsu_vx_i32mf2_m(vbool64_t mask,vint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i32mf2_m(mask,op1,op2,vl); +} + + +vint32m1_t test___riscv_vmulhsu_vx_i32m1_m(vbool32_t mask,vint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i32m1_m(mask,op1,op2,vl); +} + + +vint32m2_t test___riscv_vmulhsu_vx_i32m2_m(vbool16_t mask,vint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i32m2_m(mask,op1,op2,vl); +} + + +vint32m4_t test___riscv_vmulhsu_vx_i32m4_m(vbool8_t mask,vint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i32m4_m(mask,op1,op2,vl); +} + + +vint32m8_t test___riscv_vmulhsu_vx_i32m8_m(vbool4_t mask,vint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i32m8_m(mask,op1,op2,vl); +} + + +vint64m1_t test___riscv_vmulhsu_vx_i64m1_m(vbool64_t mask,vint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i64m1_m(mask,op1,op2,vl); +} + + +vint64m2_t test___riscv_vmulhsu_vx_i64m2_m(vbool32_t mask,vint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i64m2_m(mask,op1,op2,vl); +} + + +vint64m4_t test___riscv_vmulhsu_vx_i64m4_m(vbool16_t mask,vint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i64m4_m(mask,op1,op2,vl); +} + + +vint64m8_t test___riscv_vmulhsu_vx_i64m8_m(vbool8_t mask,vint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i64m8_m(mask,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vmulhsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 4 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmulhsu_vx_m_rv32-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmulhsu_vx_m_rv32-2.c new file mode 100644 index 00000000000..99ec34cf2d9 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmulhsu_vx_m_rv32-2.c @@ -0,0 +1,157 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vmulhsu_vx_i8mf8_m(vbool64_t mask,vint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i8mf8_m(mask,op1,op2,31); +} + + +vint8mf4_t test___riscv_vmulhsu_vx_i8mf4_m(vbool32_t mask,vint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i8mf4_m(mask,op1,op2,31); +} + + +vint8mf2_t test___riscv_vmulhsu_vx_i8mf2_m(vbool16_t mask,vint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i8mf2_m(mask,op1,op2,31); +} + + +vint8m1_t test___riscv_vmulhsu_vx_i8m1_m(vbool8_t mask,vint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i8m1_m(mask,op1,op2,31); +} + + +vint8m2_t test___riscv_vmulhsu_vx_i8m2_m(vbool4_t mask,vint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i8m2_m(mask,op1,op2,31); +} + + +vint8m4_t test___riscv_vmulhsu_vx_i8m4_m(vbool2_t mask,vint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i8m4_m(mask,op1,op2,31); +} + + +vint8m8_t test___riscv_vmulhsu_vx_i8m8_m(vbool1_t mask,vint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i8m8_m(mask,op1,op2,31); +} + + +vint16mf4_t test___riscv_vmulhsu_vx_i16mf4_m(vbool64_t mask,vint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i16mf4_m(mask,op1,op2,31); +} + + +vint16mf2_t test___riscv_vmulhsu_vx_i16mf2_m(vbool32_t mask,vint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i16mf2_m(mask,op1,op2,31); +} + + +vint16m1_t test___riscv_vmulhsu_vx_i16m1_m(vbool16_t mask,vint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i16m1_m(mask,op1,op2,31); +} + + +vint16m2_t test___riscv_vmulhsu_vx_i16m2_m(vbool8_t mask,vint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i16m2_m(mask,op1,op2,31); +} + + +vint16m4_t test___riscv_vmulhsu_vx_i16m4_m(vbool4_t mask,vint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i16m4_m(mask,op1,op2,31); +} + + +vint16m8_t test___riscv_vmulhsu_vx_i16m8_m(vbool2_t mask,vint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i16m8_m(mask,op1,op2,31); +} + + +vint32mf2_t test___riscv_vmulhsu_vx_i32mf2_m(vbool64_t mask,vint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i32mf2_m(mask,op1,op2,31); +} + + +vint32m1_t test___riscv_vmulhsu_vx_i32m1_m(vbool32_t mask,vint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i32m1_m(mask,op1,op2,31); +} + + +vint32m2_t test___riscv_vmulhsu_vx_i32m2_m(vbool16_t mask,vint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i32m2_m(mask,op1,op2,31); +} + + +vint32m4_t test___riscv_vmulhsu_vx_i32m4_m(vbool8_t mask,vint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i32m4_m(mask,op1,op2,31); +} + + +vint32m8_t test___riscv_vmulhsu_vx_i32m8_m(vbool4_t mask,vint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i32m8_m(mask,op1,op2,31); +} + + +vint64m1_t test___riscv_vmulhsu_vx_i64m1_m(vbool64_t mask,vint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i64m1_m(mask,op1,op2,31); +} + + +vint64m2_t test___riscv_vmulhsu_vx_i64m2_m(vbool32_t mask,vint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i64m2_m(mask,op1,op2,31); +} + + +vint64m4_t test___riscv_vmulhsu_vx_i64m4_m(vbool16_t mask,vint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i64m4_m(mask,op1,op2,31); +} + + +vint64m8_t test___riscv_vmulhsu_vx_i64m8_m(vbool8_t mask,vint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i64m8_m(mask,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vmulhsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 4 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmulhsu_vx_m_rv32-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmulhsu_vx_m_rv32-3.c new file mode 100644 index 00000000000..a11e4855d82 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmulhsu_vx_m_rv32-3.c @@ -0,0 +1,157 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vmulhsu_vx_i8mf8_m(vbool64_t mask,vint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i8mf8_m(mask,op1,op2,32); +} + + +vint8mf4_t test___riscv_vmulhsu_vx_i8mf4_m(vbool32_t mask,vint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i8mf4_m(mask,op1,op2,32); +} + + +vint8mf2_t test___riscv_vmulhsu_vx_i8mf2_m(vbool16_t mask,vint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i8mf2_m(mask,op1,op2,32); +} + + +vint8m1_t test___riscv_vmulhsu_vx_i8m1_m(vbool8_t mask,vint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i8m1_m(mask,op1,op2,32); +} + + +vint8m2_t test___riscv_vmulhsu_vx_i8m2_m(vbool4_t mask,vint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i8m2_m(mask,op1,op2,32); +} + + +vint8m4_t test___riscv_vmulhsu_vx_i8m4_m(vbool2_t mask,vint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i8m4_m(mask,op1,op2,32); +} + + +vint8m8_t test___riscv_vmulhsu_vx_i8m8_m(vbool1_t mask,vint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i8m8_m(mask,op1,op2,32); +} + + +vint16mf4_t test___riscv_vmulhsu_vx_i16mf4_m(vbool64_t mask,vint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i16mf4_m(mask,op1,op2,32); +} + + +vint16mf2_t test___riscv_vmulhsu_vx_i16mf2_m(vbool32_t mask,vint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i16mf2_m(mask,op1,op2,32); +} + + +vint16m1_t test___riscv_vmulhsu_vx_i16m1_m(vbool16_t mask,vint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i16m1_m(mask,op1,op2,32); +} + + +vint16m2_t test___riscv_vmulhsu_vx_i16m2_m(vbool8_t mask,vint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i16m2_m(mask,op1,op2,32); +} + + +vint16m4_t test___riscv_vmulhsu_vx_i16m4_m(vbool4_t mask,vint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i16m4_m(mask,op1,op2,32); +} + + +vint16m8_t test___riscv_vmulhsu_vx_i16m8_m(vbool2_t mask,vint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i16m8_m(mask,op1,op2,32); +} + + +vint32mf2_t test___riscv_vmulhsu_vx_i32mf2_m(vbool64_t mask,vint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i32mf2_m(mask,op1,op2,32); +} + + +vint32m1_t test___riscv_vmulhsu_vx_i32m1_m(vbool32_t mask,vint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i32m1_m(mask,op1,op2,32); +} + + +vint32m2_t test___riscv_vmulhsu_vx_i32m2_m(vbool16_t mask,vint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i32m2_m(mask,op1,op2,32); +} + + +vint32m4_t test___riscv_vmulhsu_vx_i32m4_m(vbool8_t mask,vint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i32m4_m(mask,op1,op2,32); +} + + +vint32m8_t test___riscv_vmulhsu_vx_i32m8_m(vbool4_t mask,vint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i32m8_m(mask,op1,op2,32); +} + + +vint64m1_t test___riscv_vmulhsu_vx_i64m1_m(vbool64_t mask,vint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i64m1_m(mask,op1,op2,32); +} + + +vint64m2_t test___riscv_vmulhsu_vx_i64m2_m(vbool32_t mask,vint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i64m2_m(mask,op1,op2,32); +} + + +vint64m4_t test___riscv_vmulhsu_vx_i64m4_m(vbool16_t mask,vint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i64m4_m(mask,op1,op2,32); +} + + +vint64m8_t test___riscv_vmulhsu_vx_i64m8_m(vbool8_t mask,vint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i64m8_m(mask,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vmulhsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 4 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmulhsu_vx_m_rv64-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmulhsu_vx_m_rv64-1.c new file mode 100644 index 00000000000..16a01a38cd9 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmulhsu_vx_m_rv64-1.c @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vmulhsu_vx_i8mf8_m(vbool64_t mask,vint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i8mf8_m(mask,op1,op2,vl); +} + + +vint8mf4_t test___riscv_vmulhsu_vx_i8mf4_m(vbool32_t mask,vint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i8mf4_m(mask,op1,op2,vl); +} + + +vint8mf2_t test___riscv_vmulhsu_vx_i8mf2_m(vbool16_t mask,vint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i8mf2_m(mask,op1,op2,vl); +} + + +vint8m1_t test___riscv_vmulhsu_vx_i8m1_m(vbool8_t mask,vint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i8m1_m(mask,op1,op2,vl); +} + + +vint8m2_t test___riscv_vmulhsu_vx_i8m2_m(vbool4_t mask,vint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i8m2_m(mask,op1,op2,vl); +} + + +vint8m4_t test___riscv_vmulhsu_vx_i8m4_m(vbool2_t mask,vint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i8m4_m(mask,op1,op2,vl); +} + + +vint8m8_t test___riscv_vmulhsu_vx_i8m8_m(vbool1_t mask,vint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i8m8_m(mask,op1,op2,vl); +} + + +vint16mf4_t test___riscv_vmulhsu_vx_i16mf4_m(vbool64_t mask,vint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i16mf4_m(mask,op1,op2,vl); +} + + +vint16mf2_t test___riscv_vmulhsu_vx_i16mf2_m(vbool32_t mask,vint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i16mf2_m(mask,op1,op2,vl); +} + + +vint16m1_t test___riscv_vmulhsu_vx_i16m1_m(vbool16_t mask,vint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i16m1_m(mask,op1,op2,vl); +} + + +vint16m2_t test___riscv_vmulhsu_vx_i16m2_m(vbool8_t mask,vint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i16m2_m(mask,op1,op2,vl); +} + + +vint16m4_t test___riscv_vmulhsu_vx_i16m4_m(vbool4_t mask,vint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i16m4_m(mask,op1,op2,vl); +} + + +vint16m8_t test___riscv_vmulhsu_vx_i16m8_m(vbool2_t mask,vint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i16m8_m(mask,op1,op2,vl); +} + + +vint32mf2_t test___riscv_vmulhsu_vx_i32mf2_m(vbool64_t mask,vint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i32mf2_m(mask,op1,op2,vl); +} + + +vint32m1_t test___riscv_vmulhsu_vx_i32m1_m(vbool32_t mask,vint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i32m1_m(mask,op1,op2,vl); +} + + +vint32m2_t test___riscv_vmulhsu_vx_i32m2_m(vbool16_t mask,vint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i32m2_m(mask,op1,op2,vl); +} + + +vint32m4_t test___riscv_vmulhsu_vx_i32m4_m(vbool8_t mask,vint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i32m4_m(mask,op1,op2,vl); +} + + +vint32m8_t test___riscv_vmulhsu_vx_i32m8_m(vbool4_t mask,vint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i32m8_m(mask,op1,op2,vl); +} + + +vint64m1_t test___riscv_vmulhsu_vx_i64m1_m(vbool64_t mask,vint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i64m1_m(mask,op1,op2,vl); +} + + +vint64m2_t test___riscv_vmulhsu_vx_i64m2_m(vbool32_t mask,vint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i64m2_m(mask,op1,op2,vl); +} + + +vint64m4_t test___riscv_vmulhsu_vx_i64m4_m(vbool16_t mask,vint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i64m4_m(mask,op1,op2,vl); +} + + +vint64m8_t test___riscv_vmulhsu_vx_i64m8_m(vbool8_t mask,vint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i64m8_m(mask,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmulhsu_vx_m_rv64-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmulhsu_vx_m_rv64-2.c new file mode 100644 index 00000000000..3893edea86a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmulhsu_vx_m_rv64-2.c @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vmulhsu_vx_i8mf8_m(vbool64_t mask,vint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i8mf8_m(mask,op1,op2,31); +} + + +vint8mf4_t test___riscv_vmulhsu_vx_i8mf4_m(vbool32_t mask,vint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i8mf4_m(mask,op1,op2,31); +} + + +vint8mf2_t test___riscv_vmulhsu_vx_i8mf2_m(vbool16_t mask,vint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i8mf2_m(mask,op1,op2,31); +} + + +vint8m1_t test___riscv_vmulhsu_vx_i8m1_m(vbool8_t mask,vint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i8m1_m(mask,op1,op2,31); +} + + +vint8m2_t test___riscv_vmulhsu_vx_i8m2_m(vbool4_t mask,vint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i8m2_m(mask,op1,op2,31); +} + + +vint8m4_t test___riscv_vmulhsu_vx_i8m4_m(vbool2_t mask,vint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i8m4_m(mask,op1,op2,31); +} + + +vint8m8_t test___riscv_vmulhsu_vx_i8m8_m(vbool1_t mask,vint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i8m8_m(mask,op1,op2,31); +} + + +vint16mf4_t test___riscv_vmulhsu_vx_i16mf4_m(vbool64_t mask,vint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i16mf4_m(mask,op1,op2,31); +} + + +vint16mf2_t test___riscv_vmulhsu_vx_i16mf2_m(vbool32_t mask,vint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i16mf2_m(mask,op1,op2,31); +} + + +vint16m1_t test___riscv_vmulhsu_vx_i16m1_m(vbool16_t mask,vint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i16m1_m(mask,op1,op2,31); +} + + +vint16m2_t test___riscv_vmulhsu_vx_i16m2_m(vbool8_t mask,vint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i16m2_m(mask,op1,op2,31); +} + + +vint16m4_t test___riscv_vmulhsu_vx_i16m4_m(vbool4_t mask,vint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i16m4_m(mask,op1,op2,31); +} + + +vint16m8_t test___riscv_vmulhsu_vx_i16m8_m(vbool2_t mask,vint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i16m8_m(mask,op1,op2,31); +} + + +vint32mf2_t test___riscv_vmulhsu_vx_i32mf2_m(vbool64_t mask,vint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i32mf2_m(mask,op1,op2,31); +} + + +vint32m1_t test___riscv_vmulhsu_vx_i32m1_m(vbool32_t mask,vint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i32m1_m(mask,op1,op2,31); +} + + +vint32m2_t test___riscv_vmulhsu_vx_i32m2_m(vbool16_t mask,vint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i32m2_m(mask,op1,op2,31); +} + + +vint32m4_t test___riscv_vmulhsu_vx_i32m4_m(vbool8_t mask,vint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i32m4_m(mask,op1,op2,31); +} + + +vint32m8_t test___riscv_vmulhsu_vx_i32m8_m(vbool4_t mask,vint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i32m8_m(mask,op1,op2,31); +} + + +vint64m1_t test___riscv_vmulhsu_vx_i64m1_m(vbool64_t mask,vint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i64m1_m(mask,op1,op2,31); +} + + +vint64m2_t test___riscv_vmulhsu_vx_i64m2_m(vbool32_t mask,vint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i64m2_m(mask,op1,op2,31); +} + + +vint64m4_t test___riscv_vmulhsu_vx_i64m4_m(vbool16_t mask,vint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i64m4_m(mask,op1,op2,31); +} + + +vint64m8_t test___riscv_vmulhsu_vx_i64m8_m(vbool8_t mask,vint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i64m8_m(mask,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmulhsu_vx_m_rv64-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmulhsu_vx_m_rv64-3.c new file mode 100644 index 00000000000..2c326f902ec --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmulhsu_vx_m_rv64-3.c @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vmulhsu_vx_i8mf8_m(vbool64_t mask,vint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i8mf8_m(mask,op1,op2,32); +} + + +vint8mf4_t test___riscv_vmulhsu_vx_i8mf4_m(vbool32_t mask,vint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i8mf4_m(mask,op1,op2,32); +} + + +vint8mf2_t test___riscv_vmulhsu_vx_i8mf2_m(vbool16_t mask,vint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i8mf2_m(mask,op1,op2,32); +} + + +vint8m1_t test___riscv_vmulhsu_vx_i8m1_m(vbool8_t mask,vint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i8m1_m(mask,op1,op2,32); +} + + +vint8m2_t test___riscv_vmulhsu_vx_i8m2_m(vbool4_t mask,vint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i8m2_m(mask,op1,op2,32); +} + + +vint8m4_t test___riscv_vmulhsu_vx_i8m4_m(vbool2_t mask,vint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i8m4_m(mask,op1,op2,32); +} + + +vint8m8_t test___riscv_vmulhsu_vx_i8m8_m(vbool1_t mask,vint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i8m8_m(mask,op1,op2,32); +} + + +vint16mf4_t test___riscv_vmulhsu_vx_i16mf4_m(vbool64_t mask,vint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i16mf4_m(mask,op1,op2,32); +} + + +vint16mf2_t test___riscv_vmulhsu_vx_i16mf2_m(vbool32_t mask,vint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i16mf2_m(mask,op1,op2,32); +} + + +vint16m1_t test___riscv_vmulhsu_vx_i16m1_m(vbool16_t mask,vint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i16m1_m(mask,op1,op2,32); +} + + +vint16m2_t test___riscv_vmulhsu_vx_i16m2_m(vbool8_t mask,vint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i16m2_m(mask,op1,op2,32); +} + + +vint16m4_t test___riscv_vmulhsu_vx_i16m4_m(vbool4_t mask,vint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i16m4_m(mask,op1,op2,32); +} + + +vint16m8_t test___riscv_vmulhsu_vx_i16m8_m(vbool2_t mask,vint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i16m8_m(mask,op1,op2,32); +} + + +vint32mf2_t test___riscv_vmulhsu_vx_i32mf2_m(vbool64_t mask,vint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i32mf2_m(mask,op1,op2,32); +} + + +vint32m1_t test___riscv_vmulhsu_vx_i32m1_m(vbool32_t mask,vint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i32m1_m(mask,op1,op2,32); +} + + +vint32m2_t test___riscv_vmulhsu_vx_i32m2_m(vbool16_t mask,vint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i32m2_m(mask,op1,op2,32); +} + + +vint32m4_t test___riscv_vmulhsu_vx_i32m4_m(vbool8_t mask,vint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i32m4_m(mask,op1,op2,32); +} + + +vint32m8_t test___riscv_vmulhsu_vx_i32m8_m(vbool4_t mask,vint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i32m8_m(mask,op1,op2,32); +} + + +vint64m1_t test___riscv_vmulhsu_vx_i64m1_m(vbool64_t mask,vint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i64m1_m(mask,op1,op2,32); +} + + +vint64m2_t test___riscv_vmulhsu_vx_i64m2_m(vbool32_t mask,vint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i64m2_m(mask,op1,op2,32); +} + + +vint64m4_t test___riscv_vmulhsu_vx_i64m4_m(vbool16_t mask,vint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i64m4_m(mask,op1,op2,32); +} + + +vint64m8_t test___riscv_vmulhsu_vx_i64m8_m(vbool8_t mask,vint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i64m8_m(mask,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmulhsu_vx_mu_rv32-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmulhsu_vx_mu_rv32-1.c new file mode 100644 index 00000000000..8802778a4f8 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmulhsu_vx_mu_rv32-1.c @@ -0,0 +1,157 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vmulhsu_vx_i8mf8_mu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i8mf8_mu(mask,merge,op1,op2,vl); +} + + +vint8mf4_t test___riscv_vmulhsu_vx_i8mf4_mu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i8mf4_mu(mask,merge,op1,op2,vl); +} + + +vint8mf2_t test___riscv_vmulhsu_vx_i8mf2_mu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i8mf2_mu(mask,merge,op1,op2,vl); +} + + +vint8m1_t test___riscv_vmulhsu_vx_i8m1_mu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i8m1_mu(mask,merge,op1,op2,vl); +} + + +vint8m2_t test___riscv_vmulhsu_vx_i8m2_mu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i8m2_mu(mask,merge,op1,op2,vl); +} + + +vint8m4_t test___riscv_vmulhsu_vx_i8m4_mu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i8m4_mu(mask,merge,op1,op2,vl); +} + + +vint8m8_t test___riscv_vmulhsu_vx_i8m8_mu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i8m8_mu(mask,merge,op1,op2,vl); +} + + +vint16mf4_t test___riscv_vmulhsu_vx_i16mf4_mu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i16mf4_mu(mask,merge,op1,op2,vl); +} + + +vint16mf2_t test___riscv_vmulhsu_vx_i16mf2_mu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i16mf2_mu(mask,merge,op1,op2,vl); +} + + +vint16m1_t test___riscv_vmulhsu_vx_i16m1_mu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i16m1_mu(mask,merge,op1,op2,vl); +} + + +vint16m2_t test___riscv_vmulhsu_vx_i16m2_mu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i16m2_mu(mask,merge,op1,op2,vl); +} + + +vint16m4_t test___riscv_vmulhsu_vx_i16m4_mu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i16m4_mu(mask,merge,op1,op2,vl); +} + + +vint16m8_t test___riscv_vmulhsu_vx_i16m8_mu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i16m8_mu(mask,merge,op1,op2,vl); +} + + +vint32mf2_t test___riscv_vmulhsu_vx_i32mf2_mu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i32mf2_mu(mask,merge,op1,op2,vl); +} + + +vint32m1_t test___riscv_vmulhsu_vx_i32m1_mu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i32m1_mu(mask,merge,op1,op2,vl); +} + + +vint32m2_t test___riscv_vmulhsu_vx_i32m2_mu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i32m2_mu(mask,merge,op1,op2,vl); +} + + +vint32m4_t test___riscv_vmulhsu_vx_i32m4_mu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i32m4_mu(mask,merge,op1,op2,vl); +} + + +vint32m8_t test___riscv_vmulhsu_vx_i32m8_mu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i32m8_mu(mask,merge,op1,op2,vl); +} + + +vint64m1_t test___riscv_vmulhsu_vx_i64m1_mu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i64m1_mu(mask,merge,op1,op2,vl); +} + + +vint64m2_t test___riscv_vmulhsu_vx_i64m2_mu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i64m2_mu(mask,merge,op1,op2,vl); +} + + +vint64m4_t test___riscv_vmulhsu_vx_i64m4_mu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i64m4_mu(mask,merge,op1,op2,vl); +} + + +vint64m8_t test___riscv_vmulhsu_vx_i64m8_mu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i64m8_mu(mask,merge,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vmulhsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 4 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmulhsu_vx_mu_rv32-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmulhsu_vx_mu_rv32-2.c new file mode 100644 index 00000000000..0ca0d244c8f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmulhsu_vx_mu_rv32-2.c @@ -0,0 +1,157 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vmulhsu_vx_i8mf8_mu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i8mf8_mu(mask,merge,op1,op2,31); +} + + +vint8mf4_t test___riscv_vmulhsu_vx_i8mf4_mu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i8mf4_mu(mask,merge,op1,op2,31); +} + + +vint8mf2_t test___riscv_vmulhsu_vx_i8mf2_mu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i8mf2_mu(mask,merge,op1,op2,31); +} + + +vint8m1_t test___riscv_vmulhsu_vx_i8m1_mu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i8m1_mu(mask,merge,op1,op2,31); +} + + +vint8m2_t test___riscv_vmulhsu_vx_i8m2_mu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i8m2_mu(mask,merge,op1,op2,31); +} + + +vint8m4_t test___riscv_vmulhsu_vx_i8m4_mu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i8m4_mu(mask,merge,op1,op2,31); +} + + +vint8m8_t test___riscv_vmulhsu_vx_i8m8_mu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i8m8_mu(mask,merge,op1,op2,31); +} + + +vint16mf4_t test___riscv_vmulhsu_vx_i16mf4_mu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i16mf4_mu(mask,merge,op1,op2,31); +} + + +vint16mf2_t test___riscv_vmulhsu_vx_i16mf2_mu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i16mf2_mu(mask,merge,op1,op2,31); +} + + +vint16m1_t test___riscv_vmulhsu_vx_i16m1_mu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i16m1_mu(mask,merge,op1,op2,31); +} + + +vint16m2_t test___riscv_vmulhsu_vx_i16m2_mu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i16m2_mu(mask,merge,op1,op2,31); +} + + +vint16m4_t test___riscv_vmulhsu_vx_i16m4_mu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i16m4_mu(mask,merge,op1,op2,31); +} + + +vint16m8_t test___riscv_vmulhsu_vx_i16m8_mu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i16m8_mu(mask,merge,op1,op2,31); +} + + +vint32mf2_t test___riscv_vmulhsu_vx_i32mf2_mu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i32mf2_mu(mask,merge,op1,op2,31); +} + + +vint32m1_t test___riscv_vmulhsu_vx_i32m1_mu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i32m1_mu(mask,merge,op1,op2,31); +} + + +vint32m2_t test___riscv_vmulhsu_vx_i32m2_mu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i32m2_mu(mask,merge,op1,op2,31); +} + + +vint32m4_t test___riscv_vmulhsu_vx_i32m4_mu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i32m4_mu(mask,merge,op1,op2,31); +} + + +vint32m8_t test___riscv_vmulhsu_vx_i32m8_mu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i32m8_mu(mask,merge,op1,op2,31); +} + + +vint64m1_t test___riscv_vmulhsu_vx_i64m1_mu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i64m1_mu(mask,merge,op1,op2,31); +} + + +vint64m2_t test___riscv_vmulhsu_vx_i64m2_mu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i64m2_mu(mask,merge,op1,op2,31); +} + + +vint64m4_t test___riscv_vmulhsu_vx_i64m4_mu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i64m4_mu(mask,merge,op1,op2,31); +} + + +vint64m8_t test___riscv_vmulhsu_vx_i64m8_mu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i64m8_mu(mask,merge,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vmulhsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 4 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmulhsu_vx_mu_rv32-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmulhsu_vx_mu_rv32-3.c new file mode 100644 index 00000000000..8e379e925b0 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmulhsu_vx_mu_rv32-3.c @@ -0,0 +1,157 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vmulhsu_vx_i8mf8_mu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i8mf8_mu(mask,merge,op1,op2,32); +} + + +vint8mf4_t test___riscv_vmulhsu_vx_i8mf4_mu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i8mf4_mu(mask,merge,op1,op2,32); +} + + +vint8mf2_t test___riscv_vmulhsu_vx_i8mf2_mu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i8mf2_mu(mask,merge,op1,op2,32); +} + + +vint8m1_t test___riscv_vmulhsu_vx_i8m1_mu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i8m1_mu(mask,merge,op1,op2,32); +} + + +vint8m2_t test___riscv_vmulhsu_vx_i8m2_mu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i8m2_mu(mask,merge,op1,op2,32); +} + + +vint8m4_t test___riscv_vmulhsu_vx_i8m4_mu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i8m4_mu(mask,merge,op1,op2,32); +} + + +vint8m8_t test___riscv_vmulhsu_vx_i8m8_mu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i8m8_mu(mask,merge,op1,op2,32); +} + + +vint16mf4_t test___riscv_vmulhsu_vx_i16mf4_mu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i16mf4_mu(mask,merge,op1,op2,32); +} + + +vint16mf2_t test___riscv_vmulhsu_vx_i16mf2_mu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i16mf2_mu(mask,merge,op1,op2,32); +} + + +vint16m1_t test___riscv_vmulhsu_vx_i16m1_mu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i16m1_mu(mask,merge,op1,op2,32); +} + + +vint16m2_t test___riscv_vmulhsu_vx_i16m2_mu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i16m2_mu(mask,merge,op1,op2,32); +} + + +vint16m4_t test___riscv_vmulhsu_vx_i16m4_mu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i16m4_mu(mask,merge,op1,op2,32); +} + + +vint16m8_t test___riscv_vmulhsu_vx_i16m8_mu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i16m8_mu(mask,merge,op1,op2,32); +} + + +vint32mf2_t test___riscv_vmulhsu_vx_i32mf2_mu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i32mf2_mu(mask,merge,op1,op2,32); +} + + +vint32m1_t test___riscv_vmulhsu_vx_i32m1_mu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i32m1_mu(mask,merge,op1,op2,32); +} + + +vint32m2_t test___riscv_vmulhsu_vx_i32m2_mu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i32m2_mu(mask,merge,op1,op2,32); +} + + +vint32m4_t test___riscv_vmulhsu_vx_i32m4_mu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i32m4_mu(mask,merge,op1,op2,32); +} + + +vint32m8_t test___riscv_vmulhsu_vx_i32m8_mu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i32m8_mu(mask,merge,op1,op2,32); +} + + +vint64m1_t test___riscv_vmulhsu_vx_i64m1_mu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i64m1_mu(mask,merge,op1,op2,32); +} + + +vint64m2_t test___riscv_vmulhsu_vx_i64m2_mu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i64m2_mu(mask,merge,op1,op2,32); +} + + +vint64m4_t test___riscv_vmulhsu_vx_i64m4_mu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i64m4_mu(mask,merge,op1,op2,32); +} + + +vint64m8_t test___riscv_vmulhsu_vx_i64m8_mu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i64m8_mu(mask,merge,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vmulhsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 4 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmulhsu_vx_mu_rv64-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmulhsu_vx_mu_rv64-1.c new file mode 100644 index 00000000000..75bd43e3bb5 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmulhsu_vx_mu_rv64-1.c @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vmulhsu_vx_i8mf8_mu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i8mf8_mu(mask,merge,op1,op2,vl); +} + + +vint8mf4_t test___riscv_vmulhsu_vx_i8mf4_mu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i8mf4_mu(mask,merge,op1,op2,vl); +} + + +vint8mf2_t test___riscv_vmulhsu_vx_i8mf2_mu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i8mf2_mu(mask,merge,op1,op2,vl); +} + + +vint8m1_t test___riscv_vmulhsu_vx_i8m1_mu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i8m1_mu(mask,merge,op1,op2,vl); +} + + +vint8m2_t test___riscv_vmulhsu_vx_i8m2_mu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i8m2_mu(mask,merge,op1,op2,vl); +} + + +vint8m4_t test___riscv_vmulhsu_vx_i8m4_mu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i8m4_mu(mask,merge,op1,op2,vl); +} + + +vint8m8_t test___riscv_vmulhsu_vx_i8m8_mu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i8m8_mu(mask,merge,op1,op2,vl); +} + + +vint16mf4_t test___riscv_vmulhsu_vx_i16mf4_mu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i16mf4_mu(mask,merge,op1,op2,vl); +} + + +vint16mf2_t test___riscv_vmulhsu_vx_i16mf2_mu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i16mf2_mu(mask,merge,op1,op2,vl); +} + + +vint16m1_t test___riscv_vmulhsu_vx_i16m1_mu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i16m1_mu(mask,merge,op1,op2,vl); +} + + +vint16m2_t test___riscv_vmulhsu_vx_i16m2_mu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i16m2_mu(mask,merge,op1,op2,vl); +} + + +vint16m4_t test___riscv_vmulhsu_vx_i16m4_mu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i16m4_mu(mask,merge,op1,op2,vl); +} + + +vint16m8_t test___riscv_vmulhsu_vx_i16m8_mu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i16m8_mu(mask,merge,op1,op2,vl); +} + + +vint32mf2_t test___riscv_vmulhsu_vx_i32mf2_mu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i32mf2_mu(mask,merge,op1,op2,vl); +} + + +vint32m1_t test___riscv_vmulhsu_vx_i32m1_mu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i32m1_mu(mask,merge,op1,op2,vl); +} + + +vint32m2_t test___riscv_vmulhsu_vx_i32m2_mu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i32m2_mu(mask,merge,op1,op2,vl); +} + + +vint32m4_t test___riscv_vmulhsu_vx_i32m4_mu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i32m4_mu(mask,merge,op1,op2,vl); +} + + +vint32m8_t test___riscv_vmulhsu_vx_i32m8_mu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i32m8_mu(mask,merge,op1,op2,vl); +} + + +vint64m1_t test___riscv_vmulhsu_vx_i64m1_mu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i64m1_mu(mask,merge,op1,op2,vl); +} + + +vint64m2_t test___riscv_vmulhsu_vx_i64m2_mu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i64m2_mu(mask,merge,op1,op2,vl); +} + + +vint64m4_t test___riscv_vmulhsu_vx_i64m4_mu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i64m4_mu(mask,merge,op1,op2,vl); +} + + +vint64m8_t test___riscv_vmulhsu_vx_i64m8_mu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i64m8_mu(mask,merge,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmulhsu_vx_mu_rv64-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmulhsu_vx_mu_rv64-2.c new file mode 100644 index 00000000000..e3de22968be --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmulhsu_vx_mu_rv64-2.c @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vmulhsu_vx_i8mf8_mu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i8mf8_mu(mask,merge,op1,op2,31); +} + + +vint8mf4_t test___riscv_vmulhsu_vx_i8mf4_mu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i8mf4_mu(mask,merge,op1,op2,31); +} + + +vint8mf2_t test___riscv_vmulhsu_vx_i8mf2_mu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i8mf2_mu(mask,merge,op1,op2,31); +} + + +vint8m1_t test___riscv_vmulhsu_vx_i8m1_mu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i8m1_mu(mask,merge,op1,op2,31); +} + + +vint8m2_t test___riscv_vmulhsu_vx_i8m2_mu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i8m2_mu(mask,merge,op1,op2,31); +} + + +vint8m4_t test___riscv_vmulhsu_vx_i8m4_mu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i8m4_mu(mask,merge,op1,op2,31); +} + + +vint8m8_t test___riscv_vmulhsu_vx_i8m8_mu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i8m8_mu(mask,merge,op1,op2,31); +} + + +vint16mf4_t test___riscv_vmulhsu_vx_i16mf4_mu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i16mf4_mu(mask,merge,op1,op2,31); +} + + +vint16mf2_t test___riscv_vmulhsu_vx_i16mf2_mu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i16mf2_mu(mask,merge,op1,op2,31); +} + + +vint16m1_t test___riscv_vmulhsu_vx_i16m1_mu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i16m1_mu(mask,merge,op1,op2,31); +} + + +vint16m2_t test___riscv_vmulhsu_vx_i16m2_mu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i16m2_mu(mask,merge,op1,op2,31); +} + + +vint16m4_t test___riscv_vmulhsu_vx_i16m4_mu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i16m4_mu(mask,merge,op1,op2,31); +} + + +vint16m8_t test___riscv_vmulhsu_vx_i16m8_mu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i16m8_mu(mask,merge,op1,op2,31); +} + + +vint32mf2_t test___riscv_vmulhsu_vx_i32mf2_mu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i32mf2_mu(mask,merge,op1,op2,31); +} + + +vint32m1_t test___riscv_vmulhsu_vx_i32m1_mu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i32m1_mu(mask,merge,op1,op2,31); +} + + +vint32m2_t test___riscv_vmulhsu_vx_i32m2_mu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i32m2_mu(mask,merge,op1,op2,31); +} + + +vint32m4_t test___riscv_vmulhsu_vx_i32m4_mu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i32m4_mu(mask,merge,op1,op2,31); +} + + +vint32m8_t test___riscv_vmulhsu_vx_i32m8_mu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i32m8_mu(mask,merge,op1,op2,31); +} + + +vint64m1_t test___riscv_vmulhsu_vx_i64m1_mu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i64m1_mu(mask,merge,op1,op2,31); +} + + +vint64m2_t test___riscv_vmulhsu_vx_i64m2_mu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i64m2_mu(mask,merge,op1,op2,31); +} + + +vint64m4_t test___riscv_vmulhsu_vx_i64m4_mu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i64m4_mu(mask,merge,op1,op2,31); +} + + +vint64m8_t test___riscv_vmulhsu_vx_i64m8_mu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i64m8_mu(mask,merge,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmulhsu_vx_mu_rv64-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmulhsu_vx_mu_rv64-3.c new file mode 100644 index 00000000000..7ec400c7f67 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmulhsu_vx_mu_rv64-3.c @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vmulhsu_vx_i8mf8_mu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i8mf8_mu(mask,merge,op1,op2,32); +} + + +vint8mf4_t test___riscv_vmulhsu_vx_i8mf4_mu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i8mf4_mu(mask,merge,op1,op2,32); +} + + +vint8mf2_t test___riscv_vmulhsu_vx_i8mf2_mu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i8mf2_mu(mask,merge,op1,op2,32); +} + + +vint8m1_t test___riscv_vmulhsu_vx_i8m1_mu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i8m1_mu(mask,merge,op1,op2,32); +} + + +vint8m2_t test___riscv_vmulhsu_vx_i8m2_mu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i8m2_mu(mask,merge,op1,op2,32); +} + + +vint8m4_t test___riscv_vmulhsu_vx_i8m4_mu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i8m4_mu(mask,merge,op1,op2,32); +} + + +vint8m8_t test___riscv_vmulhsu_vx_i8m8_mu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i8m8_mu(mask,merge,op1,op2,32); +} + + +vint16mf4_t test___riscv_vmulhsu_vx_i16mf4_mu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i16mf4_mu(mask,merge,op1,op2,32); +} + + +vint16mf2_t test___riscv_vmulhsu_vx_i16mf2_mu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i16mf2_mu(mask,merge,op1,op2,32); +} + + +vint16m1_t test___riscv_vmulhsu_vx_i16m1_mu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i16m1_mu(mask,merge,op1,op2,32); +} + + +vint16m2_t test___riscv_vmulhsu_vx_i16m2_mu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i16m2_mu(mask,merge,op1,op2,32); +} + + +vint16m4_t test___riscv_vmulhsu_vx_i16m4_mu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i16m4_mu(mask,merge,op1,op2,32); +} + + +vint16m8_t test___riscv_vmulhsu_vx_i16m8_mu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i16m8_mu(mask,merge,op1,op2,32); +} + + +vint32mf2_t test___riscv_vmulhsu_vx_i32mf2_mu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i32mf2_mu(mask,merge,op1,op2,32); +} + + +vint32m1_t test___riscv_vmulhsu_vx_i32m1_mu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i32m1_mu(mask,merge,op1,op2,32); +} + + +vint32m2_t test___riscv_vmulhsu_vx_i32m2_mu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i32m2_mu(mask,merge,op1,op2,32); +} + + +vint32m4_t test___riscv_vmulhsu_vx_i32m4_mu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i32m4_mu(mask,merge,op1,op2,32); +} + + +vint32m8_t test___riscv_vmulhsu_vx_i32m8_mu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i32m8_mu(mask,merge,op1,op2,32); +} + + +vint64m1_t test___riscv_vmulhsu_vx_i64m1_mu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i64m1_mu(mask,merge,op1,op2,32); +} + + +vint64m2_t test___riscv_vmulhsu_vx_i64m2_mu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i64m2_mu(mask,merge,op1,op2,32); +} + + +vint64m4_t test___riscv_vmulhsu_vx_i64m4_mu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i64m4_mu(mask,merge,op1,op2,32); +} + + +vint64m8_t test___riscv_vmulhsu_vx_i64m8_mu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i64m8_mu(mask,merge,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmulhsu_vx_rv32-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmulhsu_vx_rv32-1.c new file mode 100644 index 00000000000..95614c6fb2e --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmulhsu_vx_rv32-1.c @@ -0,0 +1,157 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vmulhsu_vx_i8mf8(vint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i8mf8(op1,op2,vl); +} + + +vint8mf4_t test___riscv_vmulhsu_vx_i8mf4(vint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i8mf4(op1,op2,vl); +} + + +vint8mf2_t test___riscv_vmulhsu_vx_i8mf2(vint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i8mf2(op1,op2,vl); +} + + +vint8m1_t test___riscv_vmulhsu_vx_i8m1(vint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i8m1(op1,op2,vl); +} + + +vint8m2_t test___riscv_vmulhsu_vx_i8m2(vint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i8m2(op1,op2,vl); +} + + +vint8m4_t test___riscv_vmulhsu_vx_i8m4(vint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i8m4(op1,op2,vl); +} + + +vint8m8_t test___riscv_vmulhsu_vx_i8m8(vint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i8m8(op1,op2,vl); +} + + +vint16mf4_t test___riscv_vmulhsu_vx_i16mf4(vint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i16mf4(op1,op2,vl); +} + + +vint16mf2_t test___riscv_vmulhsu_vx_i16mf2(vint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i16mf2(op1,op2,vl); +} + + +vint16m1_t test___riscv_vmulhsu_vx_i16m1(vint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i16m1(op1,op2,vl); +} + + +vint16m2_t test___riscv_vmulhsu_vx_i16m2(vint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i16m2(op1,op2,vl); +} + + +vint16m4_t test___riscv_vmulhsu_vx_i16m4(vint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i16m4(op1,op2,vl); +} + + +vint16m8_t test___riscv_vmulhsu_vx_i16m8(vint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i16m8(op1,op2,vl); +} + + +vint32mf2_t test___riscv_vmulhsu_vx_i32mf2(vint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i32mf2(op1,op2,vl); +} + + +vint32m1_t test___riscv_vmulhsu_vx_i32m1(vint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i32m1(op1,op2,vl); +} + + +vint32m2_t test___riscv_vmulhsu_vx_i32m2(vint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i32m2(op1,op2,vl); +} + + +vint32m4_t test___riscv_vmulhsu_vx_i32m4(vint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i32m4(op1,op2,vl); +} + + +vint32m8_t test___riscv_vmulhsu_vx_i32m8(vint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i32m8(op1,op2,vl); +} + + +vint64m1_t test___riscv_vmulhsu_vx_i64m1(vint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i64m1(op1,op2,vl); +} + + +vint64m2_t test___riscv_vmulhsu_vx_i64m2(vint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i64m2(op1,op2,vl); +} + + +vint64m4_t test___riscv_vmulhsu_vx_i64m4(vint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i64m4(op1,op2,vl); +} + + +vint64m8_t test___riscv_vmulhsu_vx_i64m8(vint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i64m8(op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vmulhsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 4 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmulhsu_vx_rv32-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmulhsu_vx_rv32-2.c new file mode 100644 index 00000000000..665f88d7786 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmulhsu_vx_rv32-2.c @@ -0,0 +1,157 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vmulhsu_vx_i8mf8(vint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i8mf8(op1,op2,31); +} + + +vint8mf4_t test___riscv_vmulhsu_vx_i8mf4(vint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i8mf4(op1,op2,31); +} + + +vint8mf2_t test___riscv_vmulhsu_vx_i8mf2(vint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i8mf2(op1,op2,31); +} + + +vint8m1_t test___riscv_vmulhsu_vx_i8m1(vint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i8m1(op1,op2,31); +} + + +vint8m2_t test___riscv_vmulhsu_vx_i8m2(vint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i8m2(op1,op2,31); +} + + +vint8m4_t test___riscv_vmulhsu_vx_i8m4(vint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i8m4(op1,op2,31); +} + + +vint8m8_t test___riscv_vmulhsu_vx_i8m8(vint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i8m8(op1,op2,31); +} + + +vint16mf4_t test___riscv_vmulhsu_vx_i16mf4(vint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i16mf4(op1,op2,31); +} + + +vint16mf2_t test___riscv_vmulhsu_vx_i16mf2(vint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i16mf2(op1,op2,31); +} + + +vint16m1_t test___riscv_vmulhsu_vx_i16m1(vint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i16m1(op1,op2,31); +} + + +vint16m2_t test___riscv_vmulhsu_vx_i16m2(vint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i16m2(op1,op2,31); +} + + +vint16m4_t test___riscv_vmulhsu_vx_i16m4(vint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i16m4(op1,op2,31); +} + + +vint16m8_t test___riscv_vmulhsu_vx_i16m8(vint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i16m8(op1,op2,31); +} + + +vint32mf2_t test___riscv_vmulhsu_vx_i32mf2(vint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i32mf2(op1,op2,31); +} + + +vint32m1_t test___riscv_vmulhsu_vx_i32m1(vint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i32m1(op1,op2,31); +} + + +vint32m2_t test___riscv_vmulhsu_vx_i32m2(vint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i32m2(op1,op2,31); +} + + +vint32m4_t test___riscv_vmulhsu_vx_i32m4(vint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i32m4(op1,op2,31); +} + + +vint32m8_t test___riscv_vmulhsu_vx_i32m8(vint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i32m8(op1,op2,31); +} + + +vint64m1_t test___riscv_vmulhsu_vx_i64m1(vint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i64m1(op1,op2,31); +} + + +vint64m2_t test___riscv_vmulhsu_vx_i64m2(vint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i64m2(op1,op2,31); +} + + +vint64m4_t test___riscv_vmulhsu_vx_i64m4(vint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i64m4(op1,op2,31); +} + + +vint64m8_t test___riscv_vmulhsu_vx_i64m8(vint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i64m8(op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vmulhsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 4 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmulhsu_vx_rv32-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmulhsu_vx_rv32-3.c new file mode 100644 index 00000000000..b9779e30c47 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmulhsu_vx_rv32-3.c @@ -0,0 +1,157 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vmulhsu_vx_i8mf8(vint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i8mf8(op1,op2,32); +} + + +vint8mf4_t test___riscv_vmulhsu_vx_i8mf4(vint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i8mf4(op1,op2,32); +} + + +vint8mf2_t test___riscv_vmulhsu_vx_i8mf2(vint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i8mf2(op1,op2,32); +} + + +vint8m1_t test___riscv_vmulhsu_vx_i8m1(vint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i8m1(op1,op2,32); +} + + +vint8m2_t test___riscv_vmulhsu_vx_i8m2(vint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i8m2(op1,op2,32); +} + + +vint8m4_t test___riscv_vmulhsu_vx_i8m4(vint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i8m4(op1,op2,32); +} + + +vint8m8_t test___riscv_vmulhsu_vx_i8m8(vint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i8m8(op1,op2,32); +} + + +vint16mf4_t test___riscv_vmulhsu_vx_i16mf4(vint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i16mf4(op1,op2,32); +} + + +vint16mf2_t test___riscv_vmulhsu_vx_i16mf2(vint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i16mf2(op1,op2,32); +} + + +vint16m1_t test___riscv_vmulhsu_vx_i16m1(vint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i16m1(op1,op2,32); +} + + +vint16m2_t test___riscv_vmulhsu_vx_i16m2(vint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i16m2(op1,op2,32); +} + + +vint16m4_t test___riscv_vmulhsu_vx_i16m4(vint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i16m4(op1,op2,32); +} + + +vint16m8_t test___riscv_vmulhsu_vx_i16m8(vint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i16m8(op1,op2,32); +} + + +vint32mf2_t test___riscv_vmulhsu_vx_i32mf2(vint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i32mf2(op1,op2,32); +} + + +vint32m1_t test___riscv_vmulhsu_vx_i32m1(vint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i32m1(op1,op2,32); +} + + +vint32m2_t test___riscv_vmulhsu_vx_i32m2(vint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i32m2(op1,op2,32); +} + + +vint32m4_t test___riscv_vmulhsu_vx_i32m4(vint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i32m4(op1,op2,32); +} + + +vint32m8_t test___riscv_vmulhsu_vx_i32m8(vint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i32m8(op1,op2,32); +} + + +vint64m1_t test___riscv_vmulhsu_vx_i64m1(vint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i64m1(op1,op2,32); +} + + +vint64m2_t test___riscv_vmulhsu_vx_i64m2(vint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i64m2(op1,op2,32); +} + + +vint64m4_t test___riscv_vmulhsu_vx_i64m4(vint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i64m4(op1,op2,32); +} + + +vint64m8_t test___riscv_vmulhsu_vx_i64m8(vint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i64m8(op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vmulhsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 4 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmulhsu_vx_rv64-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmulhsu_vx_rv64-1.c new file mode 100644 index 00000000000..4bd836bc477 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmulhsu_vx_rv64-1.c @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vmulhsu_vx_i8mf8(vint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i8mf8(op1,op2,vl); +} + + +vint8mf4_t test___riscv_vmulhsu_vx_i8mf4(vint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i8mf4(op1,op2,vl); +} + + +vint8mf2_t test___riscv_vmulhsu_vx_i8mf2(vint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i8mf2(op1,op2,vl); +} + + +vint8m1_t test___riscv_vmulhsu_vx_i8m1(vint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i8m1(op1,op2,vl); +} + + +vint8m2_t test___riscv_vmulhsu_vx_i8m2(vint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i8m2(op1,op2,vl); +} + + +vint8m4_t test___riscv_vmulhsu_vx_i8m4(vint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i8m4(op1,op2,vl); +} + + +vint8m8_t test___riscv_vmulhsu_vx_i8m8(vint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i8m8(op1,op2,vl); +} + + +vint16mf4_t test___riscv_vmulhsu_vx_i16mf4(vint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i16mf4(op1,op2,vl); +} + + +vint16mf2_t test___riscv_vmulhsu_vx_i16mf2(vint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i16mf2(op1,op2,vl); +} + + +vint16m1_t test___riscv_vmulhsu_vx_i16m1(vint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i16m1(op1,op2,vl); +} + + +vint16m2_t test___riscv_vmulhsu_vx_i16m2(vint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i16m2(op1,op2,vl); +} + + +vint16m4_t test___riscv_vmulhsu_vx_i16m4(vint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i16m4(op1,op2,vl); +} + + +vint16m8_t test___riscv_vmulhsu_vx_i16m8(vint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i16m8(op1,op2,vl); +} + + +vint32mf2_t test___riscv_vmulhsu_vx_i32mf2(vint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i32mf2(op1,op2,vl); +} + + +vint32m1_t test___riscv_vmulhsu_vx_i32m1(vint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i32m1(op1,op2,vl); +} + + +vint32m2_t test___riscv_vmulhsu_vx_i32m2(vint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i32m2(op1,op2,vl); +} + + +vint32m4_t test___riscv_vmulhsu_vx_i32m4(vint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i32m4(op1,op2,vl); +} + + +vint32m8_t test___riscv_vmulhsu_vx_i32m8(vint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i32m8(op1,op2,vl); +} + + +vint64m1_t test___riscv_vmulhsu_vx_i64m1(vint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i64m1(op1,op2,vl); +} + + +vint64m2_t test___riscv_vmulhsu_vx_i64m2(vint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i64m2(op1,op2,vl); +} + + +vint64m4_t test___riscv_vmulhsu_vx_i64m4(vint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i64m4(op1,op2,vl); +} + + +vint64m8_t test___riscv_vmulhsu_vx_i64m8(vint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i64m8(op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmulhsu_vx_rv64-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmulhsu_vx_rv64-2.c new file mode 100644 index 00000000000..661373f2da7 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmulhsu_vx_rv64-2.c @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vmulhsu_vx_i8mf8(vint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i8mf8(op1,op2,31); +} + + +vint8mf4_t test___riscv_vmulhsu_vx_i8mf4(vint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i8mf4(op1,op2,31); +} + + +vint8mf2_t test___riscv_vmulhsu_vx_i8mf2(vint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i8mf2(op1,op2,31); +} + + +vint8m1_t test___riscv_vmulhsu_vx_i8m1(vint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i8m1(op1,op2,31); +} + + +vint8m2_t test___riscv_vmulhsu_vx_i8m2(vint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i8m2(op1,op2,31); +} + + +vint8m4_t test___riscv_vmulhsu_vx_i8m4(vint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i8m4(op1,op2,31); +} + + +vint8m8_t test___riscv_vmulhsu_vx_i8m8(vint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i8m8(op1,op2,31); +} + + +vint16mf4_t test___riscv_vmulhsu_vx_i16mf4(vint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i16mf4(op1,op2,31); +} + + +vint16mf2_t test___riscv_vmulhsu_vx_i16mf2(vint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i16mf2(op1,op2,31); +} + + +vint16m1_t test___riscv_vmulhsu_vx_i16m1(vint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i16m1(op1,op2,31); +} + + +vint16m2_t test___riscv_vmulhsu_vx_i16m2(vint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i16m2(op1,op2,31); +} + + +vint16m4_t test___riscv_vmulhsu_vx_i16m4(vint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i16m4(op1,op2,31); +} + + +vint16m8_t test___riscv_vmulhsu_vx_i16m8(vint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i16m8(op1,op2,31); +} + + +vint32mf2_t test___riscv_vmulhsu_vx_i32mf2(vint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i32mf2(op1,op2,31); +} + + +vint32m1_t test___riscv_vmulhsu_vx_i32m1(vint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i32m1(op1,op2,31); +} + + +vint32m2_t test___riscv_vmulhsu_vx_i32m2(vint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i32m2(op1,op2,31); +} + + +vint32m4_t test___riscv_vmulhsu_vx_i32m4(vint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i32m4(op1,op2,31); +} + + +vint32m8_t test___riscv_vmulhsu_vx_i32m8(vint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i32m8(op1,op2,31); +} + + +vint64m1_t test___riscv_vmulhsu_vx_i64m1(vint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i64m1(op1,op2,31); +} + + +vint64m2_t test___riscv_vmulhsu_vx_i64m2(vint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i64m2(op1,op2,31); +} + + +vint64m4_t test___riscv_vmulhsu_vx_i64m4(vint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i64m4(op1,op2,31); +} + + +vint64m8_t test___riscv_vmulhsu_vx_i64m8(vint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i64m8(op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmulhsu_vx_rv64-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmulhsu_vx_rv64-3.c new file mode 100644 index 00000000000..6ef0bd73dbc --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmulhsu_vx_rv64-3.c @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vmulhsu_vx_i8mf8(vint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i8mf8(op1,op2,32); +} + + +vint8mf4_t test___riscv_vmulhsu_vx_i8mf4(vint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i8mf4(op1,op2,32); +} + + +vint8mf2_t test___riscv_vmulhsu_vx_i8mf2(vint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i8mf2(op1,op2,32); +} + + +vint8m1_t test___riscv_vmulhsu_vx_i8m1(vint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i8m1(op1,op2,32); +} + + +vint8m2_t test___riscv_vmulhsu_vx_i8m2(vint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i8m2(op1,op2,32); +} + + +vint8m4_t test___riscv_vmulhsu_vx_i8m4(vint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i8m4(op1,op2,32); +} + + +vint8m8_t test___riscv_vmulhsu_vx_i8m8(vint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i8m8(op1,op2,32); +} + + +vint16mf4_t test___riscv_vmulhsu_vx_i16mf4(vint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i16mf4(op1,op2,32); +} + + +vint16mf2_t test___riscv_vmulhsu_vx_i16mf2(vint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i16mf2(op1,op2,32); +} + + +vint16m1_t test___riscv_vmulhsu_vx_i16m1(vint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i16m1(op1,op2,32); +} + + +vint16m2_t test___riscv_vmulhsu_vx_i16m2(vint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i16m2(op1,op2,32); +} + + +vint16m4_t test___riscv_vmulhsu_vx_i16m4(vint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i16m4(op1,op2,32); +} + + +vint16m8_t test___riscv_vmulhsu_vx_i16m8(vint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i16m8(op1,op2,32); +} + + +vint32mf2_t test___riscv_vmulhsu_vx_i32mf2(vint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i32mf2(op1,op2,32); +} + + +vint32m1_t test___riscv_vmulhsu_vx_i32m1(vint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i32m1(op1,op2,32); +} + + +vint32m2_t test___riscv_vmulhsu_vx_i32m2(vint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i32m2(op1,op2,32); +} + + +vint32m4_t test___riscv_vmulhsu_vx_i32m4(vint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i32m4(op1,op2,32); +} + + +vint32m8_t test___riscv_vmulhsu_vx_i32m8(vint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i32m8(op1,op2,32); +} + + +vint64m1_t test___riscv_vmulhsu_vx_i64m1(vint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i64m1(op1,op2,32); +} + + +vint64m2_t test___riscv_vmulhsu_vx_i64m2(vint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i64m2(op1,op2,32); +} + + +vint64m4_t test___riscv_vmulhsu_vx_i64m4(vint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i64m4(op1,op2,32); +} + + +vint64m8_t test___riscv_vmulhsu_vx_i64m8(vint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i64m8(op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmulhsu_vx_tu_rv32-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmulhsu_vx_tu_rv32-1.c new file mode 100644 index 00000000000..83b30b87b49 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmulhsu_vx_tu_rv32-1.c @@ -0,0 +1,157 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vmulhsu_vx_i8mf8_tu(vint8mf8_t merge,vint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i8mf8_tu(merge,op1,op2,vl); +} + + +vint8mf4_t test___riscv_vmulhsu_vx_i8mf4_tu(vint8mf4_t merge,vint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i8mf4_tu(merge,op1,op2,vl); +} + + +vint8mf2_t test___riscv_vmulhsu_vx_i8mf2_tu(vint8mf2_t merge,vint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i8mf2_tu(merge,op1,op2,vl); +} + + +vint8m1_t test___riscv_vmulhsu_vx_i8m1_tu(vint8m1_t merge,vint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i8m1_tu(merge,op1,op2,vl); +} + + +vint8m2_t test___riscv_vmulhsu_vx_i8m2_tu(vint8m2_t merge,vint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i8m2_tu(merge,op1,op2,vl); +} + + +vint8m4_t test___riscv_vmulhsu_vx_i8m4_tu(vint8m4_t merge,vint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i8m4_tu(merge,op1,op2,vl); +} + + +vint8m8_t test___riscv_vmulhsu_vx_i8m8_tu(vint8m8_t merge,vint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i8m8_tu(merge,op1,op2,vl); +} + + +vint16mf4_t test___riscv_vmulhsu_vx_i16mf4_tu(vint16mf4_t merge,vint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i16mf4_tu(merge,op1,op2,vl); +} + + +vint16mf2_t test___riscv_vmulhsu_vx_i16mf2_tu(vint16mf2_t merge,vint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i16mf2_tu(merge,op1,op2,vl); +} + + +vint16m1_t test___riscv_vmulhsu_vx_i16m1_tu(vint16m1_t merge,vint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i16m1_tu(merge,op1,op2,vl); +} + + +vint16m2_t test___riscv_vmulhsu_vx_i16m2_tu(vint16m2_t merge,vint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i16m2_tu(merge,op1,op2,vl); +} + + +vint16m4_t test___riscv_vmulhsu_vx_i16m4_tu(vint16m4_t merge,vint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i16m4_tu(merge,op1,op2,vl); +} + + +vint16m8_t test___riscv_vmulhsu_vx_i16m8_tu(vint16m8_t merge,vint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i16m8_tu(merge,op1,op2,vl); +} + + +vint32mf2_t test___riscv_vmulhsu_vx_i32mf2_tu(vint32mf2_t merge,vint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i32mf2_tu(merge,op1,op2,vl); +} + + +vint32m1_t test___riscv_vmulhsu_vx_i32m1_tu(vint32m1_t merge,vint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i32m1_tu(merge,op1,op2,vl); +} + + +vint32m2_t test___riscv_vmulhsu_vx_i32m2_tu(vint32m2_t merge,vint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i32m2_tu(merge,op1,op2,vl); +} + + +vint32m4_t test___riscv_vmulhsu_vx_i32m4_tu(vint32m4_t merge,vint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i32m4_tu(merge,op1,op2,vl); +} + + +vint32m8_t test___riscv_vmulhsu_vx_i32m8_tu(vint32m8_t merge,vint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i32m8_tu(merge,op1,op2,vl); +} + + +vint64m1_t test___riscv_vmulhsu_vx_i64m1_tu(vint64m1_t merge,vint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i64m1_tu(merge,op1,op2,vl); +} + + +vint64m2_t test___riscv_vmulhsu_vx_i64m2_tu(vint64m2_t merge,vint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i64m2_tu(merge,op1,op2,vl); +} + + +vint64m4_t test___riscv_vmulhsu_vx_i64m4_tu(vint64m4_t merge,vint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i64m4_tu(merge,op1,op2,vl); +} + + +vint64m8_t test___riscv_vmulhsu_vx_i64m8_tu(vint64m8_t merge,vint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i64m8_tu(merge,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vmulhsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 4 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmulhsu_vx_tu_rv32-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmulhsu_vx_tu_rv32-2.c new file mode 100644 index 00000000000..e4526b95289 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmulhsu_vx_tu_rv32-2.c @@ -0,0 +1,157 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vmulhsu_vx_i8mf8_tu(vint8mf8_t merge,vint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i8mf8_tu(merge,op1,op2,31); +} + + +vint8mf4_t test___riscv_vmulhsu_vx_i8mf4_tu(vint8mf4_t merge,vint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i8mf4_tu(merge,op1,op2,31); +} + + +vint8mf2_t test___riscv_vmulhsu_vx_i8mf2_tu(vint8mf2_t merge,vint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i8mf2_tu(merge,op1,op2,31); +} + + +vint8m1_t test___riscv_vmulhsu_vx_i8m1_tu(vint8m1_t merge,vint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i8m1_tu(merge,op1,op2,31); +} + + +vint8m2_t test___riscv_vmulhsu_vx_i8m2_tu(vint8m2_t merge,vint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i8m2_tu(merge,op1,op2,31); +} + + +vint8m4_t test___riscv_vmulhsu_vx_i8m4_tu(vint8m4_t merge,vint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i8m4_tu(merge,op1,op2,31); +} + + +vint8m8_t test___riscv_vmulhsu_vx_i8m8_tu(vint8m8_t merge,vint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i8m8_tu(merge,op1,op2,31); +} + + +vint16mf4_t test___riscv_vmulhsu_vx_i16mf4_tu(vint16mf4_t merge,vint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i16mf4_tu(merge,op1,op2,31); +} + + +vint16mf2_t test___riscv_vmulhsu_vx_i16mf2_tu(vint16mf2_t merge,vint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i16mf2_tu(merge,op1,op2,31); +} + + +vint16m1_t test___riscv_vmulhsu_vx_i16m1_tu(vint16m1_t merge,vint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i16m1_tu(merge,op1,op2,31); +} + + +vint16m2_t test___riscv_vmulhsu_vx_i16m2_tu(vint16m2_t merge,vint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i16m2_tu(merge,op1,op2,31); +} + + +vint16m4_t test___riscv_vmulhsu_vx_i16m4_tu(vint16m4_t merge,vint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i16m4_tu(merge,op1,op2,31); +} + + +vint16m8_t test___riscv_vmulhsu_vx_i16m8_tu(vint16m8_t merge,vint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i16m8_tu(merge,op1,op2,31); +} + + +vint32mf2_t test___riscv_vmulhsu_vx_i32mf2_tu(vint32mf2_t merge,vint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i32mf2_tu(merge,op1,op2,31); +} + + +vint32m1_t test___riscv_vmulhsu_vx_i32m1_tu(vint32m1_t merge,vint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i32m1_tu(merge,op1,op2,31); +} + + +vint32m2_t test___riscv_vmulhsu_vx_i32m2_tu(vint32m2_t merge,vint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i32m2_tu(merge,op1,op2,31); +} + + +vint32m4_t test___riscv_vmulhsu_vx_i32m4_tu(vint32m4_t merge,vint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i32m4_tu(merge,op1,op2,31); +} + + +vint32m8_t test___riscv_vmulhsu_vx_i32m8_tu(vint32m8_t merge,vint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i32m8_tu(merge,op1,op2,31); +} + + +vint64m1_t test___riscv_vmulhsu_vx_i64m1_tu(vint64m1_t merge,vint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i64m1_tu(merge,op1,op2,31); +} + + +vint64m2_t test___riscv_vmulhsu_vx_i64m2_tu(vint64m2_t merge,vint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i64m2_tu(merge,op1,op2,31); +} + + +vint64m4_t test___riscv_vmulhsu_vx_i64m4_tu(vint64m4_t merge,vint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i64m4_tu(merge,op1,op2,31); +} + + +vint64m8_t test___riscv_vmulhsu_vx_i64m8_tu(vint64m8_t merge,vint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i64m8_tu(merge,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vmulhsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 4 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmulhsu_vx_tu_rv32-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmulhsu_vx_tu_rv32-3.c new file mode 100644 index 00000000000..1df89d6825d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmulhsu_vx_tu_rv32-3.c @@ -0,0 +1,157 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vmulhsu_vx_i8mf8_tu(vint8mf8_t merge,vint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i8mf8_tu(merge,op1,op2,32); +} + + +vint8mf4_t test___riscv_vmulhsu_vx_i8mf4_tu(vint8mf4_t merge,vint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i8mf4_tu(merge,op1,op2,32); +} + + +vint8mf2_t test___riscv_vmulhsu_vx_i8mf2_tu(vint8mf2_t merge,vint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i8mf2_tu(merge,op1,op2,32); +} + + +vint8m1_t test___riscv_vmulhsu_vx_i8m1_tu(vint8m1_t merge,vint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i8m1_tu(merge,op1,op2,32); +} + + +vint8m2_t test___riscv_vmulhsu_vx_i8m2_tu(vint8m2_t merge,vint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i8m2_tu(merge,op1,op2,32); +} + + +vint8m4_t test___riscv_vmulhsu_vx_i8m4_tu(vint8m4_t merge,vint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i8m4_tu(merge,op1,op2,32); +} + + +vint8m8_t test___riscv_vmulhsu_vx_i8m8_tu(vint8m8_t merge,vint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i8m8_tu(merge,op1,op2,32); +} + + +vint16mf4_t test___riscv_vmulhsu_vx_i16mf4_tu(vint16mf4_t merge,vint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i16mf4_tu(merge,op1,op2,32); +} + + +vint16mf2_t test___riscv_vmulhsu_vx_i16mf2_tu(vint16mf2_t merge,vint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i16mf2_tu(merge,op1,op2,32); +} + + +vint16m1_t test___riscv_vmulhsu_vx_i16m1_tu(vint16m1_t merge,vint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i16m1_tu(merge,op1,op2,32); +} + + +vint16m2_t test___riscv_vmulhsu_vx_i16m2_tu(vint16m2_t merge,vint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i16m2_tu(merge,op1,op2,32); +} + + +vint16m4_t test___riscv_vmulhsu_vx_i16m4_tu(vint16m4_t merge,vint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i16m4_tu(merge,op1,op2,32); +} + + +vint16m8_t test___riscv_vmulhsu_vx_i16m8_tu(vint16m8_t merge,vint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i16m8_tu(merge,op1,op2,32); +} + + +vint32mf2_t test___riscv_vmulhsu_vx_i32mf2_tu(vint32mf2_t merge,vint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i32mf2_tu(merge,op1,op2,32); +} + + +vint32m1_t test___riscv_vmulhsu_vx_i32m1_tu(vint32m1_t merge,vint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i32m1_tu(merge,op1,op2,32); +} + + +vint32m2_t test___riscv_vmulhsu_vx_i32m2_tu(vint32m2_t merge,vint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i32m2_tu(merge,op1,op2,32); +} + + +vint32m4_t test___riscv_vmulhsu_vx_i32m4_tu(vint32m4_t merge,vint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i32m4_tu(merge,op1,op2,32); +} + + +vint32m8_t test___riscv_vmulhsu_vx_i32m8_tu(vint32m8_t merge,vint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i32m8_tu(merge,op1,op2,32); +} + + +vint64m1_t test___riscv_vmulhsu_vx_i64m1_tu(vint64m1_t merge,vint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i64m1_tu(merge,op1,op2,32); +} + + +vint64m2_t test___riscv_vmulhsu_vx_i64m2_tu(vint64m2_t merge,vint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i64m2_tu(merge,op1,op2,32); +} + + +vint64m4_t test___riscv_vmulhsu_vx_i64m4_tu(vint64m4_t merge,vint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i64m4_tu(merge,op1,op2,32); +} + + +vint64m8_t test___riscv_vmulhsu_vx_i64m8_tu(vint64m8_t merge,vint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i64m8_tu(merge,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vmulhsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 4 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmulhsu_vx_tu_rv64-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmulhsu_vx_tu_rv64-1.c new file mode 100644 index 00000000000..78a179539d6 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmulhsu_vx_tu_rv64-1.c @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vmulhsu_vx_i8mf8_tu(vint8mf8_t merge,vint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i8mf8_tu(merge,op1,op2,vl); +} + + +vint8mf4_t test___riscv_vmulhsu_vx_i8mf4_tu(vint8mf4_t merge,vint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i8mf4_tu(merge,op1,op2,vl); +} + + +vint8mf2_t test___riscv_vmulhsu_vx_i8mf2_tu(vint8mf2_t merge,vint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i8mf2_tu(merge,op1,op2,vl); +} + + +vint8m1_t test___riscv_vmulhsu_vx_i8m1_tu(vint8m1_t merge,vint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i8m1_tu(merge,op1,op2,vl); +} + + +vint8m2_t test___riscv_vmulhsu_vx_i8m2_tu(vint8m2_t merge,vint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i8m2_tu(merge,op1,op2,vl); +} + + +vint8m4_t test___riscv_vmulhsu_vx_i8m4_tu(vint8m4_t merge,vint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i8m4_tu(merge,op1,op2,vl); +} + + +vint8m8_t test___riscv_vmulhsu_vx_i8m8_tu(vint8m8_t merge,vint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i8m8_tu(merge,op1,op2,vl); +} + + +vint16mf4_t test___riscv_vmulhsu_vx_i16mf4_tu(vint16mf4_t merge,vint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i16mf4_tu(merge,op1,op2,vl); +} + + +vint16mf2_t test___riscv_vmulhsu_vx_i16mf2_tu(vint16mf2_t merge,vint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i16mf2_tu(merge,op1,op2,vl); +} + + +vint16m1_t test___riscv_vmulhsu_vx_i16m1_tu(vint16m1_t merge,vint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i16m1_tu(merge,op1,op2,vl); +} + + +vint16m2_t test___riscv_vmulhsu_vx_i16m2_tu(vint16m2_t merge,vint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i16m2_tu(merge,op1,op2,vl); +} + + +vint16m4_t test___riscv_vmulhsu_vx_i16m4_tu(vint16m4_t merge,vint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i16m4_tu(merge,op1,op2,vl); +} + + +vint16m8_t test___riscv_vmulhsu_vx_i16m8_tu(vint16m8_t merge,vint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i16m8_tu(merge,op1,op2,vl); +} + + +vint32mf2_t test___riscv_vmulhsu_vx_i32mf2_tu(vint32mf2_t merge,vint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i32mf2_tu(merge,op1,op2,vl); +} + + +vint32m1_t test___riscv_vmulhsu_vx_i32m1_tu(vint32m1_t merge,vint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i32m1_tu(merge,op1,op2,vl); +} + + +vint32m2_t test___riscv_vmulhsu_vx_i32m2_tu(vint32m2_t merge,vint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i32m2_tu(merge,op1,op2,vl); +} + + +vint32m4_t test___riscv_vmulhsu_vx_i32m4_tu(vint32m4_t merge,vint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i32m4_tu(merge,op1,op2,vl); +} + + +vint32m8_t test___riscv_vmulhsu_vx_i32m8_tu(vint32m8_t merge,vint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i32m8_tu(merge,op1,op2,vl); +} + + +vint64m1_t test___riscv_vmulhsu_vx_i64m1_tu(vint64m1_t merge,vint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i64m1_tu(merge,op1,op2,vl); +} + + +vint64m2_t test___riscv_vmulhsu_vx_i64m2_tu(vint64m2_t merge,vint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i64m2_tu(merge,op1,op2,vl); +} + + +vint64m4_t test___riscv_vmulhsu_vx_i64m4_tu(vint64m4_t merge,vint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i64m4_tu(merge,op1,op2,vl); +} + + +vint64m8_t test___riscv_vmulhsu_vx_i64m8_tu(vint64m8_t merge,vint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i64m8_tu(merge,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmulhsu_vx_tu_rv64-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmulhsu_vx_tu_rv64-2.c new file mode 100644 index 00000000000..b5edc1973db --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmulhsu_vx_tu_rv64-2.c @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vmulhsu_vx_i8mf8_tu(vint8mf8_t merge,vint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i8mf8_tu(merge,op1,op2,31); +} + + +vint8mf4_t test___riscv_vmulhsu_vx_i8mf4_tu(vint8mf4_t merge,vint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i8mf4_tu(merge,op1,op2,31); +} + + +vint8mf2_t test___riscv_vmulhsu_vx_i8mf2_tu(vint8mf2_t merge,vint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i8mf2_tu(merge,op1,op2,31); +} + + +vint8m1_t test___riscv_vmulhsu_vx_i8m1_tu(vint8m1_t merge,vint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i8m1_tu(merge,op1,op2,31); +} + + +vint8m2_t test___riscv_vmulhsu_vx_i8m2_tu(vint8m2_t merge,vint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i8m2_tu(merge,op1,op2,31); +} + + +vint8m4_t test___riscv_vmulhsu_vx_i8m4_tu(vint8m4_t merge,vint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i8m4_tu(merge,op1,op2,31); +} + + +vint8m8_t test___riscv_vmulhsu_vx_i8m8_tu(vint8m8_t merge,vint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i8m8_tu(merge,op1,op2,31); +} + + +vint16mf4_t test___riscv_vmulhsu_vx_i16mf4_tu(vint16mf4_t merge,vint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i16mf4_tu(merge,op1,op2,31); +} + + +vint16mf2_t test___riscv_vmulhsu_vx_i16mf2_tu(vint16mf2_t merge,vint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i16mf2_tu(merge,op1,op2,31); +} + + +vint16m1_t test___riscv_vmulhsu_vx_i16m1_tu(vint16m1_t merge,vint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i16m1_tu(merge,op1,op2,31); +} + + +vint16m2_t test___riscv_vmulhsu_vx_i16m2_tu(vint16m2_t merge,vint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i16m2_tu(merge,op1,op2,31); +} + + +vint16m4_t test___riscv_vmulhsu_vx_i16m4_tu(vint16m4_t merge,vint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i16m4_tu(merge,op1,op2,31); +} + + +vint16m8_t test___riscv_vmulhsu_vx_i16m8_tu(vint16m8_t merge,vint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i16m8_tu(merge,op1,op2,31); +} + + +vint32mf2_t test___riscv_vmulhsu_vx_i32mf2_tu(vint32mf2_t merge,vint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i32mf2_tu(merge,op1,op2,31); +} + + +vint32m1_t test___riscv_vmulhsu_vx_i32m1_tu(vint32m1_t merge,vint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i32m1_tu(merge,op1,op2,31); +} + + +vint32m2_t test___riscv_vmulhsu_vx_i32m2_tu(vint32m2_t merge,vint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i32m2_tu(merge,op1,op2,31); +} + + +vint32m4_t test___riscv_vmulhsu_vx_i32m4_tu(vint32m4_t merge,vint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i32m4_tu(merge,op1,op2,31); +} + + +vint32m8_t test___riscv_vmulhsu_vx_i32m8_tu(vint32m8_t merge,vint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i32m8_tu(merge,op1,op2,31); +} + + +vint64m1_t test___riscv_vmulhsu_vx_i64m1_tu(vint64m1_t merge,vint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i64m1_tu(merge,op1,op2,31); +} + + +vint64m2_t test___riscv_vmulhsu_vx_i64m2_tu(vint64m2_t merge,vint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i64m2_tu(merge,op1,op2,31); +} + + +vint64m4_t test___riscv_vmulhsu_vx_i64m4_tu(vint64m4_t merge,vint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i64m4_tu(merge,op1,op2,31); +} + + +vint64m8_t test___riscv_vmulhsu_vx_i64m8_tu(vint64m8_t merge,vint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i64m8_tu(merge,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmulhsu_vx_tu_rv64-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmulhsu_vx_tu_rv64-3.c new file mode 100644 index 00000000000..449e58494fb --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmulhsu_vx_tu_rv64-3.c @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vmulhsu_vx_i8mf8_tu(vint8mf8_t merge,vint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i8mf8_tu(merge,op1,op2,32); +} + + +vint8mf4_t test___riscv_vmulhsu_vx_i8mf4_tu(vint8mf4_t merge,vint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i8mf4_tu(merge,op1,op2,32); +} + + +vint8mf2_t test___riscv_vmulhsu_vx_i8mf2_tu(vint8mf2_t merge,vint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i8mf2_tu(merge,op1,op2,32); +} + + +vint8m1_t test___riscv_vmulhsu_vx_i8m1_tu(vint8m1_t merge,vint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i8m1_tu(merge,op1,op2,32); +} + + +vint8m2_t test___riscv_vmulhsu_vx_i8m2_tu(vint8m2_t merge,vint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i8m2_tu(merge,op1,op2,32); +} + + +vint8m4_t test___riscv_vmulhsu_vx_i8m4_tu(vint8m4_t merge,vint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i8m4_tu(merge,op1,op2,32); +} + + +vint8m8_t test___riscv_vmulhsu_vx_i8m8_tu(vint8m8_t merge,vint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i8m8_tu(merge,op1,op2,32); +} + + +vint16mf4_t test___riscv_vmulhsu_vx_i16mf4_tu(vint16mf4_t merge,vint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i16mf4_tu(merge,op1,op2,32); +} + + +vint16mf2_t test___riscv_vmulhsu_vx_i16mf2_tu(vint16mf2_t merge,vint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i16mf2_tu(merge,op1,op2,32); +} + + +vint16m1_t test___riscv_vmulhsu_vx_i16m1_tu(vint16m1_t merge,vint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i16m1_tu(merge,op1,op2,32); +} + + +vint16m2_t test___riscv_vmulhsu_vx_i16m2_tu(vint16m2_t merge,vint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i16m2_tu(merge,op1,op2,32); +} + + +vint16m4_t test___riscv_vmulhsu_vx_i16m4_tu(vint16m4_t merge,vint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i16m4_tu(merge,op1,op2,32); +} + + +vint16m8_t test___riscv_vmulhsu_vx_i16m8_tu(vint16m8_t merge,vint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i16m8_tu(merge,op1,op2,32); +} + + +vint32mf2_t test___riscv_vmulhsu_vx_i32mf2_tu(vint32mf2_t merge,vint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i32mf2_tu(merge,op1,op2,32); +} + + +vint32m1_t test___riscv_vmulhsu_vx_i32m1_tu(vint32m1_t merge,vint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i32m1_tu(merge,op1,op2,32); +} + + +vint32m2_t test___riscv_vmulhsu_vx_i32m2_tu(vint32m2_t merge,vint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i32m2_tu(merge,op1,op2,32); +} + + +vint32m4_t test___riscv_vmulhsu_vx_i32m4_tu(vint32m4_t merge,vint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i32m4_tu(merge,op1,op2,32); +} + + +vint32m8_t test___riscv_vmulhsu_vx_i32m8_tu(vint32m8_t merge,vint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i32m8_tu(merge,op1,op2,32); +} + + +vint64m1_t test___riscv_vmulhsu_vx_i64m1_tu(vint64m1_t merge,vint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i64m1_tu(merge,op1,op2,32); +} + + +vint64m2_t test___riscv_vmulhsu_vx_i64m2_tu(vint64m2_t merge,vint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i64m2_tu(merge,op1,op2,32); +} + + +vint64m4_t test___riscv_vmulhsu_vx_i64m4_tu(vint64m4_t merge,vint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i64m4_tu(merge,op1,op2,32); +} + + +vint64m8_t test___riscv_vmulhsu_vx_i64m8_tu(vint64m8_t merge,vint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i64m8_tu(merge,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmulhsu_vx_tum_rv32-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmulhsu_vx_tum_rv32-1.c new file mode 100644 index 00000000000..3016bf20368 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmulhsu_vx_tum_rv32-1.c @@ -0,0 +1,157 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vmulhsu_vx_i8mf8_tum(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i8mf8_tum(mask,merge,op1,op2,vl); +} + + +vint8mf4_t test___riscv_vmulhsu_vx_i8mf4_tum(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i8mf4_tum(mask,merge,op1,op2,vl); +} + + +vint8mf2_t test___riscv_vmulhsu_vx_i8mf2_tum(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i8mf2_tum(mask,merge,op1,op2,vl); +} + + +vint8m1_t test___riscv_vmulhsu_vx_i8m1_tum(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i8m1_tum(mask,merge,op1,op2,vl); +} + + +vint8m2_t test___riscv_vmulhsu_vx_i8m2_tum(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i8m2_tum(mask,merge,op1,op2,vl); +} + + +vint8m4_t test___riscv_vmulhsu_vx_i8m4_tum(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i8m4_tum(mask,merge,op1,op2,vl); +} + + +vint8m8_t test___riscv_vmulhsu_vx_i8m8_tum(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i8m8_tum(mask,merge,op1,op2,vl); +} + + +vint16mf4_t test___riscv_vmulhsu_vx_i16mf4_tum(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i16mf4_tum(mask,merge,op1,op2,vl); +} + + +vint16mf2_t test___riscv_vmulhsu_vx_i16mf2_tum(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i16mf2_tum(mask,merge,op1,op2,vl); +} + + +vint16m1_t test___riscv_vmulhsu_vx_i16m1_tum(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i16m1_tum(mask,merge,op1,op2,vl); +} + + +vint16m2_t test___riscv_vmulhsu_vx_i16m2_tum(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i16m2_tum(mask,merge,op1,op2,vl); +} + + +vint16m4_t test___riscv_vmulhsu_vx_i16m4_tum(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i16m4_tum(mask,merge,op1,op2,vl); +} + + +vint16m8_t test___riscv_vmulhsu_vx_i16m8_tum(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i16m8_tum(mask,merge,op1,op2,vl); +} + + +vint32mf2_t test___riscv_vmulhsu_vx_i32mf2_tum(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i32mf2_tum(mask,merge,op1,op2,vl); +} + + +vint32m1_t test___riscv_vmulhsu_vx_i32m1_tum(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i32m1_tum(mask,merge,op1,op2,vl); +} + + +vint32m2_t test___riscv_vmulhsu_vx_i32m2_tum(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i32m2_tum(mask,merge,op1,op2,vl); +} + + +vint32m4_t test___riscv_vmulhsu_vx_i32m4_tum(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i32m4_tum(mask,merge,op1,op2,vl); +} + + +vint32m8_t test___riscv_vmulhsu_vx_i32m8_tum(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i32m8_tum(mask,merge,op1,op2,vl); +} + + +vint64m1_t test___riscv_vmulhsu_vx_i64m1_tum(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i64m1_tum(mask,merge,op1,op2,vl); +} + + +vint64m2_t test___riscv_vmulhsu_vx_i64m2_tum(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i64m2_tum(mask,merge,op1,op2,vl); +} + + +vint64m4_t test___riscv_vmulhsu_vx_i64m4_tum(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i64m4_tum(mask,merge,op1,op2,vl); +} + + +vint64m8_t test___riscv_vmulhsu_vx_i64m8_tum(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i64m8_tum(mask,merge,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vmulhsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 4 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmulhsu_vx_tum_rv32-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmulhsu_vx_tum_rv32-2.c new file mode 100644 index 00000000000..9ccd7c746f2 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmulhsu_vx_tum_rv32-2.c @@ -0,0 +1,157 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vmulhsu_vx_i8mf8_tum(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i8mf8_tum(mask,merge,op1,op2,31); +} + + +vint8mf4_t test___riscv_vmulhsu_vx_i8mf4_tum(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i8mf4_tum(mask,merge,op1,op2,31); +} + + +vint8mf2_t test___riscv_vmulhsu_vx_i8mf2_tum(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i8mf2_tum(mask,merge,op1,op2,31); +} + + +vint8m1_t test___riscv_vmulhsu_vx_i8m1_tum(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i8m1_tum(mask,merge,op1,op2,31); +} + + +vint8m2_t test___riscv_vmulhsu_vx_i8m2_tum(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i8m2_tum(mask,merge,op1,op2,31); +} + + +vint8m4_t test___riscv_vmulhsu_vx_i8m4_tum(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i8m4_tum(mask,merge,op1,op2,31); +} + + +vint8m8_t test___riscv_vmulhsu_vx_i8m8_tum(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i8m8_tum(mask,merge,op1,op2,31); +} + + +vint16mf4_t test___riscv_vmulhsu_vx_i16mf4_tum(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i16mf4_tum(mask,merge,op1,op2,31); +} + + +vint16mf2_t test___riscv_vmulhsu_vx_i16mf2_tum(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i16mf2_tum(mask,merge,op1,op2,31); +} + + +vint16m1_t test___riscv_vmulhsu_vx_i16m1_tum(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i16m1_tum(mask,merge,op1,op2,31); +} + + +vint16m2_t test___riscv_vmulhsu_vx_i16m2_tum(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i16m2_tum(mask,merge,op1,op2,31); +} + + +vint16m4_t test___riscv_vmulhsu_vx_i16m4_tum(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i16m4_tum(mask,merge,op1,op2,31); +} + + +vint16m8_t test___riscv_vmulhsu_vx_i16m8_tum(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i16m8_tum(mask,merge,op1,op2,31); +} + + +vint32mf2_t test___riscv_vmulhsu_vx_i32mf2_tum(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i32mf2_tum(mask,merge,op1,op2,31); +} + + +vint32m1_t test___riscv_vmulhsu_vx_i32m1_tum(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i32m1_tum(mask,merge,op1,op2,31); +} + + +vint32m2_t test___riscv_vmulhsu_vx_i32m2_tum(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i32m2_tum(mask,merge,op1,op2,31); +} + + +vint32m4_t test___riscv_vmulhsu_vx_i32m4_tum(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i32m4_tum(mask,merge,op1,op2,31); +} + + +vint32m8_t test___riscv_vmulhsu_vx_i32m8_tum(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i32m8_tum(mask,merge,op1,op2,31); +} + + +vint64m1_t test___riscv_vmulhsu_vx_i64m1_tum(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i64m1_tum(mask,merge,op1,op2,31); +} + + +vint64m2_t test___riscv_vmulhsu_vx_i64m2_tum(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i64m2_tum(mask,merge,op1,op2,31); +} + + +vint64m4_t test___riscv_vmulhsu_vx_i64m4_tum(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i64m4_tum(mask,merge,op1,op2,31); +} + + +vint64m8_t test___riscv_vmulhsu_vx_i64m8_tum(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i64m8_tum(mask,merge,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vmulhsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 4 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmulhsu_vx_tum_rv32-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmulhsu_vx_tum_rv32-3.c new file mode 100644 index 00000000000..c6c2239826a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmulhsu_vx_tum_rv32-3.c @@ -0,0 +1,157 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vmulhsu_vx_i8mf8_tum(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i8mf8_tum(mask,merge,op1,op2,32); +} + + +vint8mf4_t test___riscv_vmulhsu_vx_i8mf4_tum(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i8mf4_tum(mask,merge,op1,op2,32); +} + + +vint8mf2_t test___riscv_vmulhsu_vx_i8mf2_tum(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i8mf2_tum(mask,merge,op1,op2,32); +} + + +vint8m1_t test___riscv_vmulhsu_vx_i8m1_tum(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i8m1_tum(mask,merge,op1,op2,32); +} + + +vint8m2_t test___riscv_vmulhsu_vx_i8m2_tum(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i8m2_tum(mask,merge,op1,op2,32); +} + + +vint8m4_t test___riscv_vmulhsu_vx_i8m4_tum(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i8m4_tum(mask,merge,op1,op2,32); +} + + +vint8m8_t test___riscv_vmulhsu_vx_i8m8_tum(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i8m8_tum(mask,merge,op1,op2,32); +} + + +vint16mf4_t test___riscv_vmulhsu_vx_i16mf4_tum(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i16mf4_tum(mask,merge,op1,op2,32); +} + + +vint16mf2_t test___riscv_vmulhsu_vx_i16mf2_tum(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i16mf2_tum(mask,merge,op1,op2,32); +} + + +vint16m1_t test___riscv_vmulhsu_vx_i16m1_tum(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i16m1_tum(mask,merge,op1,op2,32); +} + + +vint16m2_t test___riscv_vmulhsu_vx_i16m2_tum(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i16m2_tum(mask,merge,op1,op2,32); +} + + +vint16m4_t test___riscv_vmulhsu_vx_i16m4_tum(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i16m4_tum(mask,merge,op1,op2,32); +} + + +vint16m8_t test___riscv_vmulhsu_vx_i16m8_tum(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i16m8_tum(mask,merge,op1,op2,32); +} + + +vint32mf2_t test___riscv_vmulhsu_vx_i32mf2_tum(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i32mf2_tum(mask,merge,op1,op2,32); +} + + +vint32m1_t test___riscv_vmulhsu_vx_i32m1_tum(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i32m1_tum(mask,merge,op1,op2,32); +} + + +vint32m2_t test___riscv_vmulhsu_vx_i32m2_tum(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i32m2_tum(mask,merge,op1,op2,32); +} + + +vint32m4_t test___riscv_vmulhsu_vx_i32m4_tum(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i32m4_tum(mask,merge,op1,op2,32); +} + + +vint32m8_t test___riscv_vmulhsu_vx_i32m8_tum(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i32m8_tum(mask,merge,op1,op2,32); +} + + +vint64m1_t test___riscv_vmulhsu_vx_i64m1_tum(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i64m1_tum(mask,merge,op1,op2,32); +} + + +vint64m2_t test___riscv_vmulhsu_vx_i64m2_tum(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i64m2_tum(mask,merge,op1,op2,32); +} + + +vint64m4_t test___riscv_vmulhsu_vx_i64m4_tum(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i64m4_tum(mask,merge,op1,op2,32); +} + + +vint64m8_t test___riscv_vmulhsu_vx_i64m8_tum(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i64m8_tum(mask,merge,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vmulhsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 4 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmulhsu_vx_tum_rv64-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmulhsu_vx_tum_rv64-1.c new file mode 100644 index 00000000000..6101b300c38 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmulhsu_vx_tum_rv64-1.c @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vmulhsu_vx_i8mf8_tum(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i8mf8_tum(mask,merge,op1,op2,vl); +} + + +vint8mf4_t test___riscv_vmulhsu_vx_i8mf4_tum(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i8mf4_tum(mask,merge,op1,op2,vl); +} + + +vint8mf2_t test___riscv_vmulhsu_vx_i8mf2_tum(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i8mf2_tum(mask,merge,op1,op2,vl); +} + + +vint8m1_t test___riscv_vmulhsu_vx_i8m1_tum(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i8m1_tum(mask,merge,op1,op2,vl); +} + + +vint8m2_t test___riscv_vmulhsu_vx_i8m2_tum(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i8m2_tum(mask,merge,op1,op2,vl); +} + + +vint8m4_t test___riscv_vmulhsu_vx_i8m4_tum(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i8m4_tum(mask,merge,op1,op2,vl); +} + + +vint8m8_t test___riscv_vmulhsu_vx_i8m8_tum(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i8m8_tum(mask,merge,op1,op2,vl); +} + + +vint16mf4_t test___riscv_vmulhsu_vx_i16mf4_tum(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i16mf4_tum(mask,merge,op1,op2,vl); +} + + +vint16mf2_t test___riscv_vmulhsu_vx_i16mf2_tum(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i16mf2_tum(mask,merge,op1,op2,vl); +} + + +vint16m1_t test___riscv_vmulhsu_vx_i16m1_tum(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i16m1_tum(mask,merge,op1,op2,vl); +} + + +vint16m2_t test___riscv_vmulhsu_vx_i16m2_tum(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i16m2_tum(mask,merge,op1,op2,vl); +} + + +vint16m4_t test___riscv_vmulhsu_vx_i16m4_tum(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i16m4_tum(mask,merge,op1,op2,vl); +} + + +vint16m8_t test___riscv_vmulhsu_vx_i16m8_tum(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i16m8_tum(mask,merge,op1,op2,vl); +} + + +vint32mf2_t test___riscv_vmulhsu_vx_i32mf2_tum(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i32mf2_tum(mask,merge,op1,op2,vl); +} + + +vint32m1_t test___riscv_vmulhsu_vx_i32m1_tum(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i32m1_tum(mask,merge,op1,op2,vl); +} + + +vint32m2_t test___riscv_vmulhsu_vx_i32m2_tum(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i32m2_tum(mask,merge,op1,op2,vl); +} + + +vint32m4_t test___riscv_vmulhsu_vx_i32m4_tum(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i32m4_tum(mask,merge,op1,op2,vl); +} + + +vint32m8_t test___riscv_vmulhsu_vx_i32m8_tum(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i32m8_tum(mask,merge,op1,op2,vl); +} + + +vint64m1_t test___riscv_vmulhsu_vx_i64m1_tum(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i64m1_tum(mask,merge,op1,op2,vl); +} + + +vint64m2_t test___riscv_vmulhsu_vx_i64m2_tum(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i64m2_tum(mask,merge,op1,op2,vl); +} + + +vint64m4_t test___riscv_vmulhsu_vx_i64m4_tum(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i64m4_tum(mask,merge,op1,op2,vl); +} + + +vint64m8_t test___riscv_vmulhsu_vx_i64m8_tum(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i64m8_tum(mask,merge,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmulhsu_vx_tum_rv64-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmulhsu_vx_tum_rv64-2.c new file mode 100644 index 00000000000..f54c9e0ef84 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmulhsu_vx_tum_rv64-2.c @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vmulhsu_vx_i8mf8_tum(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i8mf8_tum(mask,merge,op1,op2,31); +} + + +vint8mf4_t test___riscv_vmulhsu_vx_i8mf4_tum(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i8mf4_tum(mask,merge,op1,op2,31); +} + + +vint8mf2_t test___riscv_vmulhsu_vx_i8mf2_tum(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i8mf2_tum(mask,merge,op1,op2,31); +} + + +vint8m1_t test___riscv_vmulhsu_vx_i8m1_tum(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i8m1_tum(mask,merge,op1,op2,31); +} + + +vint8m2_t test___riscv_vmulhsu_vx_i8m2_tum(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i8m2_tum(mask,merge,op1,op2,31); +} + + +vint8m4_t test___riscv_vmulhsu_vx_i8m4_tum(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i8m4_tum(mask,merge,op1,op2,31); +} + + +vint8m8_t test___riscv_vmulhsu_vx_i8m8_tum(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i8m8_tum(mask,merge,op1,op2,31); +} + + +vint16mf4_t test___riscv_vmulhsu_vx_i16mf4_tum(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i16mf4_tum(mask,merge,op1,op2,31); +} + + +vint16mf2_t test___riscv_vmulhsu_vx_i16mf2_tum(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i16mf2_tum(mask,merge,op1,op2,31); +} + + +vint16m1_t test___riscv_vmulhsu_vx_i16m1_tum(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i16m1_tum(mask,merge,op1,op2,31); +} + + +vint16m2_t test___riscv_vmulhsu_vx_i16m2_tum(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i16m2_tum(mask,merge,op1,op2,31); +} + + +vint16m4_t test___riscv_vmulhsu_vx_i16m4_tum(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i16m4_tum(mask,merge,op1,op2,31); +} + + +vint16m8_t test___riscv_vmulhsu_vx_i16m8_tum(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i16m8_tum(mask,merge,op1,op2,31); +} + + +vint32mf2_t test___riscv_vmulhsu_vx_i32mf2_tum(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i32mf2_tum(mask,merge,op1,op2,31); +} + + +vint32m1_t test___riscv_vmulhsu_vx_i32m1_tum(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i32m1_tum(mask,merge,op1,op2,31); +} + + +vint32m2_t test___riscv_vmulhsu_vx_i32m2_tum(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i32m2_tum(mask,merge,op1,op2,31); +} + + +vint32m4_t test___riscv_vmulhsu_vx_i32m4_tum(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i32m4_tum(mask,merge,op1,op2,31); +} + + +vint32m8_t test___riscv_vmulhsu_vx_i32m8_tum(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i32m8_tum(mask,merge,op1,op2,31); +} + + +vint64m1_t test___riscv_vmulhsu_vx_i64m1_tum(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i64m1_tum(mask,merge,op1,op2,31); +} + + +vint64m2_t test___riscv_vmulhsu_vx_i64m2_tum(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i64m2_tum(mask,merge,op1,op2,31); +} + + +vint64m4_t test___riscv_vmulhsu_vx_i64m4_tum(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i64m4_tum(mask,merge,op1,op2,31); +} + + +vint64m8_t test___riscv_vmulhsu_vx_i64m8_tum(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i64m8_tum(mask,merge,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmulhsu_vx_tum_rv64-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmulhsu_vx_tum_rv64-3.c new file mode 100644 index 00000000000..e120b8ddbdf --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmulhsu_vx_tum_rv64-3.c @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vmulhsu_vx_i8mf8_tum(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i8mf8_tum(mask,merge,op1,op2,32); +} + + +vint8mf4_t test___riscv_vmulhsu_vx_i8mf4_tum(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i8mf4_tum(mask,merge,op1,op2,32); +} + + +vint8mf2_t test___riscv_vmulhsu_vx_i8mf2_tum(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i8mf2_tum(mask,merge,op1,op2,32); +} + + +vint8m1_t test___riscv_vmulhsu_vx_i8m1_tum(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i8m1_tum(mask,merge,op1,op2,32); +} + + +vint8m2_t test___riscv_vmulhsu_vx_i8m2_tum(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i8m2_tum(mask,merge,op1,op2,32); +} + + +vint8m4_t test___riscv_vmulhsu_vx_i8m4_tum(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i8m4_tum(mask,merge,op1,op2,32); +} + + +vint8m8_t test___riscv_vmulhsu_vx_i8m8_tum(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i8m8_tum(mask,merge,op1,op2,32); +} + + +vint16mf4_t test___riscv_vmulhsu_vx_i16mf4_tum(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i16mf4_tum(mask,merge,op1,op2,32); +} + + +vint16mf2_t test___riscv_vmulhsu_vx_i16mf2_tum(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i16mf2_tum(mask,merge,op1,op2,32); +} + + +vint16m1_t test___riscv_vmulhsu_vx_i16m1_tum(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i16m1_tum(mask,merge,op1,op2,32); +} + + +vint16m2_t test___riscv_vmulhsu_vx_i16m2_tum(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i16m2_tum(mask,merge,op1,op2,32); +} + + +vint16m4_t test___riscv_vmulhsu_vx_i16m4_tum(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i16m4_tum(mask,merge,op1,op2,32); +} + + +vint16m8_t test___riscv_vmulhsu_vx_i16m8_tum(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i16m8_tum(mask,merge,op1,op2,32); +} + + +vint32mf2_t test___riscv_vmulhsu_vx_i32mf2_tum(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i32mf2_tum(mask,merge,op1,op2,32); +} + + +vint32m1_t test___riscv_vmulhsu_vx_i32m1_tum(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i32m1_tum(mask,merge,op1,op2,32); +} + + +vint32m2_t test___riscv_vmulhsu_vx_i32m2_tum(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i32m2_tum(mask,merge,op1,op2,32); +} + + +vint32m4_t test___riscv_vmulhsu_vx_i32m4_tum(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i32m4_tum(mask,merge,op1,op2,32); +} + + +vint32m8_t test___riscv_vmulhsu_vx_i32m8_tum(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i32m8_tum(mask,merge,op1,op2,32); +} + + +vint64m1_t test___riscv_vmulhsu_vx_i64m1_tum(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i64m1_tum(mask,merge,op1,op2,32); +} + + +vint64m2_t test___riscv_vmulhsu_vx_i64m2_tum(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i64m2_tum(mask,merge,op1,op2,32); +} + + +vint64m4_t test___riscv_vmulhsu_vx_i64m4_tum(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i64m4_tum(mask,merge,op1,op2,32); +} + + +vint64m8_t test___riscv_vmulhsu_vx_i64m8_tum(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i64m8_tum(mask,merge,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmulhsu_vx_tumu_rv32-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmulhsu_vx_tumu_rv32-1.c new file mode 100644 index 00000000000..6e6178bb9be --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmulhsu_vx_tumu_rv32-1.c @@ -0,0 +1,157 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vmulhsu_vx_i8mf8_tumu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i8mf8_tumu(mask,merge,op1,op2,vl); +} + + +vint8mf4_t test___riscv_vmulhsu_vx_i8mf4_tumu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i8mf4_tumu(mask,merge,op1,op2,vl); +} + + +vint8mf2_t test___riscv_vmulhsu_vx_i8mf2_tumu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i8mf2_tumu(mask,merge,op1,op2,vl); +} + + +vint8m1_t test___riscv_vmulhsu_vx_i8m1_tumu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i8m1_tumu(mask,merge,op1,op2,vl); +} + + +vint8m2_t test___riscv_vmulhsu_vx_i8m2_tumu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i8m2_tumu(mask,merge,op1,op2,vl); +} + + +vint8m4_t test___riscv_vmulhsu_vx_i8m4_tumu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i8m4_tumu(mask,merge,op1,op2,vl); +} + + +vint8m8_t test___riscv_vmulhsu_vx_i8m8_tumu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i8m8_tumu(mask,merge,op1,op2,vl); +} + + +vint16mf4_t test___riscv_vmulhsu_vx_i16mf4_tumu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i16mf4_tumu(mask,merge,op1,op2,vl); +} + + +vint16mf2_t test___riscv_vmulhsu_vx_i16mf2_tumu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i16mf2_tumu(mask,merge,op1,op2,vl); +} + + +vint16m1_t test___riscv_vmulhsu_vx_i16m1_tumu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i16m1_tumu(mask,merge,op1,op2,vl); +} + + +vint16m2_t test___riscv_vmulhsu_vx_i16m2_tumu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i16m2_tumu(mask,merge,op1,op2,vl); +} + + +vint16m4_t test___riscv_vmulhsu_vx_i16m4_tumu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i16m4_tumu(mask,merge,op1,op2,vl); +} + + +vint16m8_t test___riscv_vmulhsu_vx_i16m8_tumu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i16m8_tumu(mask,merge,op1,op2,vl); +} + + +vint32mf2_t test___riscv_vmulhsu_vx_i32mf2_tumu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i32mf2_tumu(mask,merge,op1,op2,vl); +} + + +vint32m1_t test___riscv_vmulhsu_vx_i32m1_tumu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i32m1_tumu(mask,merge,op1,op2,vl); +} + + +vint32m2_t test___riscv_vmulhsu_vx_i32m2_tumu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i32m2_tumu(mask,merge,op1,op2,vl); +} + + +vint32m4_t test___riscv_vmulhsu_vx_i32m4_tumu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i32m4_tumu(mask,merge,op1,op2,vl); +} + + +vint32m8_t test___riscv_vmulhsu_vx_i32m8_tumu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i32m8_tumu(mask,merge,op1,op2,vl); +} + + +vint64m1_t test___riscv_vmulhsu_vx_i64m1_tumu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i64m1_tumu(mask,merge,op1,op2,vl); +} + + +vint64m2_t test___riscv_vmulhsu_vx_i64m2_tumu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i64m2_tumu(mask,merge,op1,op2,vl); +} + + +vint64m4_t test___riscv_vmulhsu_vx_i64m4_tumu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i64m4_tumu(mask,merge,op1,op2,vl); +} + + +vint64m8_t test___riscv_vmulhsu_vx_i64m8_tumu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i64m8_tumu(mask,merge,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vmulhsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 4 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmulhsu_vx_tumu_rv32-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmulhsu_vx_tumu_rv32-2.c new file mode 100644 index 00000000000..67a6634f858 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmulhsu_vx_tumu_rv32-2.c @@ -0,0 +1,157 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vmulhsu_vx_i8mf8_tumu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i8mf8_tumu(mask,merge,op1,op2,31); +} + + +vint8mf4_t test___riscv_vmulhsu_vx_i8mf4_tumu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i8mf4_tumu(mask,merge,op1,op2,31); +} + + +vint8mf2_t test___riscv_vmulhsu_vx_i8mf2_tumu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i8mf2_tumu(mask,merge,op1,op2,31); +} + + +vint8m1_t test___riscv_vmulhsu_vx_i8m1_tumu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i8m1_tumu(mask,merge,op1,op2,31); +} + + +vint8m2_t test___riscv_vmulhsu_vx_i8m2_tumu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i8m2_tumu(mask,merge,op1,op2,31); +} + + +vint8m4_t test___riscv_vmulhsu_vx_i8m4_tumu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i8m4_tumu(mask,merge,op1,op2,31); +} + + +vint8m8_t test___riscv_vmulhsu_vx_i8m8_tumu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i8m8_tumu(mask,merge,op1,op2,31); +} + + +vint16mf4_t test___riscv_vmulhsu_vx_i16mf4_tumu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i16mf4_tumu(mask,merge,op1,op2,31); +} + + +vint16mf2_t test___riscv_vmulhsu_vx_i16mf2_tumu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i16mf2_tumu(mask,merge,op1,op2,31); +} + + +vint16m1_t test___riscv_vmulhsu_vx_i16m1_tumu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i16m1_tumu(mask,merge,op1,op2,31); +} + + +vint16m2_t test___riscv_vmulhsu_vx_i16m2_tumu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i16m2_tumu(mask,merge,op1,op2,31); +} + + +vint16m4_t test___riscv_vmulhsu_vx_i16m4_tumu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i16m4_tumu(mask,merge,op1,op2,31); +} + + +vint16m8_t test___riscv_vmulhsu_vx_i16m8_tumu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i16m8_tumu(mask,merge,op1,op2,31); +} + + +vint32mf2_t test___riscv_vmulhsu_vx_i32mf2_tumu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i32mf2_tumu(mask,merge,op1,op2,31); +} + + +vint32m1_t test___riscv_vmulhsu_vx_i32m1_tumu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i32m1_tumu(mask,merge,op1,op2,31); +} + + +vint32m2_t test___riscv_vmulhsu_vx_i32m2_tumu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i32m2_tumu(mask,merge,op1,op2,31); +} + + +vint32m4_t test___riscv_vmulhsu_vx_i32m4_tumu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i32m4_tumu(mask,merge,op1,op2,31); +} + + +vint32m8_t test___riscv_vmulhsu_vx_i32m8_tumu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i32m8_tumu(mask,merge,op1,op2,31); +} + + +vint64m1_t test___riscv_vmulhsu_vx_i64m1_tumu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i64m1_tumu(mask,merge,op1,op2,31); +} + + +vint64m2_t test___riscv_vmulhsu_vx_i64m2_tumu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i64m2_tumu(mask,merge,op1,op2,31); +} + + +vint64m4_t test___riscv_vmulhsu_vx_i64m4_tumu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i64m4_tumu(mask,merge,op1,op2,31); +} + + +vint64m8_t test___riscv_vmulhsu_vx_i64m8_tumu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i64m8_tumu(mask,merge,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vmulhsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 4 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmulhsu_vx_tumu_rv32-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmulhsu_vx_tumu_rv32-3.c new file mode 100644 index 00000000000..06a77d688a5 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmulhsu_vx_tumu_rv32-3.c @@ -0,0 +1,157 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vmulhsu_vx_i8mf8_tumu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i8mf8_tumu(mask,merge,op1,op2,32); +} + + +vint8mf4_t test___riscv_vmulhsu_vx_i8mf4_tumu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i8mf4_tumu(mask,merge,op1,op2,32); +} + + +vint8mf2_t test___riscv_vmulhsu_vx_i8mf2_tumu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i8mf2_tumu(mask,merge,op1,op2,32); +} + + +vint8m1_t test___riscv_vmulhsu_vx_i8m1_tumu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i8m1_tumu(mask,merge,op1,op2,32); +} + + +vint8m2_t test___riscv_vmulhsu_vx_i8m2_tumu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i8m2_tumu(mask,merge,op1,op2,32); +} + + +vint8m4_t test___riscv_vmulhsu_vx_i8m4_tumu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i8m4_tumu(mask,merge,op1,op2,32); +} + + +vint8m8_t test___riscv_vmulhsu_vx_i8m8_tumu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i8m8_tumu(mask,merge,op1,op2,32); +} + + +vint16mf4_t test___riscv_vmulhsu_vx_i16mf4_tumu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i16mf4_tumu(mask,merge,op1,op2,32); +} + + +vint16mf2_t test___riscv_vmulhsu_vx_i16mf2_tumu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i16mf2_tumu(mask,merge,op1,op2,32); +} + + +vint16m1_t test___riscv_vmulhsu_vx_i16m1_tumu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i16m1_tumu(mask,merge,op1,op2,32); +} + + +vint16m2_t test___riscv_vmulhsu_vx_i16m2_tumu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i16m2_tumu(mask,merge,op1,op2,32); +} + + +vint16m4_t test___riscv_vmulhsu_vx_i16m4_tumu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i16m4_tumu(mask,merge,op1,op2,32); +} + + +vint16m8_t test___riscv_vmulhsu_vx_i16m8_tumu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i16m8_tumu(mask,merge,op1,op2,32); +} + + +vint32mf2_t test___riscv_vmulhsu_vx_i32mf2_tumu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i32mf2_tumu(mask,merge,op1,op2,32); +} + + +vint32m1_t test___riscv_vmulhsu_vx_i32m1_tumu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i32m1_tumu(mask,merge,op1,op2,32); +} + + +vint32m2_t test___riscv_vmulhsu_vx_i32m2_tumu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i32m2_tumu(mask,merge,op1,op2,32); +} + + +vint32m4_t test___riscv_vmulhsu_vx_i32m4_tumu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i32m4_tumu(mask,merge,op1,op2,32); +} + + +vint32m8_t test___riscv_vmulhsu_vx_i32m8_tumu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i32m8_tumu(mask,merge,op1,op2,32); +} + + +vint64m1_t test___riscv_vmulhsu_vx_i64m1_tumu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i64m1_tumu(mask,merge,op1,op2,32); +} + + +vint64m2_t test___riscv_vmulhsu_vx_i64m2_tumu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i64m2_tumu(mask,merge,op1,op2,32); +} + + +vint64m4_t test___riscv_vmulhsu_vx_i64m4_tumu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i64m4_tumu(mask,merge,op1,op2,32); +} + + +vint64m8_t test___riscv_vmulhsu_vx_i64m8_tumu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i64m8_tumu(mask,merge,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vmulhsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 4 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmulhsu_vx_tumu_rv64-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmulhsu_vx_tumu_rv64-1.c new file mode 100644 index 00000000000..c9cd08379e7 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmulhsu_vx_tumu_rv64-1.c @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vmulhsu_vx_i8mf8_tumu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i8mf8_tumu(mask,merge,op1,op2,vl); +} + + +vint8mf4_t test___riscv_vmulhsu_vx_i8mf4_tumu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i8mf4_tumu(mask,merge,op1,op2,vl); +} + + +vint8mf2_t test___riscv_vmulhsu_vx_i8mf2_tumu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i8mf2_tumu(mask,merge,op1,op2,vl); +} + + +vint8m1_t test___riscv_vmulhsu_vx_i8m1_tumu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i8m1_tumu(mask,merge,op1,op2,vl); +} + + +vint8m2_t test___riscv_vmulhsu_vx_i8m2_tumu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i8m2_tumu(mask,merge,op1,op2,vl); +} + + +vint8m4_t test___riscv_vmulhsu_vx_i8m4_tumu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i8m4_tumu(mask,merge,op1,op2,vl); +} + + +vint8m8_t test___riscv_vmulhsu_vx_i8m8_tumu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i8m8_tumu(mask,merge,op1,op2,vl); +} + + +vint16mf4_t test___riscv_vmulhsu_vx_i16mf4_tumu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i16mf4_tumu(mask,merge,op1,op2,vl); +} + + +vint16mf2_t test___riscv_vmulhsu_vx_i16mf2_tumu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i16mf2_tumu(mask,merge,op1,op2,vl); +} + + +vint16m1_t test___riscv_vmulhsu_vx_i16m1_tumu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i16m1_tumu(mask,merge,op1,op2,vl); +} + + +vint16m2_t test___riscv_vmulhsu_vx_i16m2_tumu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i16m2_tumu(mask,merge,op1,op2,vl); +} + + +vint16m4_t test___riscv_vmulhsu_vx_i16m4_tumu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i16m4_tumu(mask,merge,op1,op2,vl); +} + + +vint16m8_t test___riscv_vmulhsu_vx_i16m8_tumu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i16m8_tumu(mask,merge,op1,op2,vl); +} + + +vint32mf2_t test___riscv_vmulhsu_vx_i32mf2_tumu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i32mf2_tumu(mask,merge,op1,op2,vl); +} + + +vint32m1_t test___riscv_vmulhsu_vx_i32m1_tumu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i32m1_tumu(mask,merge,op1,op2,vl); +} + + +vint32m2_t test___riscv_vmulhsu_vx_i32m2_tumu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i32m2_tumu(mask,merge,op1,op2,vl); +} + + +vint32m4_t test___riscv_vmulhsu_vx_i32m4_tumu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i32m4_tumu(mask,merge,op1,op2,vl); +} + + +vint32m8_t test___riscv_vmulhsu_vx_i32m8_tumu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i32m8_tumu(mask,merge,op1,op2,vl); +} + + +vint64m1_t test___riscv_vmulhsu_vx_i64m1_tumu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i64m1_tumu(mask,merge,op1,op2,vl); +} + + +vint64m2_t test___riscv_vmulhsu_vx_i64m2_tumu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i64m2_tumu(mask,merge,op1,op2,vl); +} + + +vint64m4_t test___riscv_vmulhsu_vx_i64m4_tumu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i64m4_tumu(mask,merge,op1,op2,vl); +} + + +vint64m8_t test___riscv_vmulhsu_vx_i64m8_tumu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i64m8_tumu(mask,merge,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmulhsu_vx_tumu_rv64-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmulhsu_vx_tumu_rv64-2.c new file mode 100644 index 00000000000..41780ea64b8 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmulhsu_vx_tumu_rv64-2.c @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vmulhsu_vx_i8mf8_tumu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i8mf8_tumu(mask,merge,op1,op2,31); +} + + +vint8mf4_t test___riscv_vmulhsu_vx_i8mf4_tumu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i8mf4_tumu(mask,merge,op1,op2,31); +} + + +vint8mf2_t test___riscv_vmulhsu_vx_i8mf2_tumu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i8mf2_tumu(mask,merge,op1,op2,31); +} + + +vint8m1_t test___riscv_vmulhsu_vx_i8m1_tumu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i8m1_tumu(mask,merge,op1,op2,31); +} + + +vint8m2_t test___riscv_vmulhsu_vx_i8m2_tumu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i8m2_tumu(mask,merge,op1,op2,31); +} + + +vint8m4_t test___riscv_vmulhsu_vx_i8m4_tumu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i8m4_tumu(mask,merge,op1,op2,31); +} + + +vint8m8_t test___riscv_vmulhsu_vx_i8m8_tumu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i8m8_tumu(mask,merge,op1,op2,31); +} + + +vint16mf4_t test___riscv_vmulhsu_vx_i16mf4_tumu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i16mf4_tumu(mask,merge,op1,op2,31); +} + + +vint16mf2_t test___riscv_vmulhsu_vx_i16mf2_tumu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i16mf2_tumu(mask,merge,op1,op2,31); +} + + +vint16m1_t test___riscv_vmulhsu_vx_i16m1_tumu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i16m1_tumu(mask,merge,op1,op2,31); +} + + +vint16m2_t test___riscv_vmulhsu_vx_i16m2_tumu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i16m2_tumu(mask,merge,op1,op2,31); +} + + +vint16m4_t test___riscv_vmulhsu_vx_i16m4_tumu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i16m4_tumu(mask,merge,op1,op2,31); +} + + +vint16m8_t test___riscv_vmulhsu_vx_i16m8_tumu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i16m8_tumu(mask,merge,op1,op2,31); +} + + +vint32mf2_t test___riscv_vmulhsu_vx_i32mf2_tumu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i32mf2_tumu(mask,merge,op1,op2,31); +} + + +vint32m1_t test___riscv_vmulhsu_vx_i32m1_tumu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i32m1_tumu(mask,merge,op1,op2,31); +} + + +vint32m2_t test___riscv_vmulhsu_vx_i32m2_tumu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i32m2_tumu(mask,merge,op1,op2,31); +} + + +vint32m4_t test___riscv_vmulhsu_vx_i32m4_tumu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i32m4_tumu(mask,merge,op1,op2,31); +} + + +vint32m8_t test___riscv_vmulhsu_vx_i32m8_tumu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i32m8_tumu(mask,merge,op1,op2,31); +} + + +vint64m1_t test___riscv_vmulhsu_vx_i64m1_tumu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i64m1_tumu(mask,merge,op1,op2,31); +} + + +vint64m2_t test___riscv_vmulhsu_vx_i64m2_tumu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i64m2_tumu(mask,merge,op1,op2,31); +} + + +vint64m4_t test___riscv_vmulhsu_vx_i64m4_tumu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i64m4_tumu(mask,merge,op1,op2,31); +} + + +vint64m8_t test___riscv_vmulhsu_vx_i64m8_tumu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i64m8_tumu(mask,merge,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmulhsu_vx_tumu_rv64-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmulhsu_vx_tumu_rv64-3.c new file mode 100644 index 00000000000..5665ab4de82 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmulhsu_vx_tumu_rv64-3.c @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vmulhsu_vx_i8mf8_tumu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i8mf8_tumu(mask,merge,op1,op2,32); +} + + +vint8mf4_t test___riscv_vmulhsu_vx_i8mf4_tumu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i8mf4_tumu(mask,merge,op1,op2,32); +} + + +vint8mf2_t test___riscv_vmulhsu_vx_i8mf2_tumu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i8mf2_tumu(mask,merge,op1,op2,32); +} + + +vint8m1_t test___riscv_vmulhsu_vx_i8m1_tumu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i8m1_tumu(mask,merge,op1,op2,32); +} + + +vint8m2_t test___riscv_vmulhsu_vx_i8m2_tumu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i8m2_tumu(mask,merge,op1,op2,32); +} + + +vint8m4_t test___riscv_vmulhsu_vx_i8m4_tumu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i8m4_tumu(mask,merge,op1,op2,32); +} + + +vint8m8_t test___riscv_vmulhsu_vx_i8m8_tumu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i8m8_tumu(mask,merge,op1,op2,32); +} + + +vint16mf4_t test___riscv_vmulhsu_vx_i16mf4_tumu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i16mf4_tumu(mask,merge,op1,op2,32); +} + + +vint16mf2_t test___riscv_vmulhsu_vx_i16mf2_tumu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i16mf2_tumu(mask,merge,op1,op2,32); +} + + +vint16m1_t test___riscv_vmulhsu_vx_i16m1_tumu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i16m1_tumu(mask,merge,op1,op2,32); +} + + +vint16m2_t test___riscv_vmulhsu_vx_i16m2_tumu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i16m2_tumu(mask,merge,op1,op2,32); +} + + +vint16m4_t test___riscv_vmulhsu_vx_i16m4_tumu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i16m4_tumu(mask,merge,op1,op2,32); +} + + +vint16m8_t test___riscv_vmulhsu_vx_i16m8_tumu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i16m8_tumu(mask,merge,op1,op2,32); +} + + +vint32mf2_t test___riscv_vmulhsu_vx_i32mf2_tumu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i32mf2_tumu(mask,merge,op1,op2,32); +} + + +vint32m1_t test___riscv_vmulhsu_vx_i32m1_tumu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i32m1_tumu(mask,merge,op1,op2,32); +} + + +vint32m2_t test___riscv_vmulhsu_vx_i32m2_tumu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i32m2_tumu(mask,merge,op1,op2,32); +} + + +vint32m4_t test___riscv_vmulhsu_vx_i32m4_tumu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i32m4_tumu(mask,merge,op1,op2,32); +} + + +vint32m8_t test___riscv_vmulhsu_vx_i32m8_tumu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i32m8_tumu(mask,merge,op1,op2,32); +} + + +vint64m1_t test___riscv_vmulhsu_vx_i64m1_tumu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i64m1_tumu(mask,merge,op1,op2,32); +} + + +vint64m2_t test___riscv_vmulhsu_vx_i64m2_tumu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i64m2_tumu(mask,merge,op1,op2,32); +} + + +vint64m4_t test___riscv_vmulhsu_vx_i64m4_tumu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i64m4_tumu(mask,merge,op1,op2,32); +} + + +vint64m8_t test___riscv_vmulhsu_vx_i64m8_tumu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_vx_i64m8_tumu(mask,merge,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */