RISC-V: Add vsext.vf2 C API tests

Message ID 20230206051704.224015-1-juzhe.zhong@rivai.ai
State Committed
Commit 7d2c4a6f07ef2b450c5df8a5a0fae46078d3d21c
Headers
Series RISC-V: Add vsext.vf2 C API tests |

Commit Message

钟居哲 Feb. 6, 2023, 5:17 a.m. UTC
  From: Ju-Zhe Zhong <juzhe.zhong@rivai.ai>

gcc/testsuite/ChangeLog:

        * gcc.target/riscv/rvv/base/vsext_vf2-1.c: New test.
        * gcc.target/riscv/rvv/base/vsext_vf2-2.c: New test.
        * gcc.target/riscv/rvv/base/vsext_vf2-3.c: New test.
        * gcc.target/riscv/rvv/base/vsext_vf2_m-1.c: New test.
        * gcc.target/riscv/rvv/base/vsext_vf2_m-2.c: New test.
        * gcc.target/riscv/rvv/base/vsext_vf2_m-3.c: New test.
        * gcc.target/riscv/rvv/base/vsext_vf2_mu-1.c: New test.
        * gcc.target/riscv/rvv/base/vsext_vf2_mu-2.c: New test.
        * gcc.target/riscv/rvv/base/vsext_vf2_mu-3.c: New test.
        * gcc.target/riscv/rvv/base/vsext_vf2_tu-1.c: New test.
        * gcc.target/riscv/rvv/base/vsext_vf2_tu-2.c: New test.
        * gcc.target/riscv/rvv/base/vsext_vf2_tu-3.c: New test.
        * gcc.target/riscv/rvv/base/vsext_vf2_tum-1.c: New test.
        * gcc.target/riscv/rvv/base/vsext_vf2_tum-2.c: New test.
        * gcc.target/riscv/rvv/base/vsext_vf2_tum-3.c: New test.
        * gcc.target/riscv/rvv/base/vsext_vf2_tumu-1.c: New test.
        * gcc.target/riscv/rvv/base/vsext_vf2_tumu-2.c: New test.
        * gcc.target/riscv/rvv/base/vsext_vf2_tumu-3.c: New test.

---
 .../gcc.target/riscv/rvv/base/vsext_vf2-1.c   | 111 ++++++++++++++++++
 .../gcc.target/riscv/rvv/base/vsext_vf2-2.c   | 111 ++++++++++++++++++
 .../gcc.target/riscv/rvv/base/vsext_vf2-3.c   | 111 ++++++++++++++++++
 .../gcc.target/riscv/rvv/base/vsext_vf2_m-1.c | 111 ++++++++++++++++++
 .../gcc.target/riscv/rvv/base/vsext_vf2_m-2.c | 111 ++++++++++++++++++
 .../gcc.target/riscv/rvv/base/vsext_vf2_m-3.c | 111 ++++++++++++++++++
 .../riscv/rvv/base/vsext_vf2_mu-1.c           | 111 ++++++++++++++++++
 .../riscv/rvv/base/vsext_vf2_mu-2.c           | 111 ++++++++++++++++++
 .../riscv/rvv/base/vsext_vf2_mu-3.c           | 111 ++++++++++++++++++
 .../riscv/rvv/base/vsext_vf2_tu-1.c           | 111 ++++++++++++++++++
 .../riscv/rvv/base/vsext_vf2_tu-2.c           | 111 ++++++++++++++++++
 .../riscv/rvv/base/vsext_vf2_tu-3.c           | 111 ++++++++++++++++++
 .../riscv/rvv/base/vsext_vf2_tum-1.c          | 111 ++++++++++++++++++
 .../riscv/rvv/base/vsext_vf2_tum-2.c          | 111 ++++++++++++++++++
 .../riscv/rvv/base/vsext_vf2_tum-3.c          | 111 ++++++++++++++++++
 .../riscv/rvv/base/vsext_vf2_tumu-1.c         | 111 ++++++++++++++++++
 .../riscv/rvv/base/vsext_vf2_tumu-2.c         | 111 ++++++++++++++++++
 .../riscv/rvv/base/vsext_vf2_tumu-3.c         | 111 ++++++++++++++++++
 18 files changed, 1998 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf2-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf2-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf2-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf2_m-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf2_m-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf2_m-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf2_mu-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf2_mu-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf2_mu-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf2_tu-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf2_tu-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf2_tu-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf2_tum-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf2_tum-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf2_tum-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf2_tumu-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf2_tumu-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf2_tumu-3.c
  

Patch

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf2-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf2-1.c
new file mode 100644
index 00000000000..eb8fdb8adff
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf2-1.c
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vsext_vf2_i16mf4(vint8mf8_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i16mf4(op1,vl);
+}
+
+
+vint16mf2_t test___riscv_vsext_vf2_i16mf2(vint8mf4_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i16mf2(op1,vl);
+}
+
+
+vint16m1_t test___riscv_vsext_vf2_i16m1(vint8mf2_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i16m1(op1,vl);
+}
+
+
+vint16m2_t test___riscv_vsext_vf2_i16m2(vint8m1_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i16m2(op1,vl);
+}
+
+
+vint16m4_t test___riscv_vsext_vf2_i16m4(vint8m2_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i16m4(op1,vl);
+}
+
+
+vint16m8_t test___riscv_vsext_vf2_i16m8(vint8m4_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i16m8(op1,vl);
+}
+
+
+vint32mf2_t test___riscv_vsext_vf2_i32mf2(vint16mf4_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i32mf2(op1,vl);
+}
+
+
+vint32m1_t test___riscv_vsext_vf2_i32m1(vint16mf2_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i32m1(op1,vl);
+}
+
+
+vint32m2_t test___riscv_vsext_vf2_i32m2(vint16m1_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i32m2(op1,vl);
+}
+
+
+vint32m4_t test___riscv_vsext_vf2_i32m4(vint16m2_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i32m4(op1,vl);
+}
+
+
+vint32m8_t test___riscv_vsext_vf2_i32m8(vint16m4_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i32m8(op1,vl);
+}
+
+
+vint64m1_t test___riscv_vsext_vf2_i64m1(vint32mf2_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i64m1(op1,vl);
+}
+
+
+vint64m2_t test___riscv_vsext_vf2_i64m2(vint32m1_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i64m2(op1,vl);
+}
+
+
+vint64m4_t test___riscv_vsext_vf2_i64m4(vint32m2_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i64m4(op1,vl);
+}
+
+
+vint64m8_t test___riscv_vsext_vf2_i64m8(vint32m4_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i64m8(op1,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf2-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf2-2.c
new file mode 100644
index 00000000000..dce1aa2adf0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf2-2.c
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vsext_vf2_i16mf4(vint8mf8_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i16mf4(op1,31);
+}
+
+
+vint16mf2_t test___riscv_vsext_vf2_i16mf2(vint8mf4_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i16mf2(op1,31);
+}
+
+
+vint16m1_t test___riscv_vsext_vf2_i16m1(vint8mf2_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i16m1(op1,31);
+}
+
+
+vint16m2_t test___riscv_vsext_vf2_i16m2(vint8m1_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i16m2(op1,31);
+}
+
+
+vint16m4_t test___riscv_vsext_vf2_i16m4(vint8m2_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i16m4(op1,31);
+}
+
+
+vint16m8_t test___riscv_vsext_vf2_i16m8(vint8m4_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i16m8(op1,31);
+}
+
+
+vint32mf2_t test___riscv_vsext_vf2_i32mf2(vint16mf4_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i32mf2(op1,31);
+}
+
+
+vint32m1_t test___riscv_vsext_vf2_i32m1(vint16mf2_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i32m1(op1,31);
+}
+
+
+vint32m2_t test___riscv_vsext_vf2_i32m2(vint16m1_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i32m2(op1,31);
+}
+
+
+vint32m4_t test___riscv_vsext_vf2_i32m4(vint16m2_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i32m4(op1,31);
+}
+
+
+vint32m8_t test___riscv_vsext_vf2_i32m8(vint16m4_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i32m8(op1,31);
+}
+
+
+vint64m1_t test___riscv_vsext_vf2_i64m1(vint32mf2_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i64m1(op1,31);
+}
+
+
+vint64m2_t test___riscv_vsext_vf2_i64m2(vint32m1_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i64m2(op1,31);
+}
+
+
+vint64m4_t test___riscv_vsext_vf2_i64m4(vint32m2_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i64m4(op1,31);
+}
+
+
+vint64m8_t test___riscv_vsext_vf2_i64m8(vint32m4_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i64m8(op1,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf2-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf2-3.c
new file mode 100644
index 00000000000..98f43bcea35
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf2-3.c
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vsext_vf2_i16mf4(vint8mf8_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i16mf4(op1,32);
+}
+
+
+vint16mf2_t test___riscv_vsext_vf2_i16mf2(vint8mf4_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i16mf2(op1,32);
+}
+
+
+vint16m1_t test___riscv_vsext_vf2_i16m1(vint8mf2_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i16m1(op1,32);
+}
+
+
+vint16m2_t test___riscv_vsext_vf2_i16m2(vint8m1_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i16m2(op1,32);
+}
+
+
+vint16m4_t test___riscv_vsext_vf2_i16m4(vint8m2_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i16m4(op1,32);
+}
+
+
+vint16m8_t test___riscv_vsext_vf2_i16m8(vint8m4_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i16m8(op1,32);
+}
+
+
+vint32mf2_t test___riscv_vsext_vf2_i32mf2(vint16mf4_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i32mf2(op1,32);
+}
+
+
+vint32m1_t test___riscv_vsext_vf2_i32m1(vint16mf2_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i32m1(op1,32);
+}
+
+
+vint32m2_t test___riscv_vsext_vf2_i32m2(vint16m1_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i32m2(op1,32);
+}
+
+
+vint32m4_t test___riscv_vsext_vf2_i32m4(vint16m2_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i32m4(op1,32);
+}
+
+
+vint32m8_t test___riscv_vsext_vf2_i32m8(vint16m4_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i32m8(op1,32);
+}
+
+
+vint64m1_t test___riscv_vsext_vf2_i64m1(vint32mf2_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i64m1(op1,32);
+}
+
+
+vint64m2_t test___riscv_vsext_vf2_i64m2(vint32m1_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i64m2(op1,32);
+}
+
+
+vint64m4_t test___riscv_vsext_vf2_i64m4(vint32m2_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i64m4(op1,32);
+}
+
+
+vint64m8_t test___riscv_vsext_vf2_i64m8(vint32m4_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i64m8(op1,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf2_m-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf2_m-1.c
new file mode 100644
index 00000000000..8f7ad903e1b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf2_m-1.c
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vsext_vf2_i16mf4_m(vbool64_t mask,vint8mf8_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i16mf4_m(mask,op1,vl);
+}
+
+
+vint16mf2_t test___riscv_vsext_vf2_i16mf2_m(vbool32_t mask,vint8mf4_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i16mf2_m(mask,op1,vl);
+}
+
+
+vint16m1_t test___riscv_vsext_vf2_i16m1_m(vbool16_t mask,vint8mf2_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i16m1_m(mask,op1,vl);
+}
+
+
+vint16m2_t test___riscv_vsext_vf2_i16m2_m(vbool8_t mask,vint8m1_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i16m2_m(mask,op1,vl);
+}
+
+
+vint16m4_t test___riscv_vsext_vf2_i16m4_m(vbool4_t mask,vint8m2_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i16m4_m(mask,op1,vl);
+}
+
+
+vint16m8_t test___riscv_vsext_vf2_i16m8_m(vbool2_t mask,vint8m4_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i16m8_m(mask,op1,vl);
+}
+
+
+vint32mf2_t test___riscv_vsext_vf2_i32mf2_m(vbool64_t mask,vint16mf4_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i32mf2_m(mask,op1,vl);
+}
+
+
+vint32m1_t test___riscv_vsext_vf2_i32m1_m(vbool32_t mask,vint16mf2_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i32m1_m(mask,op1,vl);
+}
+
+
+vint32m2_t test___riscv_vsext_vf2_i32m2_m(vbool16_t mask,vint16m1_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i32m2_m(mask,op1,vl);
+}
+
+
+vint32m4_t test___riscv_vsext_vf2_i32m4_m(vbool8_t mask,vint16m2_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i32m4_m(mask,op1,vl);
+}
+
+
+vint32m8_t test___riscv_vsext_vf2_i32m8_m(vbool4_t mask,vint16m4_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i32m8_m(mask,op1,vl);
+}
+
+
+vint64m1_t test___riscv_vsext_vf2_i64m1_m(vbool64_t mask,vint32mf2_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i64m1_m(mask,op1,vl);
+}
+
+
+vint64m2_t test___riscv_vsext_vf2_i64m2_m(vbool32_t mask,vint32m1_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i64m2_m(mask,op1,vl);
+}
+
+
+vint64m4_t test___riscv_vsext_vf2_i64m4_m(vbool16_t mask,vint32m2_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i64m4_m(mask,op1,vl);
+}
+
+
+vint64m8_t test___riscv_vsext_vf2_i64m8_m(vbool8_t mask,vint32m4_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i64m8_m(mask,op1,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf2_m-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf2_m-2.c
new file mode 100644
index 00000000000..8d0573f03a6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf2_m-2.c
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vsext_vf2_i16mf4_m(vbool64_t mask,vint8mf8_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i16mf4_m(mask,op1,31);
+}
+
+
+vint16mf2_t test___riscv_vsext_vf2_i16mf2_m(vbool32_t mask,vint8mf4_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i16mf2_m(mask,op1,31);
+}
+
+
+vint16m1_t test___riscv_vsext_vf2_i16m1_m(vbool16_t mask,vint8mf2_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i16m1_m(mask,op1,31);
+}
+
+
+vint16m2_t test___riscv_vsext_vf2_i16m2_m(vbool8_t mask,vint8m1_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i16m2_m(mask,op1,31);
+}
+
+
+vint16m4_t test___riscv_vsext_vf2_i16m4_m(vbool4_t mask,vint8m2_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i16m4_m(mask,op1,31);
+}
+
+
+vint16m8_t test___riscv_vsext_vf2_i16m8_m(vbool2_t mask,vint8m4_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i16m8_m(mask,op1,31);
+}
+
+
+vint32mf2_t test___riscv_vsext_vf2_i32mf2_m(vbool64_t mask,vint16mf4_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i32mf2_m(mask,op1,31);
+}
+
+
+vint32m1_t test___riscv_vsext_vf2_i32m1_m(vbool32_t mask,vint16mf2_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i32m1_m(mask,op1,31);
+}
+
+
+vint32m2_t test___riscv_vsext_vf2_i32m2_m(vbool16_t mask,vint16m1_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i32m2_m(mask,op1,31);
+}
+
+
+vint32m4_t test___riscv_vsext_vf2_i32m4_m(vbool8_t mask,vint16m2_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i32m4_m(mask,op1,31);
+}
+
+
+vint32m8_t test___riscv_vsext_vf2_i32m8_m(vbool4_t mask,vint16m4_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i32m8_m(mask,op1,31);
+}
+
+
+vint64m1_t test___riscv_vsext_vf2_i64m1_m(vbool64_t mask,vint32mf2_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i64m1_m(mask,op1,31);
+}
+
+
+vint64m2_t test___riscv_vsext_vf2_i64m2_m(vbool32_t mask,vint32m1_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i64m2_m(mask,op1,31);
+}
+
+
+vint64m4_t test___riscv_vsext_vf2_i64m4_m(vbool16_t mask,vint32m2_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i64m4_m(mask,op1,31);
+}
+
+
+vint64m8_t test___riscv_vsext_vf2_i64m8_m(vbool8_t mask,vint32m4_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i64m8_m(mask,op1,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf2_m-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf2_m-3.c
new file mode 100644
index 00000000000..b7151d3204b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf2_m-3.c
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vsext_vf2_i16mf4_m(vbool64_t mask,vint8mf8_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i16mf4_m(mask,op1,32);
+}
+
+
+vint16mf2_t test___riscv_vsext_vf2_i16mf2_m(vbool32_t mask,vint8mf4_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i16mf2_m(mask,op1,32);
+}
+
+
+vint16m1_t test___riscv_vsext_vf2_i16m1_m(vbool16_t mask,vint8mf2_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i16m1_m(mask,op1,32);
+}
+
+
+vint16m2_t test___riscv_vsext_vf2_i16m2_m(vbool8_t mask,vint8m1_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i16m2_m(mask,op1,32);
+}
+
+
+vint16m4_t test___riscv_vsext_vf2_i16m4_m(vbool4_t mask,vint8m2_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i16m4_m(mask,op1,32);
+}
+
+
+vint16m8_t test___riscv_vsext_vf2_i16m8_m(vbool2_t mask,vint8m4_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i16m8_m(mask,op1,32);
+}
+
+
+vint32mf2_t test___riscv_vsext_vf2_i32mf2_m(vbool64_t mask,vint16mf4_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i32mf2_m(mask,op1,32);
+}
+
+
+vint32m1_t test___riscv_vsext_vf2_i32m1_m(vbool32_t mask,vint16mf2_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i32m1_m(mask,op1,32);
+}
+
+
+vint32m2_t test___riscv_vsext_vf2_i32m2_m(vbool16_t mask,vint16m1_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i32m2_m(mask,op1,32);
+}
+
+
+vint32m4_t test___riscv_vsext_vf2_i32m4_m(vbool8_t mask,vint16m2_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i32m4_m(mask,op1,32);
+}
+
+
+vint32m8_t test___riscv_vsext_vf2_i32m8_m(vbool4_t mask,vint16m4_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i32m8_m(mask,op1,32);
+}
+
+
+vint64m1_t test___riscv_vsext_vf2_i64m1_m(vbool64_t mask,vint32mf2_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i64m1_m(mask,op1,32);
+}
+
+
+vint64m2_t test___riscv_vsext_vf2_i64m2_m(vbool32_t mask,vint32m1_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i64m2_m(mask,op1,32);
+}
+
+
+vint64m4_t test___riscv_vsext_vf2_i64m4_m(vbool16_t mask,vint32m2_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i64m4_m(mask,op1,32);
+}
+
+
+vint64m8_t test___riscv_vsext_vf2_i64m8_m(vbool8_t mask,vint32m4_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i64m8_m(mask,op1,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf2_mu-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf2_mu-1.c
new file mode 100644
index 00000000000..3289fe5bcd6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf2_mu-1.c
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vsext_vf2_i16mf4_mu(vbool64_t mask,vint16mf4_t merge,vint8mf8_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i16mf4_mu(mask,merge,op1,vl);
+}
+
+
+vint16mf2_t test___riscv_vsext_vf2_i16mf2_mu(vbool32_t mask,vint16mf2_t merge,vint8mf4_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i16mf2_mu(mask,merge,op1,vl);
+}
+
+
+vint16m1_t test___riscv_vsext_vf2_i16m1_mu(vbool16_t mask,vint16m1_t merge,vint8mf2_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i16m1_mu(mask,merge,op1,vl);
+}
+
+
+vint16m2_t test___riscv_vsext_vf2_i16m2_mu(vbool8_t mask,vint16m2_t merge,vint8m1_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i16m2_mu(mask,merge,op1,vl);
+}
+
+
+vint16m4_t test___riscv_vsext_vf2_i16m4_mu(vbool4_t mask,vint16m4_t merge,vint8m2_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i16m4_mu(mask,merge,op1,vl);
+}
+
+
+vint16m8_t test___riscv_vsext_vf2_i16m8_mu(vbool2_t mask,vint16m8_t merge,vint8m4_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i16m8_mu(mask,merge,op1,vl);
+}
+
+
+vint32mf2_t test___riscv_vsext_vf2_i32mf2_mu(vbool64_t mask,vint32mf2_t merge,vint16mf4_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i32mf2_mu(mask,merge,op1,vl);
+}
+
+
+vint32m1_t test___riscv_vsext_vf2_i32m1_mu(vbool32_t mask,vint32m1_t merge,vint16mf2_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i32m1_mu(mask,merge,op1,vl);
+}
+
+
+vint32m2_t test___riscv_vsext_vf2_i32m2_mu(vbool16_t mask,vint32m2_t merge,vint16m1_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i32m2_mu(mask,merge,op1,vl);
+}
+
+
+vint32m4_t test___riscv_vsext_vf2_i32m4_mu(vbool8_t mask,vint32m4_t merge,vint16m2_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i32m4_mu(mask,merge,op1,vl);
+}
+
+
+vint32m8_t test___riscv_vsext_vf2_i32m8_mu(vbool4_t mask,vint32m8_t merge,vint16m4_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i32m8_mu(mask,merge,op1,vl);
+}
+
+
+vint64m1_t test___riscv_vsext_vf2_i64m1_mu(vbool64_t mask,vint64m1_t merge,vint32mf2_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i64m1_mu(mask,merge,op1,vl);
+}
+
+
+vint64m2_t test___riscv_vsext_vf2_i64m2_mu(vbool32_t mask,vint64m2_t merge,vint32m1_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i64m2_mu(mask,merge,op1,vl);
+}
+
+
+vint64m4_t test___riscv_vsext_vf2_i64m4_mu(vbool16_t mask,vint64m4_t merge,vint32m2_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i64m4_mu(mask,merge,op1,vl);
+}
+
+
+vint64m8_t test___riscv_vsext_vf2_i64m8_mu(vbool8_t mask,vint64m8_t merge,vint32m4_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i64m8_mu(mask,merge,op1,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*mu\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*mu\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*mu\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*mu\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*mu\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf2_mu-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf2_mu-2.c
new file mode 100644
index 00000000000..26c26e5d2cf
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf2_mu-2.c
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vsext_vf2_i16mf4_mu(vbool64_t mask,vint16mf4_t merge,vint8mf8_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i16mf4_mu(mask,merge,op1,31);
+}
+
+
+vint16mf2_t test___riscv_vsext_vf2_i16mf2_mu(vbool32_t mask,vint16mf2_t merge,vint8mf4_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i16mf2_mu(mask,merge,op1,31);
+}
+
+
+vint16m1_t test___riscv_vsext_vf2_i16m1_mu(vbool16_t mask,vint16m1_t merge,vint8mf2_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i16m1_mu(mask,merge,op1,31);
+}
+
+
+vint16m2_t test___riscv_vsext_vf2_i16m2_mu(vbool8_t mask,vint16m2_t merge,vint8m1_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i16m2_mu(mask,merge,op1,31);
+}
+
+
+vint16m4_t test___riscv_vsext_vf2_i16m4_mu(vbool4_t mask,vint16m4_t merge,vint8m2_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i16m4_mu(mask,merge,op1,31);
+}
+
+
+vint16m8_t test___riscv_vsext_vf2_i16m8_mu(vbool2_t mask,vint16m8_t merge,vint8m4_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i16m8_mu(mask,merge,op1,31);
+}
+
+
+vint32mf2_t test___riscv_vsext_vf2_i32mf2_mu(vbool64_t mask,vint32mf2_t merge,vint16mf4_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i32mf2_mu(mask,merge,op1,31);
+}
+
+
+vint32m1_t test___riscv_vsext_vf2_i32m1_mu(vbool32_t mask,vint32m1_t merge,vint16mf2_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i32m1_mu(mask,merge,op1,31);
+}
+
+
+vint32m2_t test___riscv_vsext_vf2_i32m2_mu(vbool16_t mask,vint32m2_t merge,vint16m1_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i32m2_mu(mask,merge,op1,31);
+}
+
+
+vint32m4_t test___riscv_vsext_vf2_i32m4_mu(vbool8_t mask,vint32m4_t merge,vint16m2_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i32m4_mu(mask,merge,op1,31);
+}
+
+
+vint32m8_t test___riscv_vsext_vf2_i32m8_mu(vbool4_t mask,vint32m8_t merge,vint16m4_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i32m8_mu(mask,merge,op1,31);
+}
+
+
+vint64m1_t test___riscv_vsext_vf2_i64m1_mu(vbool64_t mask,vint64m1_t merge,vint32mf2_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i64m1_mu(mask,merge,op1,31);
+}
+
+
+vint64m2_t test___riscv_vsext_vf2_i64m2_mu(vbool32_t mask,vint64m2_t merge,vint32m1_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i64m2_mu(mask,merge,op1,31);
+}
+
+
+vint64m4_t test___riscv_vsext_vf2_i64m4_mu(vbool16_t mask,vint64m4_t merge,vint32m2_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i64m4_mu(mask,merge,op1,31);
+}
+
+
+vint64m8_t test___riscv_vsext_vf2_i64m8_mu(vbool8_t mask,vint64m8_t merge,vint32m4_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i64m8_mu(mask,merge,op1,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*mu\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*mu\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*mu\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*mu\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*mu\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*mu\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*mu\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*mu\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*mu\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*mu\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*mu\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*mu\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf2_mu-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf2_mu-3.c
new file mode 100644
index 00000000000..d60387eac79
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf2_mu-3.c
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vsext_vf2_i16mf4_mu(vbool64_t mask,vint16mf4_t merge,vint8mf8_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i16mf4_mu(mask,merge,op1,32);
+}
+
+
+vint16mf2_t test___riscv_vsext_vf2_i16mf2_mu(vbool32_t mask,vint16mf2_t merge,vint8mf4_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i16mf2_mu(mask,merge,op1,32);
+}
+
+
+vint16m1_t test___riscv_vsext_vf2_i16m1_mu(vbool16_t mask,vint16m1_t merge,vint8mf2_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i16m1_mu(mask,merge,op1,32);
+}
+
+
+vint16m2_t test___riscv_vsext_vf2_i16m2_mu(vbool8_t mask,vint16m2_t merge,vint8m1_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i16m2_mu(mask,merge,op1,32);
+}
+
+
+vint16m4_t test___riscv_vsext_vf2_i16m4_mu(vbool4_t mask,vint16m4_t merge,vint8m2_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i16m4_mu(mask,merge,op1,32);
+}
+
+
+vint16m8_t test___riscv_vsext_vf2_i16m8_mu(vbool2_t mask,vint16m8_t merge,vint8m4_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i16m8_mu(mask,merge,op1,32);
+}
+
+
+vint32mf2_t test___riscv_vsext_vf2_i32mf2_mu(vbool64_t mask,vint32mf2_t merge,vint16mf4_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i32mf2_mu(mask,merge,op1,32);
+}
+
+
+vint32m1_t test___riscv_vsext_vf2_i32m1_mu(vbool32_t mask,vint32m1_t merge,vint16mf2_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i32m1_mu(mask,merge,op1,32);
+}
+
+
+vint32m2_t test___riscv_vsext_vf2_i32m2_mu(vbool16_t mask,vint32m2_t merge,vint16m1_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i32m2_mu(mask,merge,op1,32);
+}
+
+
+vint32m4_t test___riscv_vsext_vf2_i32m4_mu(vbool8_t mask,vint32m4_t merge,vint16m2_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i32m4_mu(mask,merge,op1,32);
+}
+
+
+vint32m8_t test___riscv_vsext_vf2_i32m8_mu(vbool4_t mask,vint32m8_t merge,vint16m4_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i32m8_mu(mask,merge,op1,32);
+}
+
+
+vint64m1_t test___riscv_vsext_vf2_i64m1_mu(vbool64_t mask,vint64m1_t merge,vint32mf2_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i64m1_mu(mask,merge,op1,32);
+}
+
+
+vint64m2_t test___riscv_vsext_vf2_i64m2_mu(vbool32_t mask,vint64m2_t merge,vint32m1_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i64m2_mu(mask,merge,op1,32);
+}
+
+
+vint64m4_t test___riscv_vsext_vf2_i64m4_mu(vbool16_t mask,vint64m4_t merge,vint32m2_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i64m4_mu(mask,merge,op1,32);
+}
+
+
+vint64m8_t test___riscv_vsext_vf2_i64m8_mu(vbool8_t mask,vint64m8_t merge,vint32m4_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i64m8_mu(mask,merge,op1,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*mu\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*mu\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*mu\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*mu\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*mu\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf2_tu-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf2_tu-1.c
new file mode 100644
index 00000000000..4394514f7c8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf2_tu-1.c
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vsext_vf2_i16mf4_tu(vint16mf4_t merge,vint8mf8_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i16mf4_tu(merge,op1,vl);
+}
+
+
+vint16mf2_t test___riscv_vsext_vf2_i16mf2_tu(vint16mf2_t merge,vint8mf4_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i16mf2_tu(merge,op1,vl);
+}
+
+
+vint16m1_t test___riscv_vsext_vf2_i16m1_tu(vint16m1_t merge,vint8mf2_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i16m1_tu(merge,op1,vl);
+}
+
+
+vint16m2_t test___riscv_vsext_vf2_i16m2_tu(vint16m2_t merge,vint8m1_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i16m2_tu(merge,op1,vl);
+}
+
+
+vint16m4_t test___riscv_vsext_vf2_i16m4_tu(vint16m4_t merge,vint8m2_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i16m4_tu(merge,op1,vl);
+}
+
+
+vint16m8_t test___riscv_vsext_vf2_i16m8_tu(vint16m8_t merge,vint8m4_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i16m8_tu(merge,op1,vl);
+}
+
+
+vint32mf2_t test___riscv_vsext_vf2_i32mf2_tu(vint32mf2_t merge,vint16mf4_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i32mf2_tu(merge,op1,vl);
+}
+
+
+vint32m1_t test___riscv_vsext_vf2_i32m1_tu(vint32m1_t merge,vint16mf2_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i32m1_tu(merge,op1,vl);
+}
+
+
+vint32m2_t test___riscv_vsext_vf2_i32m2_tu(vint32m2_t merge,vint16m1_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i32m2_tu(merge,op1,vl);
+}
+
+
+vint32m4_t test___riscv_vsext_vf2_i32m4_tu(vint32m4_t merge,vint16m2_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i32m4_tu(merge,op1,vl);
+}
+
+
+vint32m8_t test___riscv_vsext_vf2_i32m8_tu(vint32m8_t merge,vint16m4_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i32m8_tu(merge,op1,vl);
+}
+
+
+vint64m1_t test___riscv_vsext_vf2_i64m1_tu(vint64m1_t merge,vint32mf2_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i64m1_tu(merge,op1,vl);
+}
+
+
+vint64m2_t test___riscv_vsext_vf2_i64m2_tu(vint64m2_t merge,vint32m1_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i64m2_tu(merge,op1,vl);
+}
+
+
+vint64m4_t test___riscv_vsext_vf2_i64m4_tu(vint64m4_t merge,vint32m2_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i64m4_tu(merge,op1,vl);
+}
+
+
+vint64m8_t test___riscv_vsext_vf2_i64m8_tu(vint64m8_t merge,vint32m4_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i64m8_tu(merge,op1,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf2_tu-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf2_tu-2.c
new file mode 100644
index 00000000000..0d010e02331
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf2_tu-2.c
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vsext_vf2_i16mf4_tu(vint16mf4_t merge,vint8mf8_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i16mf4_tu(merge,op1,31);
+}
+
+
+vint16mf2_t test___riscv_vsext_vf2_i16mf2_tu(vint16mf2_t merge,vint8mf4_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i16mf2_tu(merge,op1,31);
+}
+
+
+vint16m1_t test___riscv_vsext_vf2_i16m1_tu(vint16m1_t merge,vint8mf2_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i16m1_tu(merge,op1,31);
+}
+
+
+vint16m2_t test___riscv_vsext_vf2_i16m2_tu(vint16m2_t merge,vint8m1_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i16m2_tu(merge,op1,31);
+}
+
+
+vint16m4_t test___riscv_vsext_vf2_i16m4_tu(vint16m4_t merge,vint8m2_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i16m4_tu(merge,op1,31);
+}
+
+
+vint16m8_t test___riscv_vsext_vf2_i16m8_tu(vint16m8_t merge,vint8m4_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i16m8_tu(merge,op1,31);
+}
+
+
+vint32mf2_t test___riscv_vsext_vf2_i32mf2_tu(vint32mf2_t merge,vint16mf4_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i32mf2_tu(merge,op1,31);
+}
+
+
+vint32m1_t test___riscv_vsext_vf2_i32m1_tu(vint32m1_t merge,vint16mf2_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i32m1_tu(merge,op1,31);
+}
+
+
+vint32m2_t test___riscv_vsext_vf2_i32m2_tu(vint32m2_t merge,vint16m1_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i32m2_tu(merge,op1,31);
+}
+
+
+vint32m4_t test___riscv_vsext_vf2_i32m4_tu(vint32m4_t merge,vint16m2_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i32m4_tu(merge,op1,31);
+}
+
+
+vint32m8_t test___riscv_vsext_vf2_i32m8_tu(vint32m8_t merge,vint16m4_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i32m8_tu(merge,op1,31);
+}
+
+
+vint64m1_t test___riscv_vsext_vf2_i64m1_tu(vint64m1_t merge,vint32mf2_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i64m1_tu(merge,op1,31);
+}
+
+
+vint64m2_t test___riscv_vsext_vf2_i64m2_tu(vint64m2_t merge,vint32m1_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i64m2_tu(merge,op1,31);
+}
+
+
+vint64m4_t test___riscv_vsext_vf2_i64m4_tu(vint64m4_t merge,vint32m2_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i64m4_tu(merge,op1,31);
+}
+
+
+vint64m8_t test___riscv_vsext_vf2_i64m8_tu(vint64m8_t merge,vint32m4_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i64m8_tu(merge,op1,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf2_tu-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf2_tu-3.c
new file mode 100644
index 00000000000..04443df8a33
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf2_tu-3.c
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vsext_vf2_i16mf4_tu(vint16mf4_t merge,vint8mf8_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i16mf4_tu(merge,op1,32);
+}
+
+
+vint16mf2_t test___riscv_vsext_vf2_i16mf2_tu(vint16mf2_t merge,vint8mf4_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i16mf2_tu(merge,op1,32);
+}
+
+
+vint16m1_t test___riscv_vsext_vf2_i16m1_tu(vint16m1_t merge,vint8mf2_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i16m1_tu(merge,op1,32);
+}
+
+
+vint16m2_t test___riscv_vsext_vf2_i16m2_tu(vint16m2_t merge,vint8m1_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i16m2_tu(merge,op1,32);
+}
+
+
+vint16m4_t test___riscv_vsext_vf2_i16m4_tu(vint16m4_t merge,vint8m2_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i16m4_tu(merge,op1,32);
+}
+
+
+vint16m8_t test___riscv_vsext_vf2_i16m8_tu(vint16m8_t merge,vint8m4_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i16m8_tu(merge,op1,32);
+}
+
+
+vint32mf2_t test___riscv_vsext_vf2_i32mf2_tu(vint32mf2_t merge,vint16mf4_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i32mf2_tu(merge,op1,32);
+}
+
+
+vint32m1_t test___riscv_vsext_vf2_i32m1_tu(vint32m1_t merge,vint16mf2_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i32m1_tu(merge,op1,32);
+}
+
+
+vint32m2_t test___riscv_vsext_vf2_i32m2_tu(vint32m2_t merge,vint16m1_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i32m2_tu(merge,op1,32);
+}
+
+
+vint32m4_t test___riscv_vsext_vf2_i32m4_tu(vint32m4_t merge,vint16m2_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i32m4_tu(merge,op1,32);
+}
+
+
+vint32m8_t test___riscv_vsext_vf2_i32m8_tu(vint32m8_t merge,vint16m4_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i32m8_tu(merge,op1,32);
+}
+
+
+vint64m1_t test___riscv_vsext_vf2_i64m1_tu(vint64m1_t merge,vint32mf2_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i64m1_tu(merge,op1,32);
+}
+
+
+vint64m2_t test___riscv_vsext_vf2_i64m2_tu(vint64m2_t merge,vint32m1_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i64m2_tu(merge,op1,32);
+}
+
+
+vint64m4_t test___riscv_vsext_vf2_i64m4_tu(vint64m4_t merge,vint32m2_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i64m4_tu(merge,op1,32);
+}
+
+
+vint64m8_t test___riscv_vsext_vf2_i64m8_tu(vint64m8_t merge,vint32m4_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i64m8_tu(merge,op1,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf2_tum-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf2_tum-1.c
new file mode 100644
index 00000000000..47422356482
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf2_tum-1.c
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vsext_vf2_i16mf4_tum(vbool64_t mask,vint16mf4_t merge,vint8mf8_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i16mf4_tum(mask,merge,op1,vl);
+}
+
+
+vint16mf2_t test___riscv_vsext_vf2_i16mf2_tum(vbool32_t mask,vint16mf2_t merge,vint8mf4_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i16mf2_tum(mask,merge,op1,vl);
+}
+
+
+vint16m1_t test___riscv_vsext_vf2_i16m1_tum(vbool16_t mask,vint16m1_t merge,vint8mf2_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i16m1_tum(mask,merge,op1,vl);
+}
+
+
+vint16m2_t test___riscv_vsext_vf2_i16m2_tum(vbool8_t mask,vint16m2_t merge,vint8m1_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i16m2_tum(mask,merge,op1,vl);
+}
+
+
+vint16m4_t test___riscv_vsext_vf2_i16m4_tum(vbool4_t mask,vint16m4_t merge,vint8m2_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i16m4_tum(mask,merge,op1,vl);
+}
+
+
+vint16m8_t test___riscv_vsext_vf2_i16m8_tum(vbool2_t mask,vint16m8_t merge,vint8m4_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i16m8_tum(mask,merge,op1,vl);
+}
+
+
+vint32mf2_t test___riscv_vsext_vf2_i32mf2_tum(vbool64_t mask,vint32mf2_t merge,vint16mf4_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i32mf2_tum(mask,merge,op1,vl);
+}
+
+
+vint32m1_t test___riscv_vsext_vf2_i32m1_tum(vbool32_t mask,vint32m1_t merge,vint16mf2_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i32m1_tum(mask,merge,op1,vl);
+}
+
+
+vint32m2_t test___riscv_vsext_vf2_i32m2_tum(vbool16_t mask,vint32m2_t merge,vint16m1_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i32m2_tum(mask,merge,op1,vl);
+}
+
+
+vint32m4_t test___riscv_vsext_vf2_i32m4_tum(vbool8_t mask,vint32m4_t merge,vint16m2_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i32m4_tum(mask,merge,op1,vl);
+}
+
+
+vint32m8_t test___riscv_vsext_vf2_i32m8_tum(vbool4_t mask,vint32m8_t merge,vint16m4_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i32m8_tum(mask,merge,op1,vl);
+}
+
+
+vint64m1_t test___riscv_vsext_vf2_i64m1_tum(vbool64_t mask,vint64m1_t merge,vint32mf2_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i64m1_tum(mask,merge,op1,vl);
+}
+
+
+vint64m2_t test___riscv_vsext_vf2_i64m2_tum(vbool32_t mask,vint64m2_t merge,vint32m1_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i64m2_tum(mask,merge,op1,vl);
+}
+
+
+vint64m4_t test___riscv_vsext_vf2_i64m4_tum(vbool16_t mask,vint64m4_t merge,vint32m2_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i64m4_tum(mask,merge,op1,vl);
+}
+
+
+vint64m8_t test___riscv_vsext_vf2_i64m8_tum(vbool8_t mask,vint64m8_t merge,vint32m4_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i64m8_tum(mask,merge,op1,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf2_tum-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf2_tum-2.c
new file mode 100644
index 00000000000..4a523e27807
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf2_tum-2.c
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vsext_vf2_i16mf4_tum(vbool64_t mask,vint16mf4_t merge,vint8mf8_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i16mf4_tum(mask,merge,op1,31);
+}
+
+
+vint16mf2_t test___riscv_vsext_vf2_i16mf2_tum(vbool32_t mask,vint16mf2_t merge,vint8mf4_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i16mf2_tum(mask,merge,op1,31);
+}
+
+
+vint16m1_t test___riscv_vsext_vf2_i16m1_tum(vbool16_t mask,vint16m1_t merge,vint8mf2_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i16m1_tum(mask,merge,op1,31);
+}
+
+
+vint16m2_t test___riscv_vsext_vf2_i16m2_tum(vbool8_t mask,vint16m2_t merge,vint8m1_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i16m2_tum(mask,merge,op1,31);
+}
+
+
+vint16m4_t test___riscv_vsext_vf2_i16m4_tum(vbool4_t mask,vint16m4_t merge,vint8m2_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i16m4_tum(mask,merge,op1,31);
+}
+
+
+vint16m8_t test___riscv_vsext_vf2_i16m8_tum(vbool2_t mask,vint16m8_t merge,vint8m4_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i16m8_tum(mask,merge,op1,31);
+}
+
+
+vint32mf2_t test___riscv_vsext_vf2_i32mf2_tum(vbool64_t mask,vint32mf2_t merge,vint16mf4_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i32mf2_tum(mask,merge,op1,31);
+}
+
+
+vint32m1_t test___riscv_vsext_vf2_i32m1_tum(vbool32_t mask,vint32m1_t merge,vint16mf2_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i32m1_tum(mask,merge,op1,31);
+}
+
+
+vint32m2_t test___riscv_vsext_vf2_i32m2_tum(vbool16_t mask,vint32m2_t merge,vint16m1_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i32m2_tum(mask,merge,op1,31);
+}
+
+
+vint32m4_t test___riscv_vsext_vf2_i32m4_tum(vbool8_t mask,vint32m4_t merge,vint16m2_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i32m4_tum(mask,merge,op1,31);
+}
+
+
+vint32m8_t test___riscv_vsext_vf2_i32m8_tum(vbool4_t mask,vint32m8_t merge,vint16m4_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i32m8_tum(mask,merge,op1,31);
+}
+
+
+vint64m1_t test___riscv_vsext_vf2_i64m1_tum(vbool64_t mask,vint64m1_t merge,vint32mf2_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i64m1_tum(mask,merge,op1,31);
+}
+
+
+vint64m2_t test___riscv_vsext_vf2_i64m2_tum(vbool32_t mask,vint64m2_t merge,vint32m1_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i64m2_tum(mask,merge,op1,31);
+}
+
+
+vint64m4_t test___riscv_vsext_vf2_i64m4_tum(vbool16_t mask,vint64m4_t merge,vint32m2_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i64m4_tum(mask,merge,op1,31);
+}
+
+
+vint64m8_t test___riscv_vsext_vf2_i64m8_tum(vbool8_t mask,vint64m8_t merge,vint32m4_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i64m8_tum(mask,merge,op1,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf2_tum-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf2_tum-3.c
new file mode 100644
index 00000000000..c524b7bcffe
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf2_tum-3.c
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vsext_vf2_i16mf4_tum(vbool64_t mask,vint16mf4_t merge,vint8mf8_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i16mf4_tum(mask,merge,op1,32);
+}
+
+
+vint16mf2_t test___riscv_vsext_vf2_i16mf2_tum(vbool32_t mask,vint16mf2_t merge,vint8mf4_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i16mf2_tum(mask,merge,op1,32);
+}
+
+
+vint16m1_t test___riscv_vsext_vf2_i16m1_tum(vbool16_t mask,vint16m1_t merge,vint8mf2_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i16m1_tum(mask,merge,op1,32);
+}
+
+
+vint16m2_t test___riscv_vsext_vf2_i16m2_tum(vbool8_t mask,vint16m2_t merge,vint8m1_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i16m2_tum(mask,merge,op1,32);
+}
+
+
+vint16m4_t test___riscv_vsext_vf2_i16m4_tum(vbool4_t mask,vint16m4_t merge,vint8m2_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i16m4_tum(mask,merge,op1,32);
+}
+
+
+vint16m8_t test___riscv_vsext_vf2_i16m8_tum(vbool2_t mask,vint16m8_t merge,vint8m4_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i16m8_tum(mask,merge,op1,32);
+}
+
+
+vint32mf2_t test___riscv_vsext_vf2_i32mf2_tum(vbool64_t mask,vint32mf2_t merge,vint16mf4_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i32mf2_tum(mask,merge,op1,32);
+}
+
+
+vint32m1_t test___riscv_vsext_vf2_i32m1_tum(vbool32_t mask,vint32m1_t merge,vint16mf2_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i32m1_tum(mask,merge,op1,32);
+}
+
+
+vint32m2_t test___riscv_vsext_vf2_i32m2_tum(vbool16_t mask,vint32m2_t merge,vint16m1_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i32m2_tum(mask,merge,op1,32);
+}
+
+
+vint32m4_t test___riscv_vsext_vf2_i32m4_tum(vbool8_t mask,vint32m4_t merge,vint16m2_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i32m4_tum(mask,merge,op1,32);
+}
+
+
+vint32m8_t test___riscv_vsext_vf2_i32m8_tum(vbool4_t mask,vint32m8_t merge,vint16m4_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i32m8_tum(mask,merge,op1,32);
+}
+
+
+vint64m1_t test___riscv_vsext_vf2_i64m1_tum(vbool64_t mask,vint64m1_t merge,vint32mf2_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i64m1_tum(mask,merge,op1,32);
+}
+
+
+vint64m2_t test___riscv_vsext_vf2_i64m2_tum(vbool32_t mask,vint64m2_t merge,vint32m1_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i64m2_tum(mask,merge,op1,32);
+}
+
+
+vint64m4_t test___riscv_vsext_vf2_i64m4_tum(vbool16_t mask,vint64m4_t merge,vint32m2_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i64m4_tum(mask,merge,op1,32);
+}
+
+
+vint64m8_t test___riscv_vsext_vf2_i64m8_tum(vbool8_t mask,vint64m8_t merge,vint32m4_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i64m8_tum(mask,merge,op1,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf2_tumu-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf2_tumu-1.c
new file mode 100644
index 00000000000..5bdb267a43a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf2_tumu-1.c
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vsext_vf2_i16mf4_tumu(vbool64_t mask,vint16mf4_t merge,vint8mf8_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i16mf4_tumu(mask,merge,op1,vl);
+}
+
+
+vint16mf2_t test___riscv_vsext_vf2_i16mf2_tumu(vbool32_t mask,vint16mf2_t merge,vint8mf4_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i16mf2_tumu(mask,merge,op1,vl);
+}
+
+
+vint16m1_t test___riscv_vsext_vf2_i16m1_tumu(vbool16_t mask,vint16m1_t merge,vint8mf2_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i16m1_tumu(mask,merge,op1,vl);
+}
+
+
+vint16m2_t test___riscv_vsext_vf2_i16m2_tumu(vbool8_t mask,vint16m2_t merge,vint8m1_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i16m2_tumu(mask,merge,op1,vl);
+}
+
+
+vint16m4_t test___riscv_vsext_vf2_i16m4_tumu(vbool4_t mask,vint16m4_t merge,vint8m2_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i16m4_tumu(mask,merge,op1,vl);
+}
+
+
+vint16m8_t test___riscv_vsext_vf2_i16m8_tumu(vbool2_t mask,vint16m8_t merge,vint8m4_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i16m8_tumu(mask,merge,op1,vl);
+}
+
+
+vint32mf2_t test___riscv_vsext_vf2_i32mf2_tumu(vbool64_t mask,vint32mf2_t merge,vint16mf4_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i32mf2_tumu(mask,merge,op1,vl);
+}
+
+
+vint32m1_t test___riscv_vsext_vf2_i32m1_tumu(vbool32_t mask,vint32m1_t merge,vint16mf2_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i32m1_tumu(mask,merge,op1,vl);
+}
+
+
+vint32m2_t test___riscv_vsext_vf2_i32m2_tumu(vbool16_t mask,vint32m2_t merge,vint16m1_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i32m2_tumu(mask,merge,op1,vl);
+}
+
+
+vint32m4_t test___riscv_vsext_vf2_i32m4_tumu(vbool8_t mask,vint32m4_t merge,vint16m2_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i32m4_tumu(mask,merge,op1,vl);
+}
+
+
+vint32m8_t test___riscv_vsext_vf2_i32m8_tumu(vbool4_t mask,vint32m8_t merge,vint16m4_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i32m8_tumu(mask,merge,op1,vl);
+}
+
+
+vint64m1_t test___riscv_vsext_vf2_i64m1_tumu(vbool64_t mask,vint64m1_t merge,vint32mf2_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i64m1_tumu(mask,merge,op1,vl);
+}
+
+
+vint64m2_t test___riscv_vsext_vf2_i64m2_tumu(vbool32_t mask,vint64m2_t merge,vint32m1_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i64m2_tumu(mask,merge,op1,vl);
+}
+
+
+vint64m4_t test___riscv_vsext_vf2_i64m4_tumu(vbool16_t mask,vint64m4_t merge,vint32m2_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i64m4_tumu(mask,merge,op1,vl);
+}
+
+
+vint64m8_t test___riscv_vsext_vf2_i64m8_tumu(vbool8_t mask,vint64m8_t merge,vint32m4_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i64m8_tumu(mask,merge,op1,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*mu\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*mu\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*mu\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*mu\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*mu\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*mu\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf2_tumu-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf2_tumu-2.c
new file mode 100644
index 00000000000..e1c7b1a5ede
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf2_tumu-2.c
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vsext_vf2_i16mf4_tumu(vbool64_t mask,vint16mf4_t merge,vint8mf8_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i16mf4_tumu(mask,merge,op1,31);
+}
+
+
+vint16mf2_t test___riscv_vsext_vf2_i16mf2_tumu(vbool32_t mask,vint16mf2_t merge,vint8mf4_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i16mf2_tumu(mask,merge,op1,31);
+}
+
+
+vint16m1_t test___riscv_vsext_vf2_i16m1_tumu(vbool16_t mask,vint16m1_t merge,vint8mf2_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i16m1_tumu(mask,merge,op1,31);
+}
+
+
+vint16m2_t test___riscv_vsext_vf2_i16m2_tumu(vbool8_t mask,vint16m2_t merge,vint8m1_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i16m2_tumu(mask,merge,op1,31);
+}
+
+
+vint16m4_t test___riscv_vsext_vf2_i16m4_tumu(vbool4_t mask,vint16m4_t merge,vint8m2_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i16m4_tumu(mask,merge,op1,31);
+}
+
+
+vint16m8_t test___riscv_vsext_vf2_i16m8_tumu(vbool2_t mask,vint16m8_t merge,vint8m4_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i16m8_tumu(mask,merge,op1,31);
+}
+
+
+vint32mf2_t test___riscv_vsext_vf2_i32mf2_tumu(vbool64_t mask,vint32mf2_t merge,vint16mf4_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i32mf2_tumu(mask,merge,op1,31);
+}
+
+
+vint32m1_t test___riscv_vsext_vf2_i32m1_tumu(vbool32_t mask,vint32m1_t merge,vint16mf2_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i32m1_tumu(mask,merge,op1,31);
+}
+
+
+vint32m2_t test___riscv_vsext_vf2_i32m2_tumu(vbool16_t mask,vint32m2_t merge,vint16m1_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i32m2_tumu(mask,merge,op1,31);
+}
+
+
+vint32m4_t test___riscv_vsext_vf2_i32m4_tumu(vbool8_t mask,vint32m4_t merge,vint16m2_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i32m4_tumu(mask,merge,op1,31);
+}
+
+
+vint32m8_t test___riscv_vsext_vf2_i32m8_tumu(vbool4_t mask,vint32m8_t merge,vint16m4_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i32m8_tumu(mask,merge,op1,31);
+}
+
+
+vint64m1_t test___riscv_vsext_vf2_i64m1_tumu(vbool64_t mask,vint64m1_t merge,vint32mf2_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i64m1_tumu(mask,merge,op1,31);
+}
+
+
+vint64m2_t test___riscv_vsext_vf2_i64m2_tumu(vbool32_t mask,vint64m2_t merge,vint32m1_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i64m2_tumu(mask,merge,op1,31);
+}
+
+
+vint64m4_t test___riscv_vsext_vf2_i64m4_tumu(vbool16_t mask,vint64m4_t merge,vint32m2_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i64m4_tumu(mask,merge,op1,31);
+}
+
+
+vint64m8_t test___riscv_vsext_vf2_i64m8_tumu(vbool8_t mask,vint64m8_t merge,vint32m4_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i64m8_tumu(mask,merge,op1,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*mu\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*mu\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*mu\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*mu\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*mu\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*mu\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*mu\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*mu\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*mu\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*mu\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*mu\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*mu\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*mu\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*mu\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*mu\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf2_tumu-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf2_tumu-3.c
new file mode 100644
index 00000000000..995b2a78d87
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf2_tumu-3.c
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vsext_vf2_i16mf4_tumu(vbool64_t mask,vint16mf4_t merge,vint8mf8_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i16mf4_tumu(mask,merge,op1,32);
+}
+
+
+vint16mf2_t test___riscv_vsext_vf2_i16mf2_tumu(vbool32_t mask,vint16mf2_t merge,vint8mf4_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i16mf2_tumu(mask,merge,op1,32);
+}
+
+
+vint16m1_t test___riscv_vsext_vf2_i16m1_tumu(vbool16_t mask,vint16m1_t merge,vint8mf2_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i16m1_tumu(mask,merge,op1,32);
+}
+
+
+vint16m2_t test___riscv_vsext_vf2_i16m2_tumu(vbool8_t mask,vint16m2_t merge,vint8m1_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i16m2_tumu(mask,merge,op1,32);
+}
+
+
+vint16m4_t test___riscv_vsext_vf2_i16m4_tumu(vbool4_t mask,vint16m4_t merge,vint8m2_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i16m4_tumu(mask,merge,op1,32);
+}
+
+
+vint16m8_t test___riscv_vsext_vf2_i16m8_tumu(vbool2_t mask,vint16m8_t merge,vint8m4_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i16m8_tumu(mask,merge,op1,32);
+}
+
+
+vint32mf2_t test___riscv_vsext_vf2_i32mf2_tumu(vbool64_t mask,vint32mf2_t merge,vint16mf4_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i32mf2_tumu(mask,merge,op1,32);
+}
+
+
+vint32m1_t test___riscv_vsext_vf2_i32m1_tumu(vbool32_t mask,vint32m1_t merge,vint16mf2_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i32m1_tumu(mask,merge,op1,32);
+}
+
+
+vint32m2_t test___riscv_vsext_vf2_i32m2_tumu(vbool16_t mask,vint32m2_t merge,vint16m1_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i32m2_tumu(mask,merge,op1,32);
+}
+
+
+vint32m4_t test___riscv_vsext_vf2_i32m4_tumu(vbool8_t mask,vint32m4_t merge,vint16m2_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i32m4_tumu(mask,merge,op1,32);
+}
+
+
+vint32m8_t test___riscv_vsext_vf2_i32m8_tumu(vbool4_t mask,vint32m8_t merge,vint16m4_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i32m8_tumu(mask,merge,op1,32);
+}
+
+
+vint64m1_t test___riscv_vsext_vf2_i64m1_tumu(vbool64_t mask,vint64m1_t merge,vint32mf2_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i64m1_tumu(mask,merge,op1,32);
+}
+
+
+vint64m2_t test___riscv_vsext_vf2_i64m2_tumu(vbool32_t mask,vint64m2_t merge,vint32m1_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i64m2_tumu(mask,merge,op1,32);
+}
+
+
+vint64m4_t test___riscv_vsext_vf2_i64m4_tumu(vbool16_t mask,vint64m4_t merge,vint32m2_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i64m4_tumu(mask,merge,op1,32);
+}
+
+
+vint64m8_t test___riscv_vsext_vf2_i64m8_tumu(vbool8_t mask,vint64m8_t merge,vint32m4_t op1,size_t vl)
+{
+    return __riscv_vsext_vf2_i64m8_tumu(mask,merge,op1,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*mu\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*mu\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*mu\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*mu\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*mu\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*mu\s+vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */