From patchwork Mon Feb 6 05:15:04 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "juzhe.zhong@rivai.ai" X-Patchwork-Id: 64336 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 8D99E3857BB3 for ; Mon, 6 Feb 2023 05:15:32 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from smtpbguseast1.qq.com (smtpbguseast1.qq.com [54.204.34.129]) by sourceware.org (Postfix) with ESMTPS id 2437D3858D1E for ; Mon, 6 Feb 2023 05:15:10 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 2437D3858D1E Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivai.ai Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivai.ai X-QQ-mid: bizesmtp72t1675660505tadq94fh Received: from server1.localdomain ( [58.60.1.22]) by bizesmtp.qq.com (ESMTP) with id ; Mon, 06 Feb 2023 13:15:05 +0800 (CST) X-QQ-SSF: 01400000000000E0L000000A0000000 X-QQ-FEAT: F6shoN2FPfK5jZf9yI+DcbnDC0l3gIEmMEN+hckhoXmTE4qHpqY6SpIgzmocQ eAbn6X6ptYgKK5pQzGTj6S4RUoa440/3LPsQ4B2roHNLT6aZglIM1SSZByExFKZmK5EzRYb 7M6Sk8holG/RksfySvl1XWCHhVOQ6fhp869p1WrxHg4je7sJ4nt/RYBNzhrRGXRUqELJ0jH e7NLxzoRleZZI4K8vldcl0HDJi2mMZlCFf8Zh8hdYdYR8CzkX0ScmRnO49hldhTzlhZVPkJ AgMlFbhBNlKH8Xw159u66GCH9ojD2AlCQAIrKBtSvYFW5zvOW1iY0ZSFc025XkvtF/wOjXy 8lEh/evQ65NJ+DK5C9CjTIuM/UT5CZNV/c/3I1ejowO3G3alvHRWwt99Nu2VTXBqRvYmLg5 X-QQ-GoodBg: 2 From: juzhe.zhong@rivai.ai To: gcc-patches@gcc.gnu.org Cc: kito.cheng@gmail.com, Ju-Zhe Zhong Subject: [PATCH] RISC-V: Add vsext.vf4 C API tests Date: Mon, 6 Feb 2023 13:15:04 +0800 Message-Id: <20230206051504.220629-1-juzhe.zhong@rivai.ai> X-Mailer: git-send-email 2.36.1 MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:rivai.ai:qybglogicsvr:qybglogicsvr7 X-Spam-Status: No, score=-10.9 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, KAM_SHORT, RCVD_IN_BARRACUDACENTRAL, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_PASS, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" From: Ju-Zhe Zhong gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/vsext_vf4-1.c: New test. * gcc.target/riscv/rvv/base/vsext_vf4-2.c: New test. * gcc.target/riscv/rvv/base/vsext_vf4-3.c: New test. * gcc.target/riscv/rvv/base/vsext_vf4_m-1.c: New test. * gcc.target/riscv/rvv/base/vsext_vf4_m-2.c: New test. * gcc.target/riscv/rvv/base/vsext_vf4_m-3.c: New test. * gcc.target/riscv/rvv/base/vsext_vf4_mu-1.c: New test. * gcc.target/riscv/rvv/base/vsext_vf4_mu-2.c: New test. * gcc.target/riscv/rvv/base/vsext_vf4_mu-3.c: New test. * gcc.target/riscv/rvv/base/vsext_vf4_tu-1.c: New test. * gcc.target/riscv/rvv/base/vsext_vf4_tu-2.c: New test. * gcc.target/riscv/rvv/base/vsext_vf4_tu-3.c: New test. * gcc.target/riscv/rvv/base/vsext_vf4_tum-1.c: New test. * gcc.target/riscv/rvv/base/vsext_vf4_tum-2.c: New test. * gcc.target/riscv/rvv/base/vsext_vf4_tum-3.c: New test. * gcc.target/riscv/rvv/base/vsext_vf4_tumu-1.c: New test. * gcc.target/riscv/rvv/base/vsext_vf4_tumu-2.c: New test. * gcc.target/riscv/rvv/base/vsext_vf4_tumu-3.c: New test. --- .../gcc.target/riscv/rvv/base/vsext_vf4-1.c | 69 +++++++++++++++++++ .../gcc.target/riscv/rvv/base/vsext_vf4-2.c | 69 +++++++++++++++++++ .../gcc.target/riscv/rvv/base/vsext_vf4-3.c | 69 +++++++++++++++++++ .../gcc.target/riscv/rvv/base/vsext_vf4_m-1.c | 69 +++++++++++++++++++ .../gcc.target/riscv/rvv/base/vsext_vf4_m-2.c | 69 +++++++++++++++++++ .../gcc.target/riscv/rvv/base/vsext_vf4_m-3.c | 69 +++++++++++++++++++ .../riscv/rvv/base/vsext_vf4_mu-1.c | 69 +++++++++++++++++++ .../riscv/rvv/base/vsext_vf4_mu-2.c | 69 +++++++++++++++++++ .../riscv/rvv/base/vsext_vf4_mu-3.c | 69 +++++++++++++++++++ .../riscv/rvv/base/vsext_vf4_tu-1.c | 69 +++++++++++++++++++ .../riscv/rvv/base/vsext_vf4_tu-2.c | 69 +++++++++++++++++++ .../riscv/rvv/base/vsext_vf4_tu-3.c | 69 +++++++++++++++++++ .../riscv/rvv/base/vsext_vf4_tum-1.c | 69 +++++++++++++++++++ .../riscv/rvv/base/vsext_vf4_tum-2.c | 69 +++++++++++++++++++ .../riscv/rvv/base/vsext_vf4_tum-3.c | 69 +++++++++++++++++++ .../riscv/rvv/base/vsext_vf4_tumu-1.c | 69 +++++++++++++++++++ .../riscv/rvv/base/vsext_vf4_tumu-2.c | 69 +++++++++++++++++++ .../riscv/rvv/base/vsext_vf4_tumu-3.c | 69 +++++++++++++++++++ 18 files changed, 1242 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf4-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf4-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf4-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf4_m-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf4_m-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf4_m-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf4_mu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf4_mu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf4_mu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf4_tu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf4_tu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf4_tu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf4_tum-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf4_tum-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf4_tum-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf4_tumu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf4_tumu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf4_tumu-3.c diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf4-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf4-1.c new file mode 100644 index 00000000000..f853ceafce9 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf4-1.c @@ -0,0 +1,69 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint32mf2_t test___riscv_vsext_vf4_i32mf2(vint8mf8_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i32mf2(op1,vl); +} + + +vint32m1_t test___riscv_vsext_vf4_i32m1(vint8mf4_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i32m1(op1,vl); +} + + +vint32m2_t test___riscv_vsext_vf4_i32m2(vint8mf2_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i32m2(op1,vl); +} + + +vint32m4_t test___riscv_vsext_vf4_i32m4(vint8m1_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i32m4(op1,vl); +} + + +vint32m8_t test___riscv_vsext_vf4_i32m8(vint8m2_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i32m8(op1,vl); +} + + +vint64m1_t test___riscv_vsext_vf4_i64m1(vint16mf4_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i64m1(op1,vl); +} + + +vint64m2_t test___riscv_vsext_vf4_i64m2(vint16mf2_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i64m2(op1,vl); +} + + +vint64m4_t test___riscv_vsext_vf4_i64m4(vint16m1_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i64m4(op1,vl); +} + + +vint64m8_t test___riscv_vsext_vf4_i64m8(vint16m2_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i64m8(op1,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf4-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf4-2.c new file mode 100644 index 00000000000..0f7c664bfab --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf4-2.c @@ -0,0 +1,69 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint32mf2_t test___riscv_vsext_vf4_i32mf2(vint8mf8_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i32mf2(op1,31); +} + + +vint32m1_t test___riscv_vsext_vf4_i32m1(vint8mf4_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i32m1(op1,31); +} + + +vint32m2_t test___riscv_vsext_vf4_i32m2(vint8mf2_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i32m2(op1,31); +} + + +vint32m4_t test___riscv_vsext_vf4_i32m4(vint8m1_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i32m4(op1,31); +} + + +vint32m8_t test___riscv_vsext_vf4_i32m8(vint8m2_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i32m8(op1,31); +} + + +vint64m1_t test___riscv_vsext_vf4_i64m1(vint16mf4_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i64m1(op1,31); +} + + +vint64m2_t test___riscv_vsext_vf4_i64m2(vint16mf2_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i64m2(op1,31); +} + + +vint64m4_t test___riscv_vsext_vf4_i64m4(vint16m1_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i64m4(op1,31); +} + + +vint64m8_t test___riscv_vsext_vf4_i64m8(vint16m2_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i64m8(op1,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf4-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf4-3.c new file mode 100644 index 00000000000..4741663e749 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf4-3.c @@ -0,0 +1,69 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint32mf2_t test___riscv_vsext_vf4_i32mf2(vint8mf8_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i32mf2(op1,32); +} + + +vint32m1_t test___riscv_vsext_vf4_i32m1(vint8mf4_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i32m1(op1,32); +} + + +vint32m2_t test___riscv_vsext_vf4_i32m2(vint8mf2_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i32m2(op1,32); +} + + +vint32m4_t test___riscv_vsext_vf4_i32m4(vint8m1_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i32m4(op1,32); +} + + +vint32m8_t test___riscv_vsext_vf4_i32m8(vint8m2_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i32m8(op1,32); +} + + +vint64m1_t test___riscv_vsext_vf4_i64m1(vint16mf4_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i64m1(op1,32); +} + + +vint64m2_t test___riscv_vsext_vf4_i64m2(vint16mf2_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i64m2(op1,32); +} + + +vint64m4_t test___riscv_vsext_vf4_i64m4(vint16m1_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i64m4(op1,32); +} + + +vint64m8_t test___riscv_vsext_vf4_i64m8(vint16m2_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i64m8(op1,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf4_m-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf4_m-1.c new file mode 100644 index 00000000000..53720508183 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf4_m-1.c @@ -0,0 +1,69 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint32mf2_t test___riscv_vsext_vf4_i32mf2_m(vbool64_t mask,vint8mf8_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i32mf2_m(mask,op1,vl); +} + + +vint32m1_t test___riscv_vsext_vf4_i32m1_m(vbool32_t mask,vint8mf4_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i32m1_m(mask,op1,vl); +} + + +vint32m2_t test___riscv_vsext_vf4_i32m2_m(vbool16_t mask,vint8mf2_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i32m2_m(mask,op1,vl); +} + + +vint32m4_t test___riscv_vsext_vf4_i32m4_m(vbool8_t mask,vint8m1_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i32m4_m(mask,op1,vl); +} + + +vint32m8_t test___riscv_vsext_vf4_i32m8_m(vbool4_t mask,vint8m2_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i32m8_m(mask,op1,vl); +} + + +vint64m1_t test___riscv_vsext_vf4_i64m1_m(vbool64_t mask,vint16mf4_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i64m1_m(mask,op1,vl); +} + + +vint64m2_t test___riscv_vsext_vf4_i64m2_m(vbool32_t mask,vint16mf2_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i64m2_m(mask,op1,vl); +} + + +vint64m4_t test___riscv_vsext_vf4_i64m4_m(vbool16_t mask,vint16m1_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i64m4_m(mask,op1,vl); +} + + +vint64m8_t test___riscv_vsext_vf4_i64m8_m(vbool8_t mask,vint16m2_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i64m8_m(mask,op1,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf4_m-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf4_m-2.c new file mode 100644 index 00000000000..cb993f8cea2 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf4_m-2.c @@ -0,0 +1,69 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint32mf2_t test___riscv_vsext_vf4_i32mf2_m(vbool64_t mask,vint8mf8_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i32mf2_m(mask,op1,31); +} + + +vint32m1_t test___riscv_vsext_vf4_i32m1_m(vbool32_t mask,vint8mf4_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i32m1_m(mask,op1,31); +} + + +vint32m2_t test___riscv_vsext_vf4_i32m2_m(vbool16_t mask,vint8mf2_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i32m2_m(mask,op1,31); +} + + +vint32m4_t test___riscv_vsext_vf4_i32m4_m(vbool8_t mask,vint8m1_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i32m4_m(mask,op1,31); +} + + +vint32m8_t test___riscv_vsext_vf4_i32m8_m(vbool4_t mask,vint8m2_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i32m8_m(mask,op1,31); +} + + +vint64m1_t test___riscv_vsext_vf4_i64m1_m(vbool64_t mask,vint16mf4_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i64m1_m(mask,op1,31); +} + + +vint64m2_t test___riscv_vsext_vf4_i64m2_m(vbool32_t mask,vint16mf2_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i64m2_m(mask,op1,31); +} + + +vint64m4_t test___riscv_vsext_vf4_i64m4_m(vbool16_t mask,vint16m1_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i64m4_m(mask,op1,31); +} + + +vint64m8_t test___riscv_vsext_vf4_i64m8_m(vbool8_t mask,vint16m2_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i64m8_m(mask,op1,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf4_m-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf4_m-3.c new file mode 100644 index 00000000000..69077cb00a4 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf4_m-3.c @@ -0,0 +1,69 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint32mf2_t test___riscv_vsext_vf4_i32mf2_m(vbool64_t mask,vint8mf8_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i32mf2_m(mask,op1,32); +} + + +vint32m1_t test___riscv_vsext_vf4_i32m1_m(vbool32_t mask,vint8mf4_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i32m1_m(mask,op1,32); +} + + +vint32m2_t test___riscv_vsext_vf4_i32m2_m(vbool16_t mask,vint8mf2_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i32m2_m(mask,op1,32); +} + + +vint32m4_t test___riscv_vsext_vf4_i32m4_m(vbool8_t mask,vint8m1_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i32m4_m(mask,op1,32); +} + + +vint32m8_t test___riscv_vsext_vf4_i32m8_m(vbool4_t mask,vint8m2_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i32m8_m(mask,op1,32); +} + + +vint64m1_t test___riscv_vsext_vf4_i64m1_m(vbool64_t mask,vint16mf4_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i64m1_m(mask,op1,32); +} + + +vint64m2_t test___riscv_vsext_vf4_i64m2_m(vbool32_t mask,vint16mf2_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i64m2_m(mask,op1,32); +} + + +vint64m4_t test___riscv_vsext_vf4_i64m4_m(vbool16_t mask,vint16m1_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i64m4_m(mask,op1,32); +} + + +vint64m8_t test___riscv_vsext_vf4_i64m8_m(vbool8_t mask,vint16m2_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i64m8_m(mask,op1,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf4_mu-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf4_mu-1.c new file mode 100644 index 00000000000..59ccaa7483b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf4_mu-1.c @@ -0,0 +1,69 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint32mf2_t test___riscv_vsext_vf4_i32mf2_mu(vbool64_t mask,vint32mf2_t merge,vint8mf8_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i32mf2_mu(mask,merge,op1,vl); +} + + +vint32m1_t test___riscv_vsext_vf4_i32m1_mu(vbool32_t mask,vint32m1_t merge,vint8mf4_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i32m1_mu(mask,merge,op1,vl); +} + + +vint32m2_t test___riscv_vsext_vf4_i32m2_mu(vbool16_t mask,vint32m2_t merge,vint8mf2_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i32m2_mu(mask,merge,op1,vl); +} + + +vint32m4_t test___riscv_vsext_vf4_i32m4_mu(vbool8_t mask,vint32m4_t merge,vint8m1_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i32m4_mu(mask,merge,op1,vl); +} + + +vint32m8_t test___riscv_vsext_vf4_i32m8_mu(vbool4_t mask,vint32m8_t merge,vint8m2_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i32m8_mu(mask,merge,op1,vl); +} + + +vint64m1_t test___riscv_vsext_vf4_i64m1_mu(vbool64_t mask,vint64m1_t merge,vint16mf4_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i64m1_mu(mask,merge,op1,vl); +} + + +vint64m2_t test___riscv_vsext_vf4_i64m2_mu(vbool32_t mask,vint64m2_t merge,vint16mf2_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i64m2_mu(mask,merge,op1,vl); +} + + +vint64m4_t test___riscv_vsext_vf4_i64m4_mu(vbool16_t mask,vint64m4_t merge,vint16m1_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i64m4_mu(mask,merge,op1,vl); +} + + +vint64m8_t test___riscv_vsext_vf4_i64m8_mu(vbool8_t mask,vint64m8_t merge,vint16m2_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i64m8_mu(mask,merge,op1,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*mu\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*mu\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*mu\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*mu\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf4_mu-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf4_mu-2.c new file mode 100644 index 00000000000..13766dfded7 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf4_mu-2.c @@ -0,0 +1,69 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint32mf2_t test___riscv_vsext_vf4_i32mf2_mu(vbool64_t mask,vint32mf2_t merge,vint8mf8_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i32mf2_mu(mask,merge,op1,31); +} + + +vint32m1_t test___riscv_vsext_vf4_i32m1_mu(vbool32_t mask,vint32m1_t merge,vint8mf4_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i32m1_mu(mask,merge,op1,31); +} + + +vint32m2_t test___riscv_vsext_vf4_i32m2_mu(vbool16_t mask,vint32m2_t merge,vint8mf2_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i32m2_mu(mask,merge,op1,31); +} + + +vint32m4_t test___riscv_vsext_vf4_i32m4_mu(vbool8_t mask,vint32m4_t merge,vint8m1_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i32m4_mu(mask,merge,op1,31); +} + + +vint32m8_t test___riscv_vsext_vf4_i32m8_mu(vbool4_t mask,vint32m8_t merge,vint8m2_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i32m8_mu(mask,merge,op1,31); +} + + +vint64m1_t test___riscv_vsext_vf4_i64m1_mu(vbool64_t mask,vint64m1_t merge,vint16mf4_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i64m1_mu(mask,merge,op1,31); +} + + +vint64m2_t test___riscv_vsext_vf4_i64m2_mu(vbool32_t mask,vint64m2_t merge,vint16mf2_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i64m2_mu(mask,merge,op1,31); +} + + +vint64m4_t test___riscv_vsext_vf4_i64m4_mu(vbool16_t mask,vint64m4_t merge,vint16m1_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i64m4_mu(mask,merge,op1,31); +} + + +vint64m8_t test___riscv_vsext_vf4_i64m8_mu(vbool8_t mask,vint64m8_t merge,vint16m2_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i64m8_mu(mask,merge,op1,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*mu\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*mu\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*mu\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*mu\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*mu\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*mu\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*mu\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*mu\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf4_mu-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf4_mu-3.c new file mode 100644 index 00000000000..adccce339b6 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf4_mu-3.c @@ -0,0 +1,69 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint32mf2_t test___riscv_vsext_vf4_i32mf2_mu(vbool64_t mask,vint32mf2_t merge,vint8mf8_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i32mf2_mu(mask,merge,op1,32); +} + + +vint32m1_t test___riscv_vsext_vf4_i32m1_mu(vbool32_t mask,vint32m1_t merge,vint8mf4_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i32m1_mu(mask,merge,op1,32); +} + + +vint32m2_t test___riscv_vsext_vf4_i32m2_mu(vbool16_t mask,vint32m2_t merge,vint8mf2_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i32m2_mu(mask,merge,op1,32); +} + + +vint32m4_t test___riscv_vsext_vf4_i32m4_mu(vbool8_t mask,vint32m4_t merge,vint8m1_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i32m4_mu(mask,merge,op1,32); +} + + +vint32m8_t test___riscv_vsext_vf4_i32m8_mu(vbool4_t mask,vint32m8_t merge,vint8m2_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i32m8_mu(mask,merge,op1,32); +} + + +vint64m1_t test___riscv_vsext_vf4_i64m1_mu(vbool64_t mask,vint64m1_t merge,vint16mf4_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i64m1_mu(mask,merge,op1,32); +} + + +vint64m2_t test___riscv_vsext_vf4_i64m2_mu(vbool32_t mask,vint64m2_t merge,vint16mf2_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i64m2_mu(mask,merge,op1,32); +} + + +vint64m4_t test___riscv_vsext_vf4_i64m4_mu(vbool16_t mask,vint64m4_t merge,vint16m1_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i64m4_mu(mask,merge,op1,32); +} + + +vint64m8_t test___riscv_vsext_vf4_i64m8_mu(vbool8_t mask,vint64m8_t merge,vint16m2_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i64m8_mu(mask,merge,op1,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*mu\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*mu\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*mu\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*mu\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf4_tu-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf4_tu-1.c new file mode 100644 index 00000000000..5b65b33661f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf4_tu-1.c @@ -0,0 +1,69 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint32mf2_t test___riscv_vsext_vf4_i32mf2_tu(vint32mf2_t merge,vint8mf8_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i32mf2_tu(merge,op1,vl); +} + + +vint32m1_t test___riscv_vsext_vf4_i32m1_tu(vint32m1_t merge,vint8mf4_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i32m1_tu(merge,op1,vl); +} + + +vint32m2_t test___riscv_vsext_vf4_i32m2_tu(vint32m2_t merge,vint8mf2_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i32m2_tu(merge,op1,vl); +} + + +vint32m4_t test___riscv_vsext_vf4_i32m4_tu(vint32m4_t merge,vint8m1_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i32m4_tu(merge,op1,vl); +} + + +vint32m8_t test___riscv_vsext_vf4_i32m8_tu(vint32m8_t merge,vint8m2_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i32m8_tu(merge,op1,vl); +} + + +vint64m1_t test___riscv_vsext_vf4_i64m1_tu(vint64m1_t merge,vint16mf4_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i64m1_tu(merge,op1,vl); +} + + +vint64m2_t test___riscv_vsext_vf4_i64m2_tu(vint64m2_t merge,vint16mf2_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i64m2_tu(merge,op1,vl); +} + + +vint64m4_t test___riscv_vsext_vf4_i64m4_tu(vint64m4_t merge,vint16m1_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i64m4_tu(merge,op1,vl); +} + + +vint64m8_t test___riscv_vsext_vf4_i64m8_tu(vint64m8_t merge,vint16m2_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i64m8_tu(merge,op1,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf4_tu-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf4_tu-2.c new file mode 100644 index 00000000000..975b9e23389 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf4_tu-2.c @@ -0,0 +1,69 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint32mf2_t test___riscv_vsext_vf4_i32mf2_tu(vint32mf2_t merge,vint8mf8_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i32mf2_tu(merge,op1,31); +} + + +vint32m1_t test___riscv_vsext_vf4_i32m1_tu(vint32m1_t merge,vint8mf4_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i32m1_tu(merge,op1,31); +} + + +vint32m2_t test___riscv_vsext_vf4_i32m2_tu(vint32m2_t merge,vint8mf2_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i32m2_tu(merge,op1,31); +} + + +vint32m4_t test___riscv_vsext_vf4_i32m4_tu(vint32m4_t merge,vint8m1_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i32m4_tu(merge,op1,31); +} + + +vint32m8_t test___riscv_vsext_vf4_i32m8_tu(vint32m8_t merge,vint8m2_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i32m8_tu(merge,op1,31); +} + + +vint64m1_t test___riscv_vsext_vf4_i64m1_tu(vint64m1_t merge,vint16mf4_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i64m1_tu(merge,op1,31); +} + + +vint64m2_t test___riscv_vsext_vf4_i64m2_tu(vint64m2_t merge,vint16mf2_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i64m2_tu(merge,op1,31); +} + + +vint64m4_t test___riscv_vsext_vf4_i64m4_tu(vint64m4_t merge,vint16m1_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i64m4_tu(merge,op1,31); +} + + +vint64m8_t test___riscv_vsext_vf4_i64m8_tu(vint64m8_t merge,vint16m2_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i64m8_tu(merge,op1,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf4_tu-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf4_tu-3.c new file mode 100644 index 00000000000..173725af839 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf4_tu-3.c @@ -0,0 +1,69 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint32mf2_t test___riscv_vsext_vf4_i32mf2_tu(vint32mf2_t merge,vint8mf8_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i32mf2_tu(merge,op1,32); +} + + +vint32m1_t test___riscv_vsext_vf4_i32m1_tu(vint32m1_t merge,vint8mf4_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i32m1_tu(merge,op1,32); +} + + +vint32m2_t test___riscv_vsext_vf4_i32m2_tu(vint32m2_t merge,vint8mf2_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i32m2_tu(merge,op1,32); +} + + +vint32m4_t test___riscv_vsext_vf4_i32m4_tu(vint32m4_t merge,vint8m1_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i32m4_tu(merge,op1,32); +} + + +vint32m8_t test___riscv_vsext_vf4_i32m8_tu(vint32m8_t merge,vint8m2_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i32m8_tu(merge,op1,32); +} + + +vint64m1_t test___riscv_vsext_vf4_i64m1_tu(vint64m1_t merge,vint16mf4_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i64m1_tu(merge,op1,32); +} + + +vint64m2_t test___riscv_vsext_vf4_i64m2_tu(vint64m2_t merge,vint16mf2_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i64m2_tu(merge,op1,32); +} + + +vint64m4_t test___riscv_vsext_vf4_i64m4_tu(vint64m4_t merge,vint16m1_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i64m4_tu(merge,op1,32); +} + + +vint64m8_t test___riscv_vsext_vf4_i64m8_tu(vint64m8_t merge,vint16m2_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i64m8_tu(merge,op1,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf4_tum-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf4_tum-1.c new file mode 100644 index 00000000000..5f54036eef5 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf4_tum-1.c @@ -0,0 +1,69 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint32mf2_t test___riscv_vsext_vf4_i32mf2_tum(vbool64_t mask,vint32mf2_t merge,vint8mf8_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i32mf2_tum(mask,merge,op1,vl); +} + + +vint32m1_t test___riscv_vsext_vf4_i32m1_tum(vbool32_t mask,vint32m1_t merge,vint8mf4_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i32m1_tum(mask,merge,op1,vl); +} + + +vint32m2_t test___riscv_vsext_vf4_i32m2_tum(vbool16_t mask,vint32m2_t merge,vint8mf2_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i32m2_tum(mask,merge,op1,vl); +} + + +vint32m4_t test___riscv_vsext_vf4_i32m4_tum(vbool8_t mask,vint32m4_t merge,vint8m1_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i32m4_tum(mask,merge,op1,vl); +} + + +vint32m8_t test___riscv_vsext_vf4_i32m8_tum(vbool4_t mask,vint32m8_t merge,vint8m2_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i32m8_tum(mask,merge,op1,vl); +} + + +vint64m1_t test___riscv_vsext_vf4_i64m1_tum(vbool64_t mask,vint64m1_t merge,vint16mf4_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i64m1_tum(mask,merge,op1,vl); +} + + +vint64m2_t test___riscv_vsext_vf4_i64m2_tum(vbool32_t mask,vint64m2_t merge,vint16mf2_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i64m2_tum(mask,merge,op1,vl); +} + + +vint64m4_t test___riscv_vsext_vf4_i64m4_tum(vbool16_t mask,vint64m4_t merge,vint16m1_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i64m4_tum(mask,merge,op1,vl); +} + + +vint64m8_t test___riscv_vsext_vf4_i64m8_tum(vbool8_t mask,vint64m8_t merge,vint16m2_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i64m8_tum(mask,merge,op1,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf4_tum-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf4_tum-2.c new file mode 100644 index 00000000000..5b48fcbda92 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf4_tum-2.c @@ -0,0 +1,69 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint32mf2_t test___riscv_vsext_vf4_i32mf2_tum(vbool64_t mask,vint32mf2_t merge,vint8mf8_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i32mf2_tum(mask,merge,op1,31); +} + + +vint32m1_t test___riscv_vsext_vf4_i32m1_tum(vbool32_t mask,vint32m1_t merge,vint8mf4_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i32m1_tum(mask,merge,op1,31); +} + + +vint32m2_t test___riscv_vsext_vf4_i32m2_tum(vbool16_t mask,vint32m2_t merge,vint8mf2_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i32m2_tum(mask,merge,op1,31); +} + + +vint32m4_t test___riscv_vsext_vf4_i32m4_tum(vbool8_t mask,vint32m4_t merge,vint8m1_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i32m4_tum(mask,merge,op1,31); +} + + +vint32m8_t test___riscv_vsext_vf4_i32m8_tum(vbool4_t mask,vint32m8_t merge,vint8m2_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i32m8_tum(mask,merge,op1,31); +} + + +vint64m1_t test___riscv_vsext_vf4_i64m1_tum(vbool64_t mask,vint64m1_t merge,vint16mf4_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i64m1_tum(mask,merge,op1,31); +} + + +vint64m2_t test___riscv_vsext_vf4_i64m2_tum(vbool32_t mask,vint64m2_t merge,vint16mf2_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i64m2_tum(mask,merge,op1,31); +} + + +vint64m4_t test___riscv_vsext_vf4_i64m4_tum(vbool16_t mask,vint64m4_t merge,vint16m1_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i64m4_tum(mask,merge,op1,31); +} + + +vint64m8_t test___riscv_vsext_vf4_i64m8_tum(vbool8_t mask,vint64m8_t merge,vint16m2_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i64m8_tum(mask,merge,op1,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf4_tum-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf4_tum-3.c new file mode 100644 index 00000000000..0a620e4a1ea --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf4_tum-3.c @@ -0,0 +1,69 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint32mf2_t test___riscv_vsext_vf4_i32mf2_tum(vbool64_t mask,vint32mf2_t merge,vint8mf8_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i32mf2_tum(mask,merge,op1,32); +} + + +vint32m1_t test___riscv_vsext_vf4_i32m1_tum(vbool32_t mask,vint32m1_t merge,vint8mf4_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i32m1_tum(mask,merge,op1,32); +} + + +vint32m2_t test___riscv_vsext_vf4_i32m2_tum(vbool16_t mask,vint32m2_t merge,vint8mf2_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i32m2_tum(mask,merge,op1,32); +} + + +vint32m4_t test___riscv_vsext_vf4_i32m4_tum(vbool8_t mask,vint32m4_t merge,vint8m1_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i32m4_tum(mask,merge,op1,32); +} + + +vint32m8_t test___riscv_vsext_vf4_i32m8_tum(vbool4_t mask,vint32m8_t merge,vint8m2_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i32m8_tum(mask,merge,op1,32); +} + + +vint64m1_t test___riscv_vsext_vf4_i64m1_tum(vbool64_t mask,vint64m1_t merge,vint16mf4_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i64m1_tum(mask,merge,op1,32); +} + + +vint64m2_t test___riscv_vsext_vf4_i64m2_tum(vbool32_t mask,vint64m2_t merge,vint16mf2_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i64m2_tum(mask,merge,op1,32); +} + + +vint64m4_t test___riscv_vsext_vf4_i64m4_tum(vbool16_t mask,vint64m4_t merge,vint16m1_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i64m4_tum(mask,merge,op1,32); +} + + +vint64m8_t test___riscv_vsext_vf4_i64m8_tum(vbool8_t mask,vint64m8_t merge,vint16m2_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i64m8_tum(mask,merge,op1,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf4_tumu-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf4_tumu-1.c new file mode 100644 index 00000000000..0419de80927 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf4_tumu-1.c @@ -0,0 +1,69 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint32mf2_t test___riscv_vsext_vf4_i32mf2_tumu(vbool64_t mask,vint32mf2_t merge,vint8mf8_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i32mf2_tumu(mask,merge,op1,vl); +} + + +vint32m1_t test___riscv_vsext_vf4_i32m1_tumu(vbool32_t mask,vint32m1_t merge,vint8mf4_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i32m1_tumu(mask,merge,op1,vl); +} + + +vint32m2_t test___riscv_vsext_vf4_i32m2_tumu(vbool16_t mask,vint32m2_t merge,vint8mf2_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i32m2_tumu(mask,merge,op1,vl); +} + + +vint32m4_t test___riscv_vsext_vf4_i32m4_tumu(vbool8_t mask,vint32m4_t merge,vint8m1_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i32m4_tumu(mask,merge,op1,vl); +} + + +vint32m8_t test___riscv_vsext_vf4_i32m8_tumu(vbool4_t mask,vint32m8_t merge,vint8m2_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i32m8_tumu(mask,merge,op1,vl); +} + + +vint64m1_t test___riscv_vsext_vf4_i64m1_tumu(vbool64_t mask,vint64m1_t merge,vint16mf4_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i64m1_tumu(mask,merge,op1,vl); +} + + +vint64m2_t test___riscv_vsext_vf4_i64m2_tumu(vbool32_t mask,vint64m2_t merge,vint16mf2_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i64m2_tumu(mask,merge,op1,vl); +} + + +vint64m4_t test___riscv_vsext_vf4_i64m4_tumu(vbool16_t mask,vint64m4_t merge,vint16m1_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i64m4_tumu(mask,merge,op1,vl); +} + + +vint64m8_t test___riscv_vsext_vf4_i64m8_tumu(vbool8_t mask,vint64m8_t merge,vint16m2_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i64m8_tumu(mask,merge,op1,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*mu\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*mu\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*mu\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*mu\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*mu\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf4_tumu-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf4_tumu-2.c new file mode 100644 index 00000000000..4451144077c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf4_tumu-2.c @@ -0,0 +1,69 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint32mf2_t test___riscv_vsext_vf4_i32mf2_tumu(vbool64_t mask,vint32mf2_t merge,vint8mf8_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i32mf2_tumu(mask,merge,op1,31); +} + + +vint32m1_t test___riscv_vsext_vf4_i32m1_tumu(vbool32_t mask,vint32m1_t merge,vint8mf4_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i32m1_tumu(mask,merge,op1,31); +} + + +vint32m2_t test___riscv_vsext_vf4_i32m2_tumu(vbool16_t mask,vint32m2_t merge,vint8mf2_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i32m2_tumu(mask,merge,op1,31); +} + + +vint32m4_t test___riscv_vsext_vf4_i32m4_tumu(vbool8_t mask,vint32m4_t merge,vint8m1_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i32m4_tumu(mask,merge,op1,31); +} + + +vint32m8_t test___riscv_vsext_vf4_i32m8_tumu(vbool4_t mask,vint32m8_t merge,vint8m2_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i32m8_tumu(mask,merge,op1,31); +} + + +vint64m1_t test___riscv_vsext_vf4_i64m1_tumu(vbool64_t mask,vint64m1_t merge,vint16mf4_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i64m1_tumu(mask,merge,op1,31); +} + + +vint64m2_t test___riscv_vsext_vf4_i64m2_tumu(vbool32_t mask,vint64m2_t merge,vint16mf2_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i64m2_tumu(mask,merge,op1,31); +} + + +vint64m4_t test___riscv_vsext_vf4_i64m4_tumu(vbool16_t mask,vint64m4_t merge,vint16m1_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i64m4_tumu(mask,merge,op1,31); +} + + +vint64m8_t test___riscv_vsext_vf4_i64m8_tumu(vbool8_t mask,vint64m8_t merge,vint16m2_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i64m8_tumu(mask,merge,op1,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*mu\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*mu\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*mu\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*mu\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*mu\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*mu\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*mu\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*mu\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*mu\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf4_tumu-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf4_tumu-3.c new file mode 100644 index 00000000000..71bd40dcae7 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf4_tumu-3.c @@ -0,0 +1,69 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint32mf2_t test___riscv_vsext_vf4_i32mf2_tumu(vbool64_t mask,vint32mf2_t merge,vint8mf8_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i32mf2_tumu(mask,merge,op1,32); +} + + +vint32m1_t test___riscv_vsext_vf4_i32m1_tumu(vbool32_t mask,vint32m1_t merge,vint8mf4_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i32m1_tumu(mask,merge,op1,32); +} + + +vint32m2_t test___riscv_vsext_vf4_i32m2_tumu(vbool16_t mask,vint32m2_t merge,vint8mf2_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i32m2_tumu(mask,merge,op1,32); +} + + +vint32m4_t test___riscv_vsext_vf4_i32m4_tumu(vbool8_t mask,vint32m4_t merge,vint8m1_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i32m4_tumu(mask,merge,op1,32); +} + + +vint32m8_t test___riscv_vsext_vf4_i32m8_tumu(vbool4_t mask,vint32m8_t merge,vint8m2_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i32m8_tumu(mask,merge,op1,32); +} + + +vint64m1_t test___riscv_vsext_vf4_i64m1_tumu(vbool64_t mask,vint64m1_t merge,vint16mf4_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i64m1_tumu(mask,merge,op1,32); +} + + +vint64m2_t test___riscv_vsext_vf4_i64m2_tumu(vbool32_t mask,vint64m2_t merge,vint16mf2_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i64m2_tumu(mask,merge,op1,32); +} + + +vint64m4_t test___riscv_vsext_vf4_i64m4_tumu(vbool16_t mask,vint64m4_t merge,vint16m1_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i64m4_tumu(mask,merge,op1,32); +} + + +vint64m8_t test___riscv_vsext_vf4_i64m8_tumu(vbool8_t mask,vint64m8_t merge,vint16m2_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i64m8_tumu(mask,merge,op1,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*mu\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*mu\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*mu\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*mu\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*mu\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */