diff mbox series

RISC-V: Add vzext.vf8 C API tests

Message ID 20230206050839.214506-1-juzhe.zhong@rivai.ai
State Committed
Commit a2da134248bbfa0cdaf196e4c859ce5cf4bb1e80
Headers
Series RISC-V: Add vzext.vf8 C API tests |

Commit Message

钟居哲 Feb. 6, 2023, 5:08 a.m. UTC 
  From: Ju-Zhe Zhong <juzhe.zhong@rivai.ai>

gcc/testsuite/ChangeLog:

        * gcc.target/riscv/rvv/base/vzext_vf8-1.c: New test.
        * gcc.target/riscv/rvv/base/vzext_vf8-2.c: New test.
        * gcc.target/riscv/rvv/base/vzext_vf8-3.c: New test.
        * gcc.target/riscv/rvv/base/vzext_vf8_m-1.c: New test.
        * gcc.target/riscv/rvv/base/vzext_vf8_m-2.c: New test.
        * gcc.target/riscv/rvv/base/vzext_vf8_m-3.c: New test.
        * gcc.target/riscv/rvv/base/vzext_vf8_mu-1.c: New test.
        * gcc.target/riscv/rvv/base/vzext_vf8_mu-2.c: New test.
        * gcc.target/riscv/rvv/base/vzext_vf8_mu-3.c: New test.
        * gcc.target/riscv/rvv/base/vzext_vf8_tu-1.c: New test.
        * gcc.target/riscv/rvv/base/vzext_vf8_tu-2.c: New test.
        * gcc.target/riscv/rvv/base/vzext_vf8_tu-3.c: New test.
        * gcc.target/riscv/rvv/base/vzext_vf8_tum-1.c: New test.
        * gcc.target/riscv/rvv/base/vzext_vf8_tum-2.c: New test.
        * gcc.target/riscv/rvv/base/vzext_vf8_tum-3.c: New test.
        * gcc.target/riscv/rvv/base/vzext_vf8_tumu-1.c: New test.
        * gcc.target/riscv/rvv/base/vzext_vf8_tumu-2.c: New test.
        * gcc.target/riscv/rvv/base/vzext_vf8_tumu-3.c: New test.

---
 .../gcc.target/riscv/rvv/base/vzext_vf8-1.c   | 34 +++++++++++++++++++
 .../gcc.target/riscv/rvv/base/vzext_vf8-2.c   | 34 +++++++++++++++++++
 .../gcc.target/riscv/rvv/base/vzext_vf8-3.c   | 34 +++++++++++++++++++
 .../gcc.target/riscv/rvv/base/vzext_vf8_m-1.c | 34 +++++++++++++++++++
 .../gcc.target/riscv/rvv/base/vzext_vf8_m-2.c | 34 +++++++++++++++++++
 .../gcc.target/riscv/rvv/base/vzext_vf8_m-3.c | 34 +++++++++++++++++++
 .../riscv/rvv/base/vzext_vf8_mu-1.c           | 34 +++++++++++++++++++
 .../riscv/rvv/base/vzext_vf8_mu-2.c           | 34 +++++++++++++++++++
 .../riscv/rvv/base/vzext_vf8_mu-3.c           | 34 +++++++++++++++++++
 .../riscv/rvv/base/vzext_vf8_tu-1.c           | 34 +++++++++++++++++++
 .../riscv/rvv/base/vzext_vf8_tu-2.c           | 34 +++++++++++++++++++
 .../riscv/rvv/base/vzext_vf8_tu-3.c           | 34 +++++++++++++++++++
 .../riscv/rvv/base/vzext_vf8_tum-1.c          | 34 +++++++++++++++++++
 .../riscv/rvv/base/vzext_vf8_tum-2.c          | 34 +++++++++++++++++++
 .../riscv/rvv/base/vzext_vf8_tum-3.c          | 34 +++++++++++++++++++
 .../riscv/rvv/base/vzext_vf8_tumu-1.c         | 34 +++++++++++++++++++
 .../riscv/rvv/base/vzext_vf8_tumu-2.c         | 34 +++++++++++++++++++
 .../riscv/rvv/base/vzext_vf8_tumu-3.c         | 34 +++++++++++++++++++
 18 files changed, 612 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf8-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf8-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf8-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf8_m-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf8_m-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf8_m-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf8_mu-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf8_mu-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf8_mu-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf8_tu-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf8_tu-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf8_tu-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf8_tum-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf8_tum-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf8_tum-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf8_tumu-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf8_tumu-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf8_tumu-3.c
diff mbox series

Patch

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf8-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf8-1.c
new file mode 100644
index 00000000000..c0620ec27b1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf8-1.c
@@ -0,0 +1,34 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint64m1_t test___riscv_vzext_vf8_u64m1(vuint8mf8_t op1,size_t vl)
+{
+    return __riscv_vzext_vf8_u64m1(op1,vl);
+}
+
+
+vuint64m2_t test___riscv_vzext_vf8_u64m2(vuint8mf4_t op1,size_t vl)
+{
+    return __riscv_vzext_vf8_u64m2(op1,vl);
+}
+
+
+vuint64m4_t test___riscv_vzext_vf8_u64m4(vuint8mf2_t op1,size_t vl)
+{
+    return __riscv_vzext_vf8_u64m4(op1,vl);
+}
+
+
+vuint64m8_t test___riscv_vzext_vf8_u64m8(vuint8m1_t op1,size_t vl)
+{
+    return __riscv_vzext_vf8_u64m8(op1,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf8-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf8-2.c
new file mode 100644
index 00000000000..6a191aef61f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf8-2.c
@@ -0,0 +1,34 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint64m1_t test___riscv_vzext_vf8_u64m1(vuint8mf8_t op1,size_t vl)
+{
+    return __riscv_vzext_vf8_u64m1(op1,31);
+}
+
+
+vuint64m2_t test___riscv_vzext_vf8_u64m2(vuint8mf4_t op1,size_t vl)
+{
+    return __riscv_vzext_vf8_u64m2(op1,31);
+}
+
+
+vuint64m4_t test___riscv_vzext_vf8_u64m4(vuint8mf2_t op1,size_t vl)
+{
+    return __riscv_vzext_vf8_u64m4(op1,31);
+}
+
+
+vuint64m8_t test___riscv_vzext_vf8_u64m8(vuint8m1_t op1,size_t vl)
+{
+    return __riscv_vzext_vf8_u64m8(op1,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf8-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf8-3.c
new file mode 100644
index 00000000000..f29adaf3b0b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf8-3.c
@@ -0,0 +1,34 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint64m1_t test___riscv_vzext_vf8_u64m1(vuint8mf8_t op1,size_t vl)
+{
+    return __riscv_vzext_vf8_u64m1(op1,32);
+}
+
+
+vuint64m2_t test___riscv_vzext_vf8_u64m2(vuint8mf4_t op1,size_t vl)
+{
+    return __riscv_vzext_vf8_u64m2(op1,32);
+}
+
+
+vuint64m4_t test___riscv_vzext_vf8_u64m4(vuint8mf2_t op1,size_t vl)
+{
+    return __riscv_vzext_vf8_u64m4(op1,32);
+}
+
+
+vuint64m8_t test___riscv_vzext_vf8_u64m8(vuint8m1_t op1,size_t vl)
+{
+    return __riscv_vzext_vf8_u64m8(op1,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf8_m-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf8_m-1.c
new file mode 100644
index 00000000000..bb35704346f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf8_m-1.c
@@ -0,0 +1,34 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint64m1_t test___riscv_vzext_vf8_u64m1_m(vbool64_t mask,vuint8mf8_t op1,size_t vl)
+{
+    return __riscv_vzext_vf8_u64m1_m(mask,op1,vl);
+}
+
+
+vuint64m2_t test___riscv_vzext_vf8_u64m2_m(vbool32_t mask,vuint8mf4_t op1,size_t vl)
+{
+    return __riscv_vzext_vf8_u64m2_m(mask,op1,vl);
+}
+
+
+vuint64m4_t test___riscv_vzext_vf8_u64m4_m(vbool16_t mask,vuint8mf2_t op1,size_t vl)
+{
+    return __riscv_vzext_vf8_u64m4_m(mask,op1,vl);
+}
+
+
+vuint64m8_t test___riscv_vzext_vf8_u64m8_m(vbool8_t mask,vuint8m1_t op1,size_t vl)
+{
+    return __riscv_vzext_vf8_u64m8_m(mask,op1,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf8_m-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf8_m-2.c
new file mode 100644
index 00000000000..d93cf35f876
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf8_m-2.c
@@ -0,0 +1,34 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint64m1_t test___riscv_vzext_vf8_u64m1_m(vbool64_t mask,vuint8mf8_t op1,size_t vl)
+{
+    return __riscv_vzext_vf8_u64m1_m(mask,op1,31);
+}
+
+
+vuint64m2_t test___riscv_vzext_vf8_u64m2_m(vbool32_t mask,vuint8mf4_t op1,size_t vl)
+{
+    return __riscv_vzext_vf8_u64m2_m(mask,op1,31);
+}
+
+
+vuint64m4_t test___riscv_vzext_vf8_u64m4_m(vbool16_t mask,vuint8mf2_t op1,size_t vl)
+{
+    return __riscv_vzext_vf8_u64m4_m(mask,op1,31);
+}
+
+
+vuint64m8_t test___riscv_vzext_vf8_u64m8_m(vbool8_t mask,vuint8m1_t op1,size_t vl)
+{
+    return __riscv_vzext_vf8_u64m8_m(mask,op1,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf8_m-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf8_m-3.c
new file mode 100644
index 00000000000..4e0be75405b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf8_m-3.c
@@ -0,0 +1,34 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint64m1_t test___riscv_vzext_vf8_u64m1_m(vbool64_t mask,vuint8mf8_t op1,size_t vl)
+{
+    return __riscv_vzext_vf8_u64m1_m(mask,op1,32);
+}
+
+
+vuint64m2_t test___riscv_vzext_vf8_u64m2_m(vbool32_t mask,vuint8mf4_t op1,size_t vl)
+{
+    return __riscv_vzext_vf8_u64m2_m(mask,op1,32);
+}
+
+
+vuint64m4_t test___riscv_vzext_vf8_u64m4_m(vbool16_t mask,vuint8mf2_t op1,size_t vl)
+{
+    return __riscv_vzext_vf8_u64m4_m(mask,op1,32);
+}
+
+
+vuint64m8_t test___riscv_vzext_vf8_u64m8_m(vbool8_t mask,vuint8m1_t op1,size_t vl)
+{
+    return __riscv_vzext_vf8_u64m8_m(mask,op1,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf8_mu-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf8_mu-1.c
new file mode 100644
index 00000000000..320371062f9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf8_mu-1.c
@@ -0,0 +1,34 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint64m1_t test___riscv_vzext_vf8_u64m1_mu(vbool64_t mask,vuint64m1_t merge,vuint8mf8_t op1,size_t vl)
+{
+    return __riscv_vzext_vf8_u64m1_mu(mask,merge,op1,vl);
+}
+
+
+vuint64m2_t test___riscv_vzext_vf8_u64m2_mu(vbool32_t mask,vuint64m2_t merge,vuint8mf4_t op1,size_t vl)
+{
+    return __riscv_vzext_vf8_u64m2_mu(mask,merge,op1,vl);
+}
+
+
+vuint64m4_t test___riscv_vzext_vf8_u64m4_mu(vbool16_t mask,vuint64m4_t merge,vuint8mf2_t op1,size_t vl)
+{
+    return __riscv_vzext_vf8_u64m4_mu(mask,merge,op1,vl);
+}
+
+
+vuint64m8_t test___riscv_vzext_vf8_u64m8_mu(vbool8_t mask,vuint64m8_t merge,vuint8m1_t op1,size_t vl)
+{
+    return __riscv_vzext_vf8_u64m8_mu(mask,merge,op1,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*mu\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*mu\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*mu\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*mu\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf8_mu-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf8_mu-2.c
new file mode 100644
index 00000000000..83af580e66f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf8_mu-2.c
@@ -0,0 +1,34 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint64m1_t test___riscv_vzext_vf8_u64m1_mu(vbool64_t mask,vuint64m1_t merge,vuint8mf8_t op1,size_t vl)
+{
+    return __riscv_vzext_vf8_u64m1_mu(mask,merge,op1,31);
+}
+
+
+vuint64m2_t test___riscv_vzext_vf8_u64m2_mu(vbool32_t mask,vuint64m2_t merge,vuint8mf4_t op1,size_t vl)
+{
+    return __riscv_vzext_vf8_u64m2_mu(mask,merge,op1,31);
+}
+
+
+vuint64m4_t test___riscv_vzext_vf8_u64m4_mu(vbool16_t mask,vuint64m4_t merge,vuint8mf2_t op1,size_t vl)
+{
+    return __riscv_vzext_vf8_u64m4_mu(mask,merge,op1,31);
+}
+
+
+vuint64m8_t test___riscv_vzext_vf8_u64m8_mu(vbool8_t mask,vuint64m8_t merge,vuint8m1_t op1,size_t vl)
+{
+    return __riscv_vzext_vf8_u64m8_mu(mask,merge,op1,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*mu\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*mu\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*mu\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*mu\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf8_mu-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf8_mu-3.c
new file mode 100644
index 00000000000..44a41981de3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf8_mu-3.c
@@ -0,0 +1,34 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint64m1_t test___riscv_vzext_vf8_u64m1_mu(vbool64_t mask,vuint64m1_t merge,vuint8mf8_t op1,size_t vl)
+{
+    return __riscv_vzext_vf8_u64m1_mu(mask,merge,op1,32);
+}
+
+
+vuint64m2_t test___riscv_vzext_vf8_u64m2_mu(vbool32_t mask,vuint64m2_t merge,vuint8mf4_t op1,size_t vl)
+{
+    return __riscv_vzext_vf8_u64m2_mu(mask,merge,op1,32);
+}
+
+
+vuint64m4_t test___riscv_vzext_vf8_u64m4_mu(vbool16_t mask,vuint64m4_t merge,vuint8mf2_t op1,size_t vl)
+{
+    return __riscv_vzext_vf8_u64m4_mu(mask,merge,op1,32);
+}
+
+
+vuint64m8_t test___riscv_vzext_vf8_u64m8_mu(vbool8_t mask,vuint64m8_t merge,vuint8m1_t op1,size_t vl)
+{
+    return __riscv_vzext_vf8_u64m8_mu(mask,merge,op1,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*mu\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*mu\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*mu\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*mu\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf8_tu-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf8_tu-1.c
new file mode 100644
index 00000000000..35bd01227cc
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf8_tu-1.c
@@ -0,0 +1,34 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint64m1_t test___riscv_vzext_vf8_u64m1_tu(vuint64m1_t merge,vuint8mf8_t op1,size_t vl)
+{
+    return __riscv_vzext_vf8_u64m1_tu(merge,op1,vl);
+}
+
+
+vuint64m2_t test___riscv_vzext_vf8_u64m2_tu(vuint64m2_t merge,vuint8mf4_t op1,size_t vl)
+{
+    return __riscv_vzext_vf8_u64m2_tu(merge,op1,vl);
+}
+
+
+vuint64m4_t test___riscv_vzext_vf8_u64m4_tu(vuint64m4_t merge,vuint8mf2_t op1,size_t vl)
+{
+    return __riscv_vzext_vf8_u64m4_tu(merge,op1,vl);
+}
+
+
+vuint64m8_t test___riscv_vzext_vf8_u64m8_tu(vuint64m8_t merge,vuint8m1_t op1,size_t vl)
+{
+    return __riscv_vzext_vf8_u64m8_tu(merge,op1,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf8_tu-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf8_tu-2.c
new file mode 100644
index 00000000000..7610fcdcb20
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf8_tu-2.c
@@ -0,0 +1,34 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint64m1_t test___riscv_vzext_vf8_u64m1_tu(vuint64m1_t merge,vuint8mf8_t op1,size_t vl)
+{
+    return __riscv_vzext_vf8_u64m1_tu(merge,op1,31);
+}
+
+
+vuint64m2_t test___riscv_vzext_vf8_u64m2_tu(vuint64m2_t merge,vuint8mf4_t op1,size_t vl)
+{
+    return __riscv_vzext_vf8_u64m2_tu(merge,op1,31);
+}
+
+
+vuint64m4_t test___riscv_vzext_vf8_u64m4_tu(vuint64m4_t merge,vuint8mf2_t op1,size_t vl)
+{
+    return __riscv_vzext_vf8_u64m4_tu(merge,op1,31);
+}
+
+
+vuint64m8_t test___riscv_vzext_vf8_u64m8_tu(vuint64m8_t merge,vuint8m1_t op1,size_t vl)
+{
+    return __riscv_vzext_vf8_u64m8_tu(merge,op1,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf8_tu-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf8_tu-3.c
new file mode 100644
index 00000000000..705f073874d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf8_tu-3.c
@@ -0,0 +1,34 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint64m1_t test___riscv_vzext_vf8_u64m1_tu(vuint64m1_t merge,vuint8mf8_t op1,size_t vl)
+{
+    return __riscv_vzext_vf8_u64m1_tu(merge,op1,32);
+}
+
+
+vuint64m2_t test___riscv_vzext_vf8_u64m2_tu(vuint64m2_t merge,vuint8mf4_t op1,size_t vl)
+{
+    return __riscv_vzext_vf8_u64m2_tu(merge,op1,32);
+}
+
+
+vuint64m4_t test___riscv_vzext_vf8_u64m4_tu(vuint64m4_t merge,vuint8mf2_t op1,size_t vl)
+{
+    return __riscv_vzext_vf8_u64m4_tu(merge,op1,32);
+}
+
+
+vuint64m8_t test___riscv_vzext_vf8_u64m8_tu(vuint64m8_t merge,vuint8m1_t op1,size_t vl)
+{
+    return __riscv_vzext_vf8_u64m8_tu(merge,op1,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf8_tum-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf8_tum-1.c
new file mode 100644
index 00000000000..553ea9443b6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf8_tum-1.c
@@ -0,0 +1,34 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint64m1_t test___riscv_vzext_vf8_u64m1_tum(vbool64_t mask,vuint64m1_t merge,vuint8mf8_t op1,size_t vl)
+{
+    return __riscv_vzext_vf8_u64m1_tum(mask,merge,op1,vl);
+}
+
+
+vuint64m2_t test___riscv_vzext_vf8_u64m2_tum(vbool32_t mask,vuint64m2_t merge,vuint8mf4_t op1,size_t vl)
+{
+    return __riscv_vzext_vf8_u64m2_tum(mask,merge,op1,vl);
+}
+
+
+vuint64m4_t test___riscv_vzext_vf8_u64m4_tum(vbool16_t mask,vuint64m4_t merge,vuint8mf2_t op1,size_t vl)
+{
+    return __riscv_vzext_vf8_u64m4_tum(mask,merge,op1,vl);
+}
+
+
+vuint64m8_t test___riscv_vzext_vf8_u64m8_tum(vbool8_t mask,vuint64m8_t merge,vuint8m1_t op1,size_t vl)
+{
+    return __riscv_vzext_vf8_u64m8_tum(mask,merge,op1,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf8_tum-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf8_tum-2.c
new file mode 100644
index 00000000000..8f47c1cb7a6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf8_tum-2.c
@@ -0,0 +1,34 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint64m1_t test___riscv_vzext_vf8_u64m1_tum(vbool64_t mask,vuint64m1_t merge,vuint8mf8_t op1,size_t vl)
+{
+    return __riscv_vzext_vf8_u64m1_tum(mask,merge,op1,31);
+}
+
+
+vuint64m2_t test___riscv_vzext_vf8_u64m2_tum(vbool32_t mask,vuint64m2_t merge,vuint8mf4_t op1,size_t vl)
+{
+    return __riscv_vzext_vf8_u64m2_tum(mask,merge,op1,31);
+}
+
+
+vuint64m4_t test___riscv_vzext_vf8_u64m4_tum(vbool16_t mask,vuint64m4_t merge,vuint8mf2_t op1,size_t vl)
+{
+    return __riscv_vzext_vf8_u64m4_tum(mask,merge,op1,31);
+}
+
+
+vuint64m8_t test___riscv_vzext_vf8_u64m8_tum(vbool8_t mask,vuint64m8_t merge,vuint8m1_t op1,size_t vl)
+{
+    return __riscv_vzext_vf8_u64m8_tum(mask,merge,op1,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf8_tum-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf8_tum-3.c
new file mode 100644
index 00000000000..2c0d0cb10da
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf8_tum-3.c
@@ -0,0 +1,34 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint64m1_t test___riscv_vzext_vf8_u64m1_tum(vbool64_t mask,vuint64m1_t merge,vuint8mf8_t op1,size_t vl)
+{
+    return __riscv_vzext_vf8_u64m1_tum(mask,merge,op1,32);
+}
+
+
+vuint64m2_t test___riscv_vzext_vf8_u64m2_tum(vbool32_t mask,vuint64m2_t merge,vuint8mf4_t op1,size_t vl)
+{
+    return __riscv_vzext_vf8_u64m2_tum(mask,merge,op1,32);
+}
+
+
+vuint64m4_t test___riscv_vzext_vf8_u64m4_tum(vbool16_t mask,vuint64m4_t merge,vuint8mf2_t op1,size_t vl)
+{
+    return __riscv_vzext_vf8_u64m4_tum(mask,merge,op1,32);
+}
+
+
+vuint64m8_t test___riscv_vzext_vf8_u64m8_tum(vbool8_t mask,vuint64m8_t merge,vuint8m1_t op1,size_t vl)
+{
+    return __riscv_vzext_vf8_u64m8_tum(mask,merge,op1,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf8_tumu-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf8_tumu-1.c
new file mode 100644
index 00000000000..e9341cf0573
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf8_tumu-1.c
@@ -0,0 +1,34 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint64m1_t test___riscv_vzext_vf8_u64m1_tumu(vbool64_t mask,vuint64m1_t merge,vuint8mf8_t op1,size_t vl)
+{
+    return __riscv_vzext_vf8_u64m1_tumu(mask,merge,op1,vl);
+}
+
+
+vuint64m2_t test___riscv_vzext_vf8_u64m2_tumu(vbool32_t mask,vuint64m2_t merge,vuint8mf4_t op1,size_t vl)
+{
+    return __riscv_vzext_vf8_u64m2_tumu(mask,merge,op1,vl);
+}
+
+
+vuint64m4_t test___riscv_vzext_vf8_u64m4_tumu(vbool16_t mask,vuint64m4_t merge,vuint8mf2_t op1,size_t vl)
+{
+    return __riscv_vzext_vf8_u64m4_tumu(mask,merge,op1,vl);
+}
+
+
+vuint64m8_t test___riscv_vzext_vf8_u64m8_tumu(vbool8_t mask,vuint64m8_t merge,vuint8m1_t op1,size_t vl)
+{
+    return __riscv_vzext_vf8_u64m8_tumu(mask,merge,op1,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*mu\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*mu\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*mu\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*mu\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf8_tumu-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf8_tumu-2.c
new file mode 100644
index 00000000000..ac5dd0f55c1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf8_tumu-2.c
@@ -0,0 +1,34 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint64m1_t test___riscv_vzext_vf8_u64m1_tumu(vbool64_t mask,vuint64m1_t merge,vuint8mf8_t op1,size_t vl)
+{
+    return __riscv_vzext_vf8_u64m1_tumu(mask,merge,op1,31);
+}
+
+
+vuint64m2_t test___riscv_vzext_vf8_u64m2_tumu(vbool32_t mask,vuint64m2_t merge,vuint8mf4_t op1,size_t vl)
+{
+    return __riscv_vzext_vf8_u64m2_tumu(mask,merge,op1,31);
+}
+
+
+vuint64m4_t test___riscv_vzext_vf8_u64m4_tumu(vbool16_t mask,vuint64m4_t merge,vuint8mf2_t op1,size_t vl)
+{
+    return __riscv_vzext_vf8_u64m4_tumu(mask,merge,op1,31);
+}
+
+
+vuint64m8_t test___riscv_vzext_vf8_u64m8_tumu(vbool8_t mask,vuint64m8_t merge,vuint8m1_t op1,size_t vl)
+{
+    return __riscv_vzext_vf8_u64m8_tumu(mask,merge,op1,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*mu\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*mu\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*mu\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*mu\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf8_tumu-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf8_tumu-3.c
new file mode 100644
index 00000000000..fa6133ec9c4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf8_tumu-3.c
@@ -0,0 +1,34 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint64m1_t test___riscv_vzext_vf8_u64m1_tumu(vbool64_t mask,vuint64m1_t merge,vuint8mf8_t op1,size_t vl)
+{
+    return __riscv_vzext_vf8_u64m1_tumu(mask,merge,op1,32);
+}
+
+
+vuint64m2_t test___riscv_vzext_vf8_u64m2_tumu(vbool32_t mask,vuint64m2_t merge,vuint8mf4_t op1,size_t vl)
+{
+    return __riscv_vzext_vf8_u64m2_tumu(mask,merge,op1,32);
+}
+
+
+vuint64m4_t test___riscv_vzext_vf8_u64m4_tumu(vbool16_t mask,vuint64m4_t merge,vuint8mf2_t op1,size_t vl)
+{
+    return __riscv_vzext_vf8_u64m4_tumu(mask,merge,op1,32);
+}
+
+
+vuint64m8_t test___riscv_vzext_vf8_u64m8_tumu(vbool8_t mask,vuint64m8_t merge,vuint8m1_t op1,size_t vl)
+{
+    return __riscv_vzext_vf8_u64m8_tumu(mask,merge,op1,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*mu\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*mu\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*mu\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*mu\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */