RISC-V: Add vdivu.vx C++ API tests

Message ID 20230203081138.229977-1-juzhe.zhong@rivai.ai
State Committed
Commit 8189380d868d902120c91d166c3517fa79ed28f7
Headers
Series RISC-V: Add vdivu.vx C++ API tests |

Commit Message

钟居哲 Feb. 3, 2023, 8:11 a.m. UTC
  From: Ju-Zhe Zhong <juzhe.zhong@rivai.ai>

gcc/testsuite/ChangeLog:

        * g++.target/riscv/rvv/base/vdivu_vx_mu_rv32-1.C: New test.
        * g++.target/riscv/rvv/base/vdivu_vx_mu_rv32-2.C: New test.
        * g++.target/riscv/rvv/base/vdivu_vx_mu_rv32-3.C: New test.
        * g++.target/riscv/rvv/base/vdivu_vx_mu_rv64-1.C: New test.
        * g++.target/riscv/rvv/base/vdivu_vx_mu_rv64-2.C: New test.
        * g++.target/riscv/rvv/base/vdivu_vx_mu_rv64-3.C: New test.
        * g++.target/riscv/rvv/base/vdivu_vx_rv32-1.C: New test.
        * g++.target/riscv/rvv/base/vdivu_vx_rv32-2.C: New test.
        * g++.target/riscv/rvv/base/vdivu_vx_rv32-3.C: New test.
        * g++.target/riscv/rvv/base/vdivu_vx_rv64-1.C: New test.
        * g++.target/riscv/rvv/base/vdivu_vx_rv64-2.C: New test.
        * g++.target/riscv/rvv/base/vdivu_vx_rv64-3.C: New test.
        * g++.target/riscv/rvv/base/vdivu_vx_tu_rv32-1.C: New test.
        * g++.target/riscv/rvv/base/vdivu_vx_tu_rv32-2.C: New test.
        * g++.target/riscv/rvv/base/vdivu_vx_tu_rv32-3.C: New test.
        * g++.target/riscv/rvv/base/vdivu_vx_tu_rv64-1.C: New test.
        * g++.target/riscv/rvv/base/vdivu_vx_tu_rv64-2.C: New test.
        * g++.target/riscv/rvv/base/vdivu_vx_tu_rv64-3.C: New test.
        * g++.target/riscv/rvv/base/vdivu_vx_tum_rv32-1.C: New test.
        * g++.target/riscv/rvv/base/vdivu_vx_tum_rv32-2.C: New test.
        * g++.target/riscv/rvv/base/vdivu_vx_tum_rv32-3.C: New test.
        * g++.target/riscv/rvv/base/vdivu_vx_tum_rv64-1.C: New test.
        * g++.target/riscv/rvv/base/vdivu_vx_tum_rv64-2.C: New test.
        * g++.target/riscv/rvv/base/vdivu_vx_tum_rv64-3.C: New test.
        * g++.target/riscv/rvv/base/vdivu_vx_tumu_rv32-1.C: New test.
        * g++.target/riscv/rvv/base/vdivu_vx_tumu_rv32-2.C: New test.
        * g++.target/riscv/rvv/base/vdivu_vx_tumu_rv32-3.C: New test.
        * g++.target/riscv/rvv/base/vdivu_vx_tumu_rv64-1.C: New test.
        * g++.target/riscv/rvv/base/vdivu_vx_tumu_rv64-2.C: New test.
        * g++.target/riscv/rvv/base/vdivu_vx_tumu_rv64-3.C: New test.

---
 .../riscv/rvv/base/vdivu_vx_mu_rv32-1.C       | 157 +++++++++
 .../riscv/rvv/base/vdivu_vx_mu_rv32-2.C       | 157 +++++++++
 .../riscv/rvv/base/vdivu_vx_mu_rv32-3.C       | 157 +++++++++
 .../riscv/rvv/base/vdivu_vx_mu_rv64-1.C       | 160 +++++++++
 .../riscv/rvv/base/vdivu_vx_mu_rv64-2.C       | 160 +++++++++
 .../riscv/rvv/base/vdivu_vx_mu_rv64-3.C       | 160 +++++++++
 .../riscv/rvv/base/vdivu_vx_rv32-1.C          | 308 +++++++++++++++++
 .../riscv/rvv/base/vdivu_vx_rv32-2.C          | 308 +++++++++++++++++
 .../riscv/rvv/base/vdivu_vx_rv32-3.C          | 308 +++++++++++++++++
 .../riscv/rvv/base/vdivu_vx_rv64-1.C          | 314 ++++++++++++++++++
 .../riscv/rvv/base/vdivu_vx_rv64-2.C          | 314 ++++++++++++++++++
 .../riscv/rvv/base/vdivu_vx_rv64-3.C          | 314 ++++++++++++++++++
 .../riscv/rvv/base/vdivu_vx_tu_rv32-1.C       | 157 +++++++++
 .../riscv/rvv/base/vdivu_vx_tu_rv32-2.C       | 157 +++++++++
 .../riscv/rvv/base/vdivu_vx_tu_rv32-3.C       | 157 +++++++++
 .../riscv/rvv/base/vdivu_vx_tu_rv64-1.C       | 160 +++++++++
 .../riscv/rvv/base/vdivu_vx_tu_rv64-2.C       | 160 +++++++++
 .../riscv/rvv/base/vdivu_vx_tu_rv64-3.C       | 160 +++++++++
 .../riscv/rvv/base/vdivu_vx_tum_rv32-1.C      | 157 +++++++++
 .../riscv/rvv/base/vdivu_vx_tum_rv32-2.C      | 157 +++++++++
 .../riscv/rvv/base/vdivu_vx_tum_rv32-3.C      | 157 +++++++++
 .../riscv/rvv/base/vdivu_vx_tum_rv64-1.C      | 160 +++++++++
 .../riscv/rvv/base/vdivu_vx_tum_rv64-2.C      | 160 +++++++++
 .../riscv/rvv/base/vdivu_vx_tum_rv64-3.C      | 160 +++++++++
 .../riscv/rvv/base/vdivu_vx_tumu_rv32-1.C     | 157 +++++++++
 .../riscv/rvv/base/vdivu_vx_tumu_rv32-2.C     | 157 +++++++++
 .../riscv/rvv/base/vdivu_vx_tumu_rv32-3.C     | 157 +++++++++
 .../riscv/rvv/base/vdivu_vx_tumu_rv64-1.C     | 160 +++++++++
 .../riscv/rvv/base/vdivu_vx_tumu_rv64-2.C     | 160 +++++++++
 .../riscv/rvv/base/vdivu_vx_tumu_rv64-3.C     | 160 +++++++++
 30 files changed, 5670 insertions(+)
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vdivu_vx_mu_rv32-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vdivu_vx_mu_rv32-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vdivu_vx_mu_rv32-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vdivu_vx_mu_rv64-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vdivu_vx_mu_rv64-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vdivu_vx_mu_rv64-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vdivu_vx_rv32-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vdivu_vx_rv32-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vdivu_vx_rv32-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vdivu_vx_rv64-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vdivu_vx_rv64-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vdivu_vx_rv64-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vdivu_vx_tu_rv32-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vdivu_vx_tu_rv32-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vdivu_vx_tu_rv32-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vdivu_vx_tu_rv64-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vdivu_vx_tu_rv64-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vdivu_vx_tu_rv64-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vdivu_vx_tum_rv32-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vdivu_vx_tum_rv32-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vdivu_vx_tum_rv32-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vdivu_vx_tum_rv64-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vdivu_vx_tum_rv64-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vdivu_vx_tum_rv64-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vdivu_vx_tumu_rv32-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vdivu_vx_tumu_rv32-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vdivu_vx_tumu_rv32-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vdivu_vx_tumu_rv64-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vdivu_vx_tumu_rv64-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vdivu_vx_tumu_rv64-3.C
  

Patch

diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vdivu_vx_mu_rv32-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vdivu_vx_mu_rv32-1.C
new file mode 100644
index 00000000000..77ab19ed232
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vdivu_vx_mu_rv32-1.C
@@ -0,0 +1,157 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint8mf8_t test___riscv_vdivu_mu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vdivu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint8mf4_t test___riscv_vdivu_mu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vdivu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint8mf2_t test___riscv_vdivu_mu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vdivu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint8m1_t test___riscv_vdivu_mu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vdivu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint8m2_t test___riscv_vdivu_mu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vdivu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint8m4_t test___riscv_vdivu_mu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vdivu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint8m8_t test___riscv_vdivu_mu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vdivu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint16mf4_t test___riscv_vdivu_mu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vdivu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint16mf2_t test___riscv_vdivu_mu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vdivu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m1_t test___riscv_vdivu_mu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vdivu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m2_t test___riscv_vdivu_mu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vdivu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m4_t test___riscv_vdivu_mu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vdivu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m8_t test___riscv_vdivu_mu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vdivu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint32mf2_t test___riscv_vdivu_mu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vdivu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m1_t test___riscv_vdivu_mu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vdivu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m2_t test___riscv_vdivu_mu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vdivu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m4_t test___riscv_vdivu_mu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vdivu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m8_t test___riscv_vdivu_mu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vdivu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m1_t test___riscv_vdivu_mu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vdivu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m2_t test___riscv_vdivu_mu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vdivu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m4_t test___riscv_vdivu_mu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vdivu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m8_t test___riscv_vdivu_mu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vdivu_mu(mask,merge,op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*mu\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vdivu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 4 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vdivu_vx_mu_rv32-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vdivu_vx_mu_rv32-2.C
new file mode 100644
index 00000000000..6e6103f5c5e
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vdivu_vx_mu_rv32-2.C
@@ -0,0 +1,157 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint8mf8_t test___riscv_vdivu_mu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vdivu_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint8mf4_t test___riscv_vdivu_mu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vdivu_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint8mf2_t test___riscv_vdivu_mu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vdivu_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint8m1_t test___riscv_vdivu_mu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vdivu_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint8m2_t test___riscv_vdivu_mu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vdivu_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint8m4_t test___riscv_vdivu_mu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vdivu_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint8m8_t test___riscv_vdivu_mu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vdivu_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint16mf4_t test___riscv_vdivu_mu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vdivu_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint16mf2_t test___riscv_vdivu_mu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vdivu_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint16m1_t test___riscv_vdivu_mu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vdivu_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint16m2_t test___riscv_vdivu_mu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vdivu_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint16m4_t test___riscv_vdivu_mu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vdivu_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint16m8_t test___riscv_vdivu_mu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vdivu_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint32mf2_t test___riscv_vdivu_mu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vdivu_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint32m1_t test___riscv_vdivu_mu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vdivu_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint32m2_t test___riscv_vdivu_mu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vdivu_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint32m4_t test___riscv_vdivu_mu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vdivu_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint32m8_t test___riscv_vdivu_mu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vdivu_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint64m1_t test___riscv_vdivu_mu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vdivu_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint64m2_t test___riscv_vdivu_mu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vdivu_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint64m4_t test___riscv_vdivu_mu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vdivu_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint64m8_t test___riscv_vdivu_mu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vdivu_mu(mask,merge,op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*mu\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*mu\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*mu\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*mu\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*mu\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*mu\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*mu\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*mu\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*mu\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*mu\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*mu\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*mu\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vdivu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 4 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vdivu_vx_mu_rv32-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vdivu_vx_mu_rv32-3.C
new file mode 100644
index 00000000000..c1e7e3dfcff
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vdivu_vx_mu_rv32-3.C
@@ -0,0 +1,157 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint8mf8_t test___riscv_vdivu_mu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vdivu_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint8mf4_t test___riscv_vdivu_mu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vdivu_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint8mf2_t test___riscv_vdivu_mu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vdivu_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint8m1_t test___riscv_vdivu_mu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vdivu_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint8m2_t test___riscv_vdivu_mu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vdivu_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint8m4_t test___riscv_vdivu_mu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vdivu_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint8m8_t test___riscv_vdivu_mu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vdivu_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint16mf4_t test___riscv_vdivu_mu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vdivu_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint16mf2_t test___riscv_vdivu_mu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vdivu_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint16m1_t test___riscv_vdivu_mu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vdivu_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint16m2_t test___riscv_vdivu_mu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vdivu_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint16m4_t test___riscv_vdivu_mu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vdivu_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint16m8_t test___riscv_vdivu_mu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vdivu_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint32mf2_t test___riscv_vdivu_mu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vdivu_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint32m1_t test___riscv_vdivu_mu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vdivu_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint32m2_t test___riscv_vdivu_mu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vdivu_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint32m4_t test___riscv_vdivu_mu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vdivu_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint32m8_t test___riscv_vdivu_mu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vdivu_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint64m1_t test___riscv_vdivu_mu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vdivu_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint64m2_t test___riscv_vdivu_mu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vdivu_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint64m4_t test___riscv_vdivu_mu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vdivu_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint64m8_t test___riscv_vdivu_mu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vdivu_mu(mask,merge,op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*mu\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vdivu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 4 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vdivu_vx_mu_rv64-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vdivu_vx_mu_rv64-1.C
new file mode 100644
index 00000000000..7500e52c876
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vdivu_vx_mu_rv64-1.C
@@ -0,0 +1,160 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint8mf8_t test___riscv_vdivu_mu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vdivu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint8mf4_t test___riscv_vdivu_mu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vdivu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint8mf2_t test___riscv_vdivu_mu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vdivu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint8m1_t test___riscv_vdivu_mu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vdivu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint8m2_t test___riscv_vdivu_mu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vdivu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint8m4_t test___riscv_vdivu_mu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vdivu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint8m8_t test___riscv_vdivu_mu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vdivu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint16mf4_t test___riscv_vdivu_mu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vdivu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint16mf2_t test___riscv_vdivu_mu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vdivu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m1_t test___riscv_vdivu_mu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vdivu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m2_t test___riscv_vdivu_mu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vdivu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m4_t test___riscv_vdivu_mu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vdivu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m8_t test___riscv_vdivu_mu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vdivu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint32mf2_t test___riscv_vdivu_mu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vdivu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m1_t test___riscv_vdivu_mu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vdivu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m2_t test___riscv_vdivu_mu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vdivu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m4_t test___riscv_vdivu_mu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vdivu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m8_t test___riscv_vdivu_mu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vdivu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m1_t test___riscv_vdivu_mu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vdivu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m2_t test___riscv_vdivu_mu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vdivu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m4_t test___riscv_vdivu_mu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vdivu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m8_t test___riscv_vdivu_mu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vdivu_mu(mask,merge,op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*mu\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*mu\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*mu\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*mu\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*mu\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vdivu_vx_mu_rv64-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vdivu_vx_mu_rv64-2.C
new file mode 100644
index 00000000000..fef29c71f95
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vdivu_vx_mu_rv64-2.C
@@ -0,0 +1,160 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint8mf8_t test___riscv_vdivu_mu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vdivu_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint8mf4_t test___riscv_vdivu_mu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vdivu_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint8mf2_t test___riscv_vdivu_mu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vdivu_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint8m1_t test___riscv_vdivu_mu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vdivu_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint8m2_t test___riscv_vdivu_mu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vdivu_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint8m4_t test___riscv_vdivu_mu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vdivu_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint8m8_t test___riscv_vdivu_mu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vdivu_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint16mf4_t test___riscv_vdivu_mu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vdivu_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint16mf2_t test___riscv_vdivu_mu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vdivu_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint16m1_t test___riscv_vdivu_mu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vdivu_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint16m2_t test___riscv_vdivu_mu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vdivu_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint16m4_t test___riscv_vdivu_mu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vdivu_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint16m8_t test___riscv_vdivu_mu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vdivu_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint32mf2_t test___riscv_vdivu_mu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vdivu_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint32m1_t test___riscv_vdivu_mu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vdivu_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint32m2_t test___riscv_vdivu_mu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vdivu_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint32m4_t test___riscv_vdivu_mu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vdivu_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint32m8_t test___riscv_vdivu_mu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vdivu_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint64m1_t test___riscv_vdivu_mu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vdivu_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint64m2_t test___riscv_vdivu_mu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vdivu_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint64m4_t test___riscv_vdivu_mu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vdivu_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint64m8_t test___riscv_vdivu_mu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vdivu_mu(mask,merge,op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*mu\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*mu\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*mu\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*mu\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*mu\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*mu\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*mu\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*mu\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*mu\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*mu\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*mu\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*mu\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*mu\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*mu\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*mu\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*mu\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vdivu_vx_mu_rv64-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vdivu_vx_mu_rv64-3.C
new file mode 100644
index 00000000000..95d9a37fc23
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vdivu_vx_mu_rv64-3.C
@@ -0,0 +1,160 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint8mf8_t test___riscv_vdivu_mu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vdivu_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint8mf4_t test___riscv_vdivu_mu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vdivu_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint8mf2_t test___riscv_vdivu_mu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vdivu_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint8m1_t test___riscv_vdivu_mu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vdivu_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint8m2_t test___riscv_vdivu_mu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vdivu_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint8m4_t test___riscv_vdivu_mu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vdivu_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint8m8_t test___riscv_vdivu_mu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vdivu_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint16mf4_t test___riscv_vdivu_mu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vdivu_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint16mf2_t test___riscv_vdivu_mu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vdivu_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint16m1_t test___riscv_vdivu_mu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vdivu_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint16m2_t test___riscv_vdivu_mu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vdivu_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint16m4_t test___riscv_vdivu_mu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vdivu_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint16m8_t test___riscv_vdivu_mu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vdivu_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint32mf2_t test___riscv_vdivu_mu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vdivu_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint32m1_t test___riscv_vdivu_mu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vdivu_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint32m2_t test___riscv_vdivu_mu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vdivu_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint32m4_t test___riscv_vdivu_mu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vdivu_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint32m8_t test___riscv_vdivu_mu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vdivu_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint64m1_t test___riscv_vdivu_mu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vdivu_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint64m2_t test___riscv_vdivu_mu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vdivu_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint64m4_t test___riscv_vdivu_mu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vdivu_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint64m8_t test___riscv_vdivu_mu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vdivu_mu(mask,merge,op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*mu\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*mu\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*mu\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*mu\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*mu\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vdivu_vx_rv32-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vdivu_vx_rv32-1.C
new file mode 100644
index 00000000000..02ba63b4fe5
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vdivu_vx_rv32-1.C
@@ -0,0 +1,308 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint8mf8_t test___riscv_vdivu(vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vdivu(op1,op2,vl);
+}
+
+
+vuint8mf4_t test___riscv_vdivu(vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vdivu(op1,op2,vl);
+}
+
+
+vuint8mf2_t test___riscv_vdivu(vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vdivu(op1,op2,vl);
+}
+
+
+vuint8m1_t test___riscv_vdivu(vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vdivu(op1,op2,vl);
+}
+
+
+vuint8m2_t test___riscv_vdivu(vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vdivu(op1,op2,vl);
+}
+
+
+vuint8m4_t test___riscv_vdivu(vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vdivu(op1,op2,vl);
+}
+
+
+vuint8m8_t test___riscv_vdivu(vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vdivu(op1,op2,vl);
+}
+
+
+vuint16mf4_t test___riscv_vdivu(vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vdivu(op1,op2,vl);
+}
+
+
+vuint16mf2_t test___riscv_vdivu(vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vdivu(op1,op2,vl);
+}
+
+
+vuint16m1_t test___riscv_vdivu(vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vdivu(op1,op2,vl);
+}
+
+
+vuint16m2_t test___riscv_vdivu(vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vdivu(op1,op2,vl);
+}
+
+
+vuint16m4_t test___riscv_vdivu(vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vdivu(op1,op2,vl);
+}
+
+
+vuint16m8_t test___riscv_vdivu(vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vdivu(op1,op2,vl);
+}
+
+
+vuint32mf2_t test___riscv_vdivu(vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vdivu(op1,op2,vl);
+}
+
+
+vuint32m1_t test___riscv_vdivu(vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vdivu(op1,op2,vl);
+}
+
+
+vuint32m2_t test___riscv_vdivu(vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vdivu(op1,op2,vl);
+}
+
+
+vuint32m4_t test___riscv_vdivu(vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vdivu(op1,op2,vl);
+}
+
+
+vuint32m8_t test___riscv_vdivu(vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vdivu(op1,op2,vl);
+}
+
+
+vuint64m1_t test___riscv_vdivu(vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vdivu(op1,op2,vl);
+}
+
+
+vuint64m2_t test___riscv_vdivu(vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vdivu(op1,op2,vl);
+}
+
+
+vuint64m4_t test___riscv_vdivu(vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vdivu(op1,op2,vl);
+}
+
+
+vuint64m8_t test___riscv_vdivu(vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vdivu(op1,op2,vl);
+}
+
+
+vuint8mf8_t test___riscv_vdivu(vbool64_t mask,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vdivu(mask,op1,op2,vl);
+}
+
+
+vuint8mf4_t test___riscv_vdivu(vbool32_t mask,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vdivu(mask,op1,op2,vl);
+}
+
+
+vuint8mf2_t test___riscv_vdivu(vbool16_t mask,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vdivu(mask,op1,op2,vl);
+}
+
+
+vuint8m1_t test___riscv_vdivu(vbool8_t mask,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vdivu(mask,op1,op2,vl);
+}
+
+
+vuint8m2_t test___riscv_vdivu(vbool4_t mask,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vdivu(mask,op1,op2,vl);
+}
+
+
+vuint8m4_t test___riscv_vdivu(vbool2_t mask,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vdivu(mask,op1,op2,vl);
+}
+
+
+vuint8m8_t test___riscv_vdivu(vbool1_t mask,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vdivu(mask,op1,op2,vl);
+}
+
+
+vuint16mf4_t test___riscv_vdivu(vbool64_t mask,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vdivu(mask,op1,op2,vl);
+}
+
+
+vuint16mf2_t test___riscv_vdivu(vbool32_t mask,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vdivu(mask,op1,op2,vl);
+}
+
+
+vuint16m1_t test___riscv_vdivu(vbool16_t mask,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vdivu(mask,op1,op2,vl);
+}
+
+
+vuint16m2_t test___riscv_vdivu(vbool8_t mask,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vdivu(mask,op1,op2,vl);
+}
+
+
+vuint16m4_t test___riscv_vdivu(vbool4_t mask,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vdivu(mask,op1,op2,vl);
+}
+
+
+vuint16m8_t test___riscv_vdivu(vbool2_t mask,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vdivu(mask,op1,op2,vl);
+}
+
+
+vuint32mf2_t test___riscv_vdivu(vbool64_t mask,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vdivu(mask,op1,op2,vl);
+}
+
+
+vuint32m1_t test___riscv_vdivu(vbool32_t mask,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vdivu(mask,op1,op2,vl);
+}
+
+
+vuint32m2_t test___riscv_vdivu(vbool16_t mask,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vdivu(mask,op1,op2,vl);
+}
+
+
+vuint32m4_t test___riscv_vdivu(vbool8_t mask,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vdivu(mask,op1,op2,vl);
+}
+
+
+vuint32m8_t test___riscv_vdivu(vbool4_t mask,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vdivu(mask,op1,op2,vl);
+}
+
+
+vuint64m1_t test___riscv_vdivu(vbool64_t mask,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vdivu(mask,op1,op2,vl);
+}
+
+
+vuint64m2_t test___riscv_vdivu(vbool32_t mask,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vdivu(mask,op1,op2,vl);
+}
+
+
+vuint64m4_t test___riscv_vdivu(vbool16_t mask,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vdivu(mask,op1,op2,vl);
+}
+
+
+vuint64m8_t test___riscv_vdivu(vbool8_t mask,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vdivu(mask,op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vdivu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 4 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vdivu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 4 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vdivu_vx_rv32-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vdivu_vx_rv32-2.C
new file mode 100644
index 00000000000..272b246e56b
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vdivu_vx_rv32-2.C
@@ -0,0 +1,308 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint8mf8_t test___riscv_vdivu(vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vdivu(op1,op2,31);
+}
+
+
+vuint8mf4_t test___riscv_vdivu(vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vdivu(op1,op2,31);
+}
+
+
+vuint8mf2_t test___riscv_vdivu(vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vdivu(op1,op2,31);
+}
+
+
+vuint8m1_t test___riscv_vdivu(vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vdivu(op1,op2,31);
+}
+
+
+vuint8m2_t test___riscv_vdivu(vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vdivu(op1,op2,31);
+}
+
+
+vuint8m4_t test___riscv_vdivu(vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vdivu(op1,op2,31);
+}
+
+
+vuint8m8_t test___riscv_vdivu(vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vdivu(op1,op2,31);
+}
+
+
+vuint16mf4_t test___riscv_vdivu(vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vdivu(op1,op2,31);
+}
+
+
+vuint16mf2_t test___riscv_vdivu(vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vdivu(op1,op2,31);
+}
+
+
+vuint16m1_t test___riscv_vdivu(vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vdivu(op1,op2,31);
+}
+
+
+vuint16m2_t test___riscv_vdivu(vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vdivu(op1,op2,31);
+}
+
+
+vuint16m4_t test___riscv_vdivu(vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vdivu(op1,op2,31);
+}
+
+
+vuint16m8_t test___riscv_vdivu(vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vdivu(op1,op2,31);
+}
+
+
+vuint32mf2_t test___riscv_vdivu(vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vdivu(op1,op2,31);
+}
+
+
+vuint32m1_t test___riscv_vdivu(vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vdivu(op1,op2,31);
+}
+
+
+vuint32m2_t test___riscv_vdivu(vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vdivu(op1,op2,31);
+}
+
+
+vuint32m4_t test___riscv_vdivu(vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vdivu(op1,op2,31);
+}
+
+
+vuint32m8_t test___riscv_vdivu(vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vdivu(op1,op2,31);
+}
+
+
+vuint64m1_t test___riscv_vdivu(vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vdivu(op1,op2,31);
+}
+
+
+vuint64m2_t test___riscv_vdivu(vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vdivu(op1,op2,31);
+}
+
+
+vuint64m4_t test___riscv_vdivu(vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vdivu(op1,op2,31);
+}
+
+
+vuint64m8_t test___riscv_vdivu(vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vdivu(op1,op2,31);
+}
+
+
+vuint8mf8_t test___riscv_vdivu(vbool64_t mask,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vdivu(mask,op1,op2,31);
+}
+
+
+vuint8mf4_t test___riscv_vdivu(vbool32_t mask,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vdivu(mask,op1,op2,31);
+}
+
+
+vuint8mf2_t test___riscv_vdivu(vbool16_t mask,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vdivu(mask,op1,op2,31);
+}
+
+
+vuint8m1_t test___riscv_vdivu(vbool8_t mask,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vdivu(mask,op1,op2,31);
+}
+
+
+vuint8m2_t test___riscv_vdivu(vbool4_t mask,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vdivu(mask,op1,op2,31);
+}
+
+
+vuint8m4_t test___riscv_vdivu(vbool2_t mask,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vdivu(mask,op1,op2,31);
+}
+
+
+vuint8m8_t test___riscv_vdivu(vbool1_t mask,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vdivu(mask,op1,op2,31);
+}
+
+
+vuint16mf4_t test___riscv_vdivu(vbool64_t mask,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vdivu(mask,op1,op2,31);
+}
+
+
+vuint16mf2_t test___riscv_vdivu(vbool32_t mask,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vdivu(mask,op1,op2,31);
+}
+
+
+vuint16m1_t test___riscv_vdivu(vbool16_t mask,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vdivu(mask,op1,op2,31);
+}
+
+
+vuint16m2_t test___riscv_vdivu(vbool8_t mask,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vdivu(mask,op1,op2,31);
+}
+
+
+vuint16m4_t test___riscv_vdivu(vbool4_t mask,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vdivu(mask,op1,op2,31);
+}
+
+
+vuint16m8_t test___riscv_vdivu(vbool2_t mask,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vdivu(mask,op1,op2,31);
+}
+
+
+vuint32mf2_t test___riscv_vdivu(vbool64_t mask,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vdivu(mask,op1,op2,31);
+}
+
+
+vuint32m1_t test___riscv_vdivu(vbool32_t mask,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vdivu(mask,op1,op2,31);
+}
+
+
+vuint32m2_t test___riscv_vdivu(vbool16_t mask,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vdivu(mask,op1,op2,31);
+}
+
+
+vuint32m4_t test___riscv_vdivu(vbool8_t mask,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vdivu(mask,op1,op2,31);
+}
+
+
+vuint32m8_t test___riscv_vdivu(vbool4_t mask,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vdivu(mask,op1,op2,31);
+}
+
+
+vuint64m1_t test___riscv_vdivu(vbool64_t mask,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vdivu(mask,op1,op2,31);
+}
+
+
+vuint64m2_t test___riscv_vdivu(vbool32_t mask,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vdivu(mask,op1,op2,31);
+}
+
+
+vuint64m4_t test___riscv_vdivu(vbool16_t mask,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vdivu(mask,op1,op2,31);
+}
+
+
+vuint64m8_t test___riscv_vdivu(vbool8_t mask,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vdivu(mask,op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vdivu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 4 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vdivu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 4 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vdivu_vx_rv32-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vdivu_vx_rv32-3.C
new file mode 100644
index 00000000000..4fc11caa7fd
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vdivu_vx_rv32-3.C
@@ -0,0 +1,308 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint8mf8_t test___riscv_vdivu(vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vdivu(op1,op2,32);
+}
+
+
+vuint8mf4_t test___riscv_vdivu(vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vdivu(op1,op2,32);
+}
+
+
+vuint8mf2_t test___riscv_vdivu(vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vdivu(op1,op2,32);
+}
+
+
+vuint8m1_t test___riscv_vdivu(vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vdivu(op1,op2,32);
+}
+
+
+vuint8m2_t test___riscv_vdivu(vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vdivu(op1,op2,32);
+}
+
+
+vuint8m4_t test___riscv_vdivu(vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vdivu(op1,op2,32);
+}
+
+
+vuint8m8_t test___riscv_vdivu(vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vdivu(op1,op2,32);
+}
+
+
+vuint16mf4_t test___riscv_vdivu(vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vdivu(op1,op2,32);
+}
+
+
+vuint16mf2_t test___riscv_vdivu(vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vdivu(op1,op2,32);
+}
+
+
+vuint16m1_t test___riscv_vdivu(vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vdivu(op1,op2,32);
+}
+
+
+vuint16m2_t test___riscv_vdivu(vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vdivu(op1,op2,32);
+}
+
+
+vuint16m4_t test___riscv_vdivu(vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vdivu(op1,op2,32);
+}
+
+
+vuint16m8_t test___riscv_vdivu(vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vdivu(op1,op2,32);
+}
+
+
+vuint32mf2_t test___riscv_vdivu(vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vdivu(op1,op2,32);
+}
+
+
+vuint32m1_t test___riscv_vdivu(vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vdivu(op1,op2,32);
+}
+
+
+vuint32m2_t test___riscv_vdivu(vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vdivu(op1,op2,32);
+}
+
+
+vuint32m4_t test___riscv_vdivu(vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vdivu(op1,op2,32);
+}
+
+
+vuint32m8_t test___riscv_vdivu(vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vdivu(op1,op2,32);
+}
+
+
+vuint64m1_t test___riscv_vdivu(vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vdivu(op1,op2,32);
+}
+
+
+vuint64m2_t test___riscv_vdivu(vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vdivu(op1,op2,32);
+}
+
+
+vuint64m4_t test___riscv_vdivu(vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vdivu(op1,op2,32);
+}
+
+
+vuint64m8_t test___riscv_vdivu(vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vdivu(op1,op2,32);
+}
+
+
+vuint8mf8_t test___riscv_vdivu(vbool64_t mask,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vdivu(mask,op1,op2,32);
+}
+
+
+vuint8mf4_t test___riscv_vdivu(vbool32_t mask,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vdivu(mask,op1,op2,32);
+}
+
+
+vuint8mf2_t test___riscv_vdivu(vbool16_t mask,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vdivu(mask,op1,op2,32);
+}
+
+
+vuint8m1_t test___riscv_vdivu(vbool8_t mask,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vdivu(mask,op1,op2,32);
+}
+
+
+vuint8m2_t test___riscv_vdivu(vbool4_t mask,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vdivu(mask,op1,op2,32);
+}
+
+
+vuint8m4_t test___riscv_vdivu(vbool2_t mask,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vdivu(mask,op1,op2,32);
+}
+
+
+vuint8m8_t test___riscv_vdivu(vbool1_t mask,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vdivu(mask,op1,op2,32);
+}
+
+
+vuint16mf4_t test___riscv_vdivu(vbool64_t mask,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vdivu(mask,op1,op2,32);
+}
+
+
+vuint16mf2_t test___riscv_vdivu(vbool32_t mask,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vdivu(mask,op1,op2,32);
+}
+
+
+vuint16m1_t test___riscv_vdivu(vbool16_t mask,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vdivu(mask,op1,op2,32);
+}
+
+
+vuint16m2_t test___riscv_vdivu(vbool8_t mask,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vdivu(mask,op1,op2,32);
+}
+
+
+vuint16m4_t test___riscv_vdivu(vbool4_t mask,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vdivu(mask,op1,op2,32);
+}
+
+
+vuint16m8_t test___riscv_vdivu(vbool2_t mask,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vdivu(mask,op1,op2,32);
+}
+
+
+vuint32mf2_t test___riscv_vdivu(vbool64_t mask,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vdivu(mask,op1,op2,32);
+}
+
+
+vuint32m1_t test___riscv_vdivu(vbool32_t mask,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vdivu(mask,op1,op2,32);
+}
+
+
+vuint32m2_t test___riscv_vdivu(vbool16_t mask,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vdivu(mask,op1,op2,32);
+}
+
+
+vuint32m4_t test___riscv_vdivu(vbool8_t mask,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vdivu(mask,op1,op2,32);
+}
+
+
+vuint32m8_t test___riscv_vdivu(vbool4_t mask,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vdivu(mask,op1,op2,32);
+}
+
+
+vuint64m1_t test___riscv_vdivu(vbool64_t mask,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vdivu(mask,op1,op2,32);
+}
+
+
+vuint64m2_t test___riscv_vdivu(vbool32_t mask,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vdivu(mask,op1,op2,32);
+}
+
+
+vuint64m4_t test___riscv_vdivu(vbool16_t mask,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vdivu(mask,op1,op2,32);
+}
+
+
+vuint64m8_t test___riscv_vdivu(vbool8_t mask,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vdivu(mask,op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vdivu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 4 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vdivu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 4 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vdivu_vx_rv64-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vdivu_vx_rv64-1.C
new file mode 100644
index 00000000000..b61a70f4646
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vdivu_vx_rv64-1.C
@@ -0,0 +1,314 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint8mf8_t test___riscv_vdivu(vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vdivu(op1,op2,vl);
+}
+
+
+vuint8mf4_t test___riscv_vdivu(vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vdivu(op1,op2,vl);
+}
+
+
+vuint8mf2_t test___riscv_vdivu(vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vdivu(op1,op2,vl);
+}
+
+
+vuint8m1_t test___riscv_vdivu(vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vdivu(op1,op2,vl);
+}
+
+
+vuint8m2_t test___riscv_vdivu(vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vdivu(op1,op2,vl);
+}
+
+
+vuint8m4_t test___riscv_vdivu(vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vdivu(op1,op2,vl);
+}
+
+
+vuint8m8_t test___riscv_vdivu(vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vdivu(op1,op2,vl);
+}
+
+
+vuint16mf4_t test___riscv_vdivu(vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vdivu(op1,op2,vl);
+}
+
+
+vuint16mf2_t test___riscv_vdivu(vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vdivu(op1,op2,vl);
+}
+
+
+vuint16m1_t test___riscv_vdivu(vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vdivu(op1,op2,vl);
+}
+
+
+vuint16m2_t test___riscv_vdivu(vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vdivu(op1,op2,vl);
+}
+
+
+vuint16m4_t test___riscv_vdivu(vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vdivu(op1,op2,vl);
+}
+
+
+vuint16m8_t test___riscv_vdivu(vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vdivu(op1,op2,vl);
+}
+
+
+vuint32mf2_t test___riscv_vdivu(vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vdivu(op1,op2,vl);
+}
+
+
+vuint32m1_t test___riscv_vdivu(vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vdivu(op1,op2,vl);
+}
+
+
+vuint32m2_t test___riscv_vdivu(vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vdivu(op1,op2,vl);
+}
+
+
+vuint32m4_t test___riscv_vdivu(vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vdivu(op1,op2,vl);
+}
+
+
+vuint32m8_t test___riscv_vdivu(vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vdivu(op1,op2,vl);
+}
+
+
+vuint64m1_t test___riscv_vdivu(vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vdivu(op1,op2,vl);
+}
+
+
+vuint64m2_t test___riscv_vdivu(vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vdivu(op1,op2,vl);
+}
+
+
+vuint64m4_t test___riscv_vdivu(vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vdivu(op1,op2,vl);
+}
+
+
+vuint64m8_t test___riscv_vdivu(vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vdivu(op1,op2,vl);
+}
+
+
+vuint8mf8_t test___riscv_vdivu(vbool64_t mask,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vdivu(mask,op1,op2,vl);
+}
+
+
+vuint8mf4_t test___riscv_vdivu(vbool32_t mask,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vdivu(mask,op1,op2,vl);
+}
+
+
+vuint8mf2_t test___riscv_vdivu(vbool16_t mask,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vdivu(mask,op1,op2,vl);
+}
+
+
+vuint8m1_t test___riscv_vdivu(vbool8_t mask,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vdivu(mask,op1,op2,vl);
+}
+
+
+vuint8m2_t test___riscv_vdivu(vbool4_t mask,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vdivu(mask,op1,op2,vl);
+}
+
+
+vuint8m4_t test___riscv_vdivu(vbool2_t mask,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vdivu(mask,op1,op2,vl);
+}
+
+
+vuint8m8_t test___riscv_vdivu(vbool1_t mask,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vdivu(mask,op1,op2,vl);
+}
+
+
+vuint16mf4_t test___riscv_vdivu(vbool64_t mask,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vdivu(mask,op1,op2,vl);
+}
+
+
+vuint16mf2_t test___riscv_vdivu(vbool32_t mask,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vdivu(mask,op1,op2,vl);
+}
+
+
+vuint16m1_t test___riscv_vdivu(vbool16_t mask,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vdivu(mask,op1,op2,vl);
+}
+
+
+vuint16m2_t test___riscv_vdivu(vbool8_t mask,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vdivu(mask,op1,op2,vl);
+}
+
+
+vuint16m4_t test___riscv_vdivu(vbool4_t mask,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vdivu(mask,op1,op2,vl);
+}
+
+
+vuint16m8_t test___riscv_vdivu(vbool2_t mask,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vdivu(mask,op1,op2,vl);
+}
+
+
+vuint32mf2_t test___riscv_vdivu(vbool64_t mask,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vdivu(mask,op1,op2,vl);
+}
+
+
+vuint32m1_t test___riscv_vdivu(vbool32_t mask,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vdivu(mask,op1,op2,vl);
+}
+
+
+vuint32m2_t test___riscv_vdivu(vbool16_t mask,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vdivu(mask,op1,op2,vl);
+}
+
+
+vuint32m4_t test___riscv_vdivu(vbool8_t mask,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vdivu(mask,op1,op2,vl);
+}
+
+
+vuint32m8_t test___riscv_vdivu(vbool4_t mask,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vdivu(mask,op1,op2,vl);
+}
+
+
+vuint64m1_t test___riscv_vdivu(vbool64_t mask,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vdivu(mask,op1,op2,vl);
+}
+
+
+vuint64m2_t test___riscv_vdivu(vbool32_t mask,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vdivu(mask,op1,op2,vl);
+}
+
+
+vuint64m4_t test___riscv_vdivu(vbool16_t mask,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vdivu(mask,op1,op2,vl);
+}
+
+
+vuint64m8_t test___riscv_vdivu(vbool8_t mask,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vdivu(mask,op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vdivu_vx_rv64-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vdivu_vx_rv64-2.C
new file mode 100644
index 00000000000..d268d22d161
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vdivu_vx_rv64-2.C
@@ -0,0 +1,314 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint8mf8_t test___riscv_vdivu(vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vdivu(op1,op2,31);
+}
+
+
+vuint8mf4_t test___riscv_vdivu(vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vdivu(op1,op2,31);
+}
+
+
+vuint8mf2_t test___riscv_vdivu(vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vdivu(op1,op2,31);
+}
+
+
+vuint8m1_t test___riscv_vdivu(vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vdivu(op1,op2,31);
+}
+
+
+vuint8m2_t test___riscv_vdivu(vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vdivu(op1,op2,31);
+}
+
+
+vuint8m4_t test___riscv_vdivu(vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vdivu(op1,op2,31);
+}
+
+
+vuint8m8_t test___riscv_vdivu(vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vdivu(op1,op2,31);
+}
+
+
+vuint16mf4_t test___riscv_vdivu(vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vdivu(op1,op2,31);
+}
+
+
+vuint16mf2_t test___riscv_vdivu(vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vdivu(op1,op2,31);
+}
+
+
+vuint16m1_t test___riscv_vdivu(vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vdivu(op1,op2,31);
+}
+
+
+vuint16m2_t test___riscv_vdivu(vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vdivu(op1,op2,31);
+}
+
+
+vuint16m4_t test___riscv_vdivu(vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vdivu(op1,op2,31);
+}
+
+
+vuint16m8_t test___riscv_vdivu(vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vdivu(op1,op2,31);
+}
+
+
+vuint32mf2_t test___riscv_vdivu(vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vdivu(op1,op2,31);
+}
+
+
+vuint32m1_t test___riscv_vdivu(vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vdivu(op1,op2,31);
+}
+
+
+vuint32m2_t test___riscv_vdivu(vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vdivu(op1,op2,31);
+}
+
+
+vuint32m4_t test___riscv_vdivu(vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vdivu(op1,op2,31);
+}
+
+
+vuint32m8_t test___riscv_vdivu(vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vdivu(op1,op2,31);
+}
+
+
+vuint64m1_t test___riscv_vdivu(vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vdivu(op1,op2,31);
+}
+
+
+vuint64m2_t test___riscv_vdivu(vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vdivu(op1,op2,31);
+}
+
+
+vuint64m4_t test___riscv_vdivu(vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vdivu(op1,op2,31);
+}
+
+
+vuint64m8_t test___riscv_vdivu(vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vdivu(op1,op2,31);
+}
+
+
+vuint8mf8_t test___riscv_vdivu(vbool64_t mask,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vdivu(mask,op1,op2,31);
+}
+
+
+vuint8mf4_t test___riscv_vdivu(vbool32_t mask,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vdivu(mask,op1,op2,31);
+}
+
+
+vuint8mf2_t test___riscv_vdivu(vbool16_t mask,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vdivu(mask,op1,op2,31);
+}
+
+
+vuint8m1_t test___riscv_vdivu(vbool8_t mask,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vdivu(mask,op1,op2,31);
+}
+
+
+vuint8m2_t test___riscv_vdivu(vbool4_t mask,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vdivu(mask,op1,op2,31);
+}
+
+
+vuint8m4_t test___riscv_vdivu(vbool2_t mask,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vdivu(mask,op1,op2,31);
+}
+
+
+vuint8m8_t test___riscv_vdivu(vbool1_t mask,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vdivu(mask,op1,op2,31);
+}
+
+
+vuint16mf4_t test___riscv_vdivu(vbool64_t mask,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vdivu(mask,op1,op2,31);
+}
+
+
+vuint16mf2_t test___riscv_vdivu(vbool32_t mask,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vdivu(mask,op1,op2,31);
+}
+
+
+vuint16m1_t test___riscv_vdivu(vbool16_t mask,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vdivu(mask,op1,op2,31);
+}
+
+
+vuint16m2_t test___riscv_vdivu(vbool8_t mask,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vdivu(mask,op1,op2,31);
+}
+
+
+vuint16m4_t test___riscv_vdivu(vbool4_t mask,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vdivu(mask,op1,op2,31);
+}
+
+
+vuint16m8_t test___riscv_vdivu(vbool2_t mask,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vdivu(mask,op1,op2,31);
+}
+
+
+vuint32mf2_t test___riscv_vdivu(vbool64_t mask,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vdivu(mask,op1,op2,31);
+}
+
+
+vuint32m1_t test___riscv_vdivu(vbool32_t mask,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vdivu(mask,op1,op2,31);
+}
+
+
+vuint32m2_t test___riscv_vdivu(vbool16_t mask,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vdivu(mask,op1,op2,31);
+}
+
+
+vuint32m4_t test___riscv_vdivu(vbool8_t mask,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vdivu(mask,op1,op2,31);
+}
+
+
+vuint32m8_t test___riscv_vdivu(vbool4_t mask,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vdivu(mask,op1,op2,31);
+}
+
+
+vuint64m1_t test___riscv_vdivu(vbool64_t mask,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vdivu(mask,op1,op2,31);
+}
+
+
+vuint64m2_t test___riscv_vdivu(vbool32_t mask,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vdivu(mask,op1,op2,31);
+}
+
+
+vuint64m4_t test___riscv_vdivu(vbool16_t mask,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vdivu(mask,op1,op2,31);
+}
+
+
+vuint64m8_t test___riscv_vdivu(vbool8_t mask,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vdivu(mask,op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vdivu_vx_rv64-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vdivu_vx_rv64-3.C
new file mode 100644
index 00000000000..f933f809461
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vdivu_vx_rv64-3.C
@@ -0,0 +1,314 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint8mf8_t test___riscv_vdivu(vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vdivu(op1,op2,32);
+}
+
+
+vuint8mf4_t test___riscv_vdivu(vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vdivu(op1,op2,32);
+}
+
+
+vuint8mf2_t test___riscv_vdivu(vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vdivu(op1,op2,32);
+}
+
+
+vuint8m1_t test___riscv_vdivu(vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vdivu(op1,op2,32);
+}
+
+
+vuint8m2_t test___riscv_vdivu(vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vdivu(op1,op2,32);
+}
+
+
+vuint8m4_t test___riscv_vdivu(vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vdivu(op1,op2,32);
+}
+
+
+vuint8m8_t test___riscv_vdivu(vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vdivu(op1,op2,32);
+}
+
+
+vuint16mf4_t test___riscv_vdivu(vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vdivu(op1,op2,32);
+}
+
+
+vuint16mf2_t test___riscv_vdivu(vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vdivu(op1,op2,32);
+}
+
+
+vuint16m1_t test___riscv_vdivu(vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vdivu(op1,op2,32);
+}
+
+
+vuint16m2_t test___riscv_vdivu(vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vdivu(op1,op2,32);
+}
+
+
+vuint16m4_t test___riscv_vdivu(vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vdivu(op1,op2,32);
+}
+
+
+vuint16m8_t test___riscv_vdivu(vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vdivu(op1,op2,32);
+}
+
+
+vuint32mf2_t test___riscv_vdivu(vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vdivu(op1,op2,32);
+}
+
+
+vuint32m1_t test___riscv_vdivu(vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vdivu(op1,op2,32);
+}
+
+
+vuint32m2_t test___riscv_vdivu(vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vdivu(op1,op2,32);
+}
+
+
+vuint32m4_t test___riscv_vdivu(vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vdivu(op1,op2,32);
+}
+
+
+vuint32m8_t test___riscv_vdivu(vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vdivu(op1,op2,32);
+}
+
+
+vuint64m1_t test___riscv_vdivu(vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vdivu(op1,op2,32);
+}
+
+
+vuint64m2_t test___riscv_vdivu(vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vdivu(op1,op2,32);
+}
+
+
+vuint64m4_t test___riscv_vdivu(vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vdivu(op1,op2,32);
+}
+
+
+vuint64m8_t test___riscv_vdivu(vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vdivu(op1,op2,32);
+}
+
+
+vuint8mf8_t test___riscv_vdivu(vbool64_t mask,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vdivu(mask,op1,op2,32);
+}
+
+
+vuint8mf4_t test___riscv_vdivu(vbool32_t mask,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vdivu(mask,op1,op2,32);
+}
+
+
+vuint8mf2_t test___riscv_vdivu(vbool16_t mask,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vdivu(mask,op1,op2,32);
+}
+
+
+vuint8m1_t test___riscv_vdivu(vbool8_t mask,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vdivu(mask,op1,op2,32);
+}
+
+
+vuint8m2_t test___riscv_vdivu(vbool4_t mask,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vdivu(mask,op1,op2,32);
+}
+
+
+vuint8m4_t test___riscv_vdivu(vbool2_t mask,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vdivu(mask,op1,op2,32);
+}
+
+
+vuint8m8_t test___riscv_vdivu(vbool1_t mask,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vdivu(mask,op1,op2,32);
+}
+
+
+vuint16mf4_t test___riscv_vdivu(vbool64_t mask,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vdivu(mask,op1,op2,32);
+}
+
+
+vuint16mf2_t test___riscv_vdivu(vbool32_t mask,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vdivu(mask,op1,op2,32);
+}
+
+
+vuint16m1_t test___riscv_vdivu(vbool16_t mask,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vdivu(mask,op1,op2,32);
+}
+
+
+vuint16m2_t test___riscv_vdivu(vbool8_t mask,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vdivu(mask,op1,op2,32);
+}
+
+
+vuint16m4_t test___riscv_vdivu(vbool4_t mask,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vdivu(mask,op1,op2,32);
+}
+
+
+vuint16m8_t test___riscv_vdivu(vbool2_t mask,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vdivu(mask,op1,op2,32);
+}
+
+
+vuint32mf2_t test___riscv_vdivu(vbool64_t mask,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vdivu(mask,op1,op2,32);
+}
+
+
+vuint32m1_t test___riscv_vdivu(vbool32_t mask,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vdivu(mask,op1,op2,32);
+}
+
+
+vuint32m2_t test___riscv_vdivu(vbool16_t mask,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vdivu(mask,op1,op2,32);
+}
+
+
+vuint32m4_t test___riscv_vdivu(vbool8_t mask,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vdivu(mask,op1,op2,32);
+}
+
+
+vuint32m8_t test___riscv_vdivu(vbool4_t mask,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vdivu(mask,op1,op2,32);
+}
+
+
+vuint64m1_t test___riscv_vdivu(vbool64_t mask,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vdivu(mask,op1,op2,32);
+}
+
+
+vuint64m2_t test___riscv_vdivu(vbool32_t mask,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vdivu(mask,op1,op2,32);
+}
+
+
+vuint64m4_t test___riscv_vdivu(vbool16_t mask,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vdivu(mask,op1,op2,32);
+}
+
+
+vuint64m8_t test___riscv_vdivu(vbool8_t mask,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vdivu(mask,op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vdivu_vx_tu_rv32-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vdivu_vx_tu_rv32-1.C
new file mode 100644
index 00000000000..3d0f2e5d8e9
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vdivu_vx_tu_rv32-1.C
@@ -0,0 +1,157 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint8mf8_t test___riscv_vdivu_tu(vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vdivu_tu(merge,op1,op2,vl);
+}
+
+
+vuint8mf4_t test___riscv_vdivu_tu(vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vdivu_tu(merge,op1,op2,vl);
+}
+
+
+vuint8mf2_t test___riscv_vdivu_tu(vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vdivu_tu(merge,op1,op2,vl);
+}
+
+
+vuint8m1_t test___riscv_vdivu_tu(vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vdivu_tu(merge,op1,op2,vl);
+}
+
+
+vuint8m2_t test___riscv_vdivu_tu(vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vdivu_tu(merge,op1,op2,vl);
+}
+
+
+vuint8m4_t test___riscv_vdivu_tu(vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vdivu_tu(merge,op1,op2,vl);
+}
+
+
+vuint8m8_t test___riscv_vdivu_tu(vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vdivu_tu(merge,op1,op2,vl);
+}
+
+
+vuint16mf4_t test___riscv_vdivu_tu(vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vdivu_tu(merge,op1,op2,vl);
+}
+
+
+vuint16mf2_t test___riscv_vdivu_tu(vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vdivu_tu(merge,op1,op2,vl);
+}
+
+
+vuint16m1_t test___riscv_vdivu_tu(vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vdivu_tu(merge,op1,op2,vl);
+}
+
+
+vuint16m2_t test___riscv_vdivu_tu(vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vdivu_tu(merge,op1,op2,vl);
+}
+
+
+vuint16m4_t test___riscv_vdivu_tu(vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vdivu_tu(merge,op1,op2,vl);
+}
+
+
+vuint16m8_t test___riscv_vdivu_tu(vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vdivu_tu(merge,op1,op2,vl);
+}
+
+
+vuint32mf2_t test___riscv_vdivu_tu(vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vdivu_tu(merge,op1,op2,vl);
+}
+
+
+vuint32m1_t test___riscv_vdivu_tu(vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vdivu_tu(merge,op1,op2,vl);
+}
+
+
+vuint32m2_t test___riscv_vdivu_tu(vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vdivu_tu(merge,op1,op2,vl);
+}
+
+
+vuint32m4_t test___riscv_vdivu_tu(vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vdivu_tu(merge,op1,op2,vl);
+}
+
+
+vuint32m8_t test___riscv_vdivu_tu(vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vdivu_tu(merge,op1,op2,vl);
+}
+
+
+vuint64m1_t test___riscv_vdivu_tu(vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vdivu_tu(merge,op1,op2,vl);
+}
+
+
+vuint64m2_t test___riscv_vdivu_tu(vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vdivu_tu(merge,op1,op2,vl);
+}
+
+
+vuint64m4_t test___riscv_vdivu_tu(vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vdivu_tu(merge,op1,op2,vl);
+}
+
+
+vuint64m8_t test___riscv_vdivu_tu(vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vdivu_tu(merge,op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vdivu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 4 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vdivu_vx_tu_rv32-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vdivu_vx_tu_rv32-2.C
new file mode 100644
index 00000000000..a35ba5c2142
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vdivu_vx_tu_rv32-2.C
@@ -0,0 +1,157 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint8mf8_t test___riscv_vdivu_tu(vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vdivu_tu(merge,op1,op2,31);
+}
+
+
+vuint8mf4_t test___riscv_vdivu_tu(vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vdivu_tu(merge,op1,op2,31);
+}
+
+
+vuint8mf2_t test___riscv_vdivu_tu(vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vdivu_tu(merge,op1,op2,31);
+}
+
+
+vuint8m1_t test___riscv_vdivu_tu(vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vdivu_tu(merge,op1,op2,31);
+}
+
+
+vuint8m2_t test___riscv_vdivu_tu(vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vdivu_tu(merge,op1,op2,31);
+}
+
+
+vuint8m4_t test___riscv_vdivu_tu(vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vdivu_tu(merge,op1,op2,31);
+}
+
+
+vuint8m8_t test___riscv_vdivu_tu(vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vdivu_tu(merge,op1,op2,31);
+}
+
+
+vuint16mf4_t test___riscv_vdivu_tu(vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vdivu_tu(merge,op1,op2,31);
+}
+
+
+vuint16mf2_t test___riscv_vdivu_tu(vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vdivu_tu(merge,op1,op2,31);
+}
+
+
+vuint16m1_t test___riscv_vdivu_tu(vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vdivu_tu(merge,op1,op2,31);
+}
+
+
+vuint16m2_t test___riscv_vdivu_tu(vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vdivu_tu(merge,op1,op2,31);
+}
+
+
+vuint16m4_t test___riscv_vdivu_tu(vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vdivu_tu(merge,op1,op2,31);
+}
+
+
+vuint16m8_t test___riscv_vdivu_tu(vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vdivu_tu(merge,op1,op2,31);
+}
+
+
+vuint32mf2_t test___riscv_vdivu_tu(vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vdivu_tu(merge,op1,op2,31);
+}
+
+
+vuint32m1_t test___riscv_vdivu_tu(vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vdivu_tu(merge,op1,op2,31);
+}
+
+
+vuint32m2_t test___riscv_vdivu_tu(vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vdivu_tu(merge,op1,op2,31);
+}
+
+
+vuint32m4_t test___riscv_vdivu_tu(vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vdivu_tu(merge,op1,op2,31);
+}
+
+
+vuint32m8_t test___riscv_vdivu_tu(vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vdivu_tu(merge,op1,op2,31);
+}
+
+
+vuint64m1_t test___riscv_vdivu_tu(vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vdivu_tu(merge,op1,op2,31);
+}
+
+
+vuint64m2_t test___riscv_vdivu_tu(vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vdivu_tu(merge,op1,op2,31);
+}
+
+
+vuint64m4_t test___riscv_vdivu_tu(vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vdivu_tu(merge,op1,op2,31);
+}
+
+
+vuint64m8_t test___riscv_vdivu_tu(vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vdivu_tu(merge,op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vdivu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 4 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vdivu_vx_tu_rv32-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vdivu_vx_tu_rv32-3.C
new file mode 100644
index 00000000000..129d103f634
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vdivu_vx_tu_rv32-3.C
@@ -0,0 +1,157 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint8mf8_t test___riscv_vdivu_tu(vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vdivu_tu(merge,op1,op2,32);
+}
+
+
+vuint8mf4_t test___riscv_vdivu_tu(vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vdivu_tu(merge,op1,op2,32);
+}
+
+
+vuint8mf2_t test___riscv_vdivu_tu(vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vdivu_tu(merge,op1,op2,32);
+}
+
+
+vuint8m1_t test___riscv_vdivu_tu(vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vdivu_tu(merge,op1,op2,32);
+}
+
+
+vuint8m2_t test___riscv_vdivu_tu(vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vdivu_tu(merge,op1,op2,32);
+}
+
+
+vuint8m4_t test___riscv_vdivu_tu(vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vdivu_tu(merge,op1,op2,32);
+}
+
+
+vuint8m8_t test___riscv_vdivu_tu(vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vdivu_tu(merge,op1,op2,32);
+}
+
+
+vuint16mf4_t test___riscv_vdivu_tu(vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vdivu_tu(merge,op1,op2,32);
+}
+
+
+vuint16mf2_t test___riscv_vdivu_tu(vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vdivu_tu(merge,op1,op2,32);
+}
+
+
+vuint16m1_t test___riscv_vdivu_tu(vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vdivu_tu(merge,op1,op2,32);
+}
+
+
+vuint16m2_t test___riscv_vdivu_tu(vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vdivu_tu(merge,op1,op2,32);
+}
+
+
+vuint16m4_t test___riscv_vdivu_tu(vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vdivu_tu(merge,op1,op2,32);
+}
+
+
+vuint16m8_t test___riscv_vdivu_tu(vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vdivu_tu(merge,op1,op2,32);
+}
+
+
+vuint32mf2_t test___riscv_vdivu_tu(vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vdivu_tu(merge,op1,op2,32);
+}
+
+
+vuint32m1_t test___riscv_vdivu_tu(vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vdivu_tu(merge,op1,op2,32);
+}
+
+
+vuint32m2_t test___riscv_vdivu_tu(vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vdivu_tu(merge,op1,op2,32);
+}
+
+
+vuint32m4_t test___riscv_vdivu_tu(vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vdivu_tu(merge,op1,op2,32);
+}
+
+
+vuint32m8_t test___riscv_vdivu_tu(vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vdivu_tu(merge,op1,op2,32);
+}
+
+
+vuint64m1_t test___riscv_vdivu_tu(vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vdivu_tu(merge,op1,op2,32);
+}
+
+
+vuint64m2_t test___riscv_vdivu_tu(vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vdivu_tu(merge,op1,op2,32);
+}
+
+
+vuint64m4_t test___riscv_vdivu_tu(vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vdivu_tu(merge,op1,op2,32);
+}
+
+
+vuint64m8_t test___riscv_vdivu_tu(vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vdivu_tu(merge,op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vdivu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 4 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vdivu_vx_tu_rv64-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vdivu_vx_tu_rv64-1.C
new file mode 100644
index 00000000000..c109ee200a0
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vdivu_vx_tu_rv64-1.C
@@ -0,0 +1,160 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint8mf8_t test___riscv_vdivu_tu(vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vdivu_tu(merge,op1,op2,vl);
+}
+
+
+vuint8mf4_t test___riscv_vdivu_tu(vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vdivu_tu(merge,op1,op2,vl);
+}
+
+
+vuint8mf2_t test___riscv_vdivu_tu(vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vdivu_tu(merge,op1,op2,vl);
+}
+
+
+vuint8m1_t test___riscv_vdivu_tu(vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vdivu_tu(merge,op1,op2,vl);
+}
+
+
+vuint8m2_t test___riscv_vdivu_tu(vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vdivu_tu(merge,op1,op2,vl);
+}
+
+
+vuint8m4_t test___riscv_vdivu_tu(vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vdivu_tu(merge,op1,op2,vl);
+}
+
+
+vuint8m8_t test___riscv_vdivu_tu(vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vdivu_tu(merge,op1,op2,vl);
+}
+
+
+vuint16mf4_t test___riscv_vdivu_tu(vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vdivu_tu(merge,op1,op2,vl);
+}
+
+
+vuint16mf2_t test___riscv_vdivu_tu(vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vdivu_tu(merge,op1,op2,vl);
+}
+
+
+vuint16m1_t test___riscv_vdivu_tu(vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vdivu_tu(merge,op1,op2,vl);
+}
+
+
+vuint16m2_t test___riscv_vdivu_tu(vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vdivu_tu(merge,op1,op2,vl);
+}
+
+
+vuint16m4_t test___riscv_vdivu_tu(vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vdivu_tu(merge,op1,op2,vl);
+}
+
+
+vuint16m8_t test___riscv_vdivu_tu(vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vdivu_tu(merge,op1,op2,vl);
+}
+
+
+vuint32mf2_t test___riscv_vdivu_tu(vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vdivu_tu(merge,op1,op2,vl);
+}
+
+
+vuint32m1_t test___riscv_vdivu_tu(vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vdivu_tu(merge,op1,op2,vl);
+}
+
+
+vuint32m2_t test___riscv_vdivu_tu(vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vdivu_tu(merge,op1,op2,vl);
+}
+
+
+vuint32m4_t test___riscv_vdivu_tu(vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vdivu_tu(merge,op1,op2,vl);
+}
+
+
+vuint32m8_t test___riscv_vdivu_tu(vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vdivu_tu(merge,op1,op2,vl);
+}
+
+
+vuint64m1_t test___riscv_vdivu_tu(vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vdivu_tu(merge,op1,op2,vl);
+}
+
+
+vuint64m2_t test___riscv_vdivu_tu(vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vdivu_tu(merge,op1,op2,vl);
+}
+
+
+vuint64m4_t test___riscv_vdivu_tu(vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vdivu_tu(merge,op1,op2,vl);
+}
+
+
+vuint64m8_t test___riscv_vdivu_tu(vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vdivu_tu(merge,op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vdivu_vx_tu_rv64-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vdivu_vx_tu_rv64-2.C
new file mode 100644
index 00000000000..ae58b157695
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vdivu_vx_tu_rv64-2.C
@@ -0,0 +1,160 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint8mf8_t test___riscv_vdivu_tu(vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vdivu_tu(merge,op1,op2,31);
+}
+
+
+vuint8mf4_t test___riscv_vdivu_tu(vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vdivu_tu(merge,op1,op2,31);
+}
+
+
+vuint8mf2_t test___riscv_vdivu_tu(vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vdivu_tu(merge,op1,op2,31);
+}
+
+
+vuint8m1_t test___riscv_vdivu_tu(vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vdivu_tu(merge,op1,op2,31);
+}
+
+
+vuint8m2_t test___riscv_vdivu_tu(vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vdivu_tu(merge,op1,op2,31);
+}
+
+
+vuint8m4_t test___riscv_vdivu_tu(vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vdivu_tu(merge,op1,op2,31);
+}
+
+
+vuint8m8_t test___riscv_vdivu_tu(vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vdivu_tu(merge,op1,op2,31);
+}
+
+
+vuint16mf4_t test___riscv_vdivu_tu(vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vdivu_tu(merge,op1,op2,31);
+}
+
+
+vuint16mf2_t test___riscv_vdivu_tu(vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vdivu_tu(merge,op1,op2,31);
+}
+
+
+vuint16m1_t test___riscv_vdivu_tu(vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vdivu_tu(merge,op1,op2,31);
+}
+
+
+vuint16m2_t test___riscv_vdivu_tu(vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vdivu_tu(merge,op1,op2,31);
+}
+
+
+vuint16m4_t test___riscv_vdivu_tu(vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vdivu_tu(merge,op1,op2,31);
+}
+
+
+vuint16m8_t test___riscv_vdivu_tu(vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vdivu_tu(merge,op1,op2,31);
+}
+
+
+vuint32mf2_t test___riscv_vdivu_tu(vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vdivu_tu(merge,op1,op2,31);
+}
+
+
+vuint32m1_t test___riscv_vdivu_tu(vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vdivu_tu(merge,op1,op2,31);
+}
+
+
+vuint32m2_t test___riscv_vdivu_tu(vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vdivu_tu(merge,op1,op2,31);
+}
+
+
+vuint32m4_t test___riscv_vdivu_tu(vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vdivu_tu(merge,op1,op2,31);
+}
+
+
+vuint32m8_t test___riscv_vdivu_tu(vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vdivu_tu(merge,op1,op2,31);
+}
+
+
+vuint64m1_t test___riscv_vdivu_tu(vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vdivu_tu(merge,op1,op2,31);
+}
+
+
+vuint64m2_t test___riscv_vdivu_tu(vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vdivu_tu(merge,op1,op2,31);
+}
+
+
+vuint64m4_t test___riscv_vdivu_tu(vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vdivu_tu(merge,op1,op2,31);
+}
+
+
+vuint64m8_t test___riscv_vdivu_tu(vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vdivu_tu(merge,op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vdivu_vx_tu_rv64-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vdivu_vx_tu_rv64-3.C
new file mode 100644
index 00000000000..fc9874f058f
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vdivu_vx_tu_rv64-3.C
@@ -0,0 +1,160 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint8mf8_t test___riscv_vdivu_tu(vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vdivu_tu(merge,op1,op2,32);
+}
+
+
+vuint8mf4_t test___riscv_vdivu_tu(vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vdivu_tu(merge,op1,op2,32);
+}
+
+
+vuint8mf2_t test___riscv_vdivu_tu(vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vdivu_tu(merge,op1,op2,32);
+}
+
+
+vuint8m1_t test___riscv_vdivu_tu(vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vdivu_tu(merge,op1,op2,32);
+}
+
+
+vuint8m2_t test___riscv_vdivu_tu(vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vdivu_tu(merge,op1,op2,32);
+}
+
+
+vuint8m4_t test___riscv_vdivu_tu(vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vdivu_tu(merge,op1,op2,32);
+}
+
+
+vuint8m8_t test___riscv_vdivu_tu(vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vdivu_tu(merge,op1,op2,32);
+}
+
+
+vuint16mf4_t test___riscv_vdivu_tu(vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vdivu_tu(merge,op1,op2,32);
+}
+
+
+vuint16mf2_t test___riscv_vdivu_tu(vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vdivu_tu(merge,op1,op2,32);
+}
+
+
+vuint16m1_t test___riscv_vdivu_tu(vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vdivu_tu(merge,op1,op2,32);
+}
+
+
+vuint16m2_t test___riscv_vdivu_tu(vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vdivu_tu(merge,op1,op2,32);
+}
+
+
+vuint16m4_t test___riscv_vdivu_tu(vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vdivu_tu(merge,op1,op2,32);
+}
+
+
+vuint16m8_t test___riscv_vdivu_tu(vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vdivu_tu(merge,op1,op2,32);
+}
+
+
+vuint32mf2_t test___riscv_vdivu_tu(vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vdivu_tu(merge,op1,op2,32);
+}
+
+
+vuint32m1_t test___riscv_vdivu_tu(vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vdivu_tu(merge,op1,op2,32);
+}
+
+
+vuint32m2_t test___riscv_vdivu_tu(vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vdivu_tu(merge,op1,op2,32);
+}
+
+
+vuint32m4_t test___riscv_vdivu_tu(vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vdivu_tu(merge,op1,op2,32);
+}
+
+
+vuint32m8_t test___riscv_vdivu_tu(vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vdivu_tu(merge,op1,op2,32);
+}
+
+
+vuint64m1_t test___riscv_vdivu_tu(vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vdivu_tu(merge,op1,op2,32);
+}
+
+
+vuint64m2_t test___riscv_vdivu_tu(vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vdivu_tu(merge,op1,op2,32);
+}
+
+
+vuint64m4_t test___riscv_vdivu_tu(vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vdivu_tu(merge,op1,op2,32);
+}
+
+
+vuint64m8_t test___riscv_vdivu_tu(vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vdivu_tu(merge,op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vdivu_vx_tum_rv32-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vdivu_vx_tum_rv32-1.C
new file mode 100644
index 00000000000..6063430baec
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vdivu_vx_tum_rv32-1.C
@@ -0,0 +1,157 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint8mf8_t test___riscv_vdivu_tum(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vdivu_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint8mf4_t test___riscv_vdivu_tum(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vdivu_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint8mf2_t test___riscv_vdivu_tum(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vdivu_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint8m1_t test___riscv_vdivu_tum(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vdivu_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint8m2_t test___riscv_vdivu_tum(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vdivu_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint8m4_t test___riscv_vdivu_tum(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vdivu_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint8m8_t test___riscv_vdivu_tum(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vdivu_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint16mf4_t test___riscv_vdivu_tum(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vdivu_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint16mf2_t test___riscv_vdivu_tum(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vdivu_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m1_t test___riscv_vdivu_tum(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vdivu_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m2_t test___riscv_vdivu_tum(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vdivu_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m4_t test___riscv_vdivu_tum(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vdivu_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m8_t test___riscv_vdivu_tum(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vdivu_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint32mf2_t test___riscv_vdivu_tum(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vdivu_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m1_t test___riscv_vdivu_tum(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vdivu_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m2_t test___riscv_vdivu_tum(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vdivu_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m4_t test___riscv_vdivu_tum(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vdivu_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m8_t test___riscv_vdivu_tum(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vdivu_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m1_t test___riscv_vdivu_tum(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vdivu_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m2_t test___riscv_vdivu_tum(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vdivu_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m4_t test___riscv_vdivu_tum(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vdivu_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m8_t test___riscv_vdivu_tum(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vdivu_tum(mask,merge,op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vdivu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 4 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vdivu_vx_tum_rv32-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vdivu_vx_tum_rv32-2.C
new file mode 100644
index 00000000000..2c6d58286f2
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vdivu_vx_tum_rv32-2.C
@@ -0,0 +1,157 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint8mf8_t test___riscv_vdivu_tum(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vdivu_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint8mf4_t test___riscv_vdivu_tum(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vdivu_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint8mf2_t test___riscv_vdivu_tum(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vdivu_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint8m1_t test___riscv_vdivu_tum(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vdivu_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint8m2_t test___riscv_vdivu_tum(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vdivu_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint8m4_t test___riscv_vdivu_tum(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vdivu_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint8m8_t test___riscv_vdivu_tum(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vdivu_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint16mf4_t test___riscv_vdivu_tum(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vdivu_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint16mf2_t test___riscv_vdivu_tum(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vdivu_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint16m1_t test___riscv_vdivu_tum(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vdivu_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint16m2_t test___riscv_vdivu_tum(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vdivu_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint16m4_t test___riscv_vdivu_tum(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vdivu_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint16m8_t test___riscv_vdivu_tum(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vdivu_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint32mf2_t test___riscv_vdivu_tum(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vdivu_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint32m1_t test___riscv_vdivu_tum(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vdivu_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint32m2_t test___riscv_vdivu_tum(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vdivu_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint32m4_t test___riscv_vdivu_tum(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vdivu_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint32m8_t test___riscv_vdivu_tum(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vdivu_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint64m1_t test___riscv_vdivu_tum(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vdivu_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint64m2_t test___riscv_vdivu_tum(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vdivu_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint64m4_t test___riscv_vdivu_tum(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vdivu_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint64m8_t test___riscv_vdivu_tum(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vdivu_tum(mask,merge,op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vdivu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 4 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vdivu_vx_tum_rv32-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vdivu_vx_tum_rv32-3.C
new file mode 100644
index 00000000000..0880c63a326
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vdivu_vx_tum_rv32-3.C
@@ -0,0 +1,157 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint8mf8_t test___riscv_vdivu_tum(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vdivu_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint8mf4_t test___riscv_vdivu_tum(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vdivu_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint8mf2_t test___riscv_vdivu_tum(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vdivu_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint8m1_t test___riscv_vdivu_tum(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vdivu_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint8m2_t test___riscv_vdivu_tum(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vdivu_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint8m4_t test___riscv_vdivu_tum(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vdivu_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint8m8_t test___riscv_vdivu_tum(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vdivu_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint16mf4_t test___riscv_vdivu_tum(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vdivu_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint16mf2_t test___riscv_vdivu_tum(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vdivu_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint16m1_t test___riscv_vdivu_tum(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vdivu_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint16m2_t test___riscv_vdivu_tum(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vdivu_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint16m4_t test___riscv_vdivu_tum(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vdivu_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint16m8_t test___riscv_vdivu_tum(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vdivu_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint32mf2_t test___riscv_vdivu_tum(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vdivu_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint32m1_t test___riscv_vdivu_tum(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vdivu_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint32m2_t test___riscv_vdivu_tum(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vdivu_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint32m4_t test___riscv_vdivu_tum(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vdivu_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint32m8_t test___riscv_vdivu_tum(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vdivu_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint64m1_t test___riscv_vdivu_tum(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vdivu_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint64m2_t test___riscv_vdivu_tum(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vdivu_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint64m4_t test___riscv_vdivu_tum(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vdivu_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint64m8_t test___riscv_vdivu_tum(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vdivu_tum(mask,merge,op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vdivu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 4 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vdivu_vx_tum_rv64-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vdivu_vx_tum_rv64-1.C
new file mode 100644
index 00000000000..4234c496dc1
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vdivu_vx_tum_rv64-1.C
@@ -0,0 +1,160 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint8mf8_t test___riscv_vdivu_tum(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vdivu_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint8mf4_t test___riscv_vdivu_tum(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vdivu_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint8mf2_t test___riscv_vdivu_tum(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vdivu_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint8m1_t test___riscv_vdivu_tum(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vdivu_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint8m2_t test___riscv_vdivu_tum(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vdivu_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint8m4_t test___riscv_vdivu_tum(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vdivu_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint8m8_t test___riscv_vdivu_tum(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vdivu_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint16mf4_t test___riscv_vdivu_tum(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vdivu_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint16mf2_t test___riscv_vdivu_tum(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vdivu_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m1_t test___riscv_vdivu_tum(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vdivu_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m2_t test___riscv_vdivu_tum(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vdivu_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m4_t test___riscv_vdivu_tum(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vdivu_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m8_t test___riscv_vdivu_tum(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vdivu_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint32mf2_t test___riscv_vdivu_tum(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vdivu_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m1_t test___riscv_vdivu_tum(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vdivu_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m2_t test___riscv_vdivu_tum(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vdivu_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m4_t test___riscv_vdivu_tum(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vdivu_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m8_t test___riscv_vdivu_tum(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vdivu_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m1_t test___riscv_vdivu_tum(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vdivu_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m2_t test___riscv_vdivu_tum(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vdivu_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m4_t test___riscv_vdivu_tum(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vdivu_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m8_t test___riscv_vdivu_tum(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vdivu_tum(mask,merge,op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vdivu_vx_tum_rv64-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vdivu_vx_tum_rv64-2.C
new file mode 100644
index 00000000000..a02d9946201
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vdivu_vx_tum_rv64-2.C
@@ -0,0 +1,160 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint8mf8_t test___riscv_vdivu_tum(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vdivu_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint8mf4_t test___riscv_vdivu_tum(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vdivu_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint8mf2_t test___riscv_vdivu_tum(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vdivu_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint8m1_t test___riscv_vdivu_tum(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vdivu_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint8m2_t test___riscv_vdivu_tum(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vdivu_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint8m4_t test___riscv_vdivu_tum(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vdivu_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint8m8_t test___riscv_vdivu_tum(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vdivu_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint16mf4_t test___riscv_vdivu_tum(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vdivu_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint16mf2_t test___riscv_vdivu_tum(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vdivu_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint16m1_t test___riscv_vdivu_tum(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vdivu_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint16m2_t test___riscv_vdivu_tum(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vdivu_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint16m4_t test___riscv_vdivu_tum(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vdivu_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint16m8_t test___riscv_vdivu_tum(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vdivu_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint32mf2_t test___riscv_vdivu_tum(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vdivu_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint32m1_t test___riscv_vdivu_tum(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vdivu_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint32m2_t test___riscv_vdivu_tum(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vdivu_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint32m4_t test___riscv_vdivu_tum(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vdivu_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint32m8_t test___riscv_vdivu_tum(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vdivu_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint64m1_t test___riscv_vdivu_tum(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vdivu_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint64m2_t test___riscv_vdivu_tum(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vdivu_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint64m4_t test___riscv_vdivu_tum(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vdivu_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint64m8_t test___riscv_vdivu_tum(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vdivu_tum(mask,merge,op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vdivu_vx_tum_rv64-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vdivu_vx_tum_rv64-3.C
new file mode 100644
index 00000000000..afb560fcb22
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vdivu_vx_tum_rv64-3.C
@@ -0,0 +1,160 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint8mf8_t test___riscv_vdivu_tum(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vdivu_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint8mf4_t test___riscv_vdivu_tum(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vdivu_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint8mf2_t test___riscv_vdivu_tum(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vdivu_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint8m1_t test___riscv_vdivu_tum(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vdivu_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint8m2_t test___riscv_vdivu_tum(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vdivu_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint8m4_t test___riscv_vdivu_tum(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vdivu_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint8m8_t test___riscv_vdivu_tum(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vdivu_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint16mf4_t test___riscv_vdivu_tum(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vdivu_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint16mf2_t test___riscv_vdivu_tum(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vdivu_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint16m1_t test___riscv_vdivu_tum(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vdivu_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint16m2_t test___riscv_vdivu_tum(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vdivu_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint16m4_t test___riscv_vdivu_tum(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vdivu_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint16m8_t test___riscv_vdivu_tum(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vdivu_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint32mf2_t test___riscv_vdivu_tum(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vdivu_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint32m1_t test___riscv_vdivu_tum(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vdivu_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint32m2_t test___riscv_vdivu_tum(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vdivu_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint32m4_t test___riscv_vdivu_tum(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vdivu_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint32m8_t test___riscv_vdivu_tum(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vdivu_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint64m1_t test___riscv_vdivu_tum(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vdivu_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint64m2_t test___riscv_vdivu_tum(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vdivu_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint64m4_t test___riscv_vdivu_tum(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vdivu_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint64m8_t test___riscv_vdivu_tum(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vdivu_tum(mask,merge,op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vdivu_vx_tumu_rv32-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vdivu_vx_tumu_rv32-1.C
new file mode 100644
index 00000000000..616568ac035
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vdivu_vx_tumu_rv32-1.C
@@ -0,0 +1,157 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint8mf8_t test___riscv_vdivu_tumu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vdivu_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint8mf4_t test___riscv_vdivu_tumu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vdivu_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint8mf2_t test___riscv_vdivu_tumu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vdivu_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint8m1_t test___riscv_vdivu_tumu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vdivu_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint8m2_t test___riscv_vdivu_tumu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vdivu_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint8m4_t test___riscv_vdivu_tumu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vdivu_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint8m8_t test___riscv_vdivu_tumu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vdivu_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint16mf4_t test___riscv_vdivu_tumu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vdivu_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint16mf2_t test___riscv_vdivu_tumu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vdivu_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m1_t test___riscv_vdivu_tumu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vdivu_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m2_t test___riscv_vdivu_tumu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vdivu_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m4_t test___riscv_vdivu_tumu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vdivu_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m8_t test___riscv_vdivu_tumu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vdivu_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint32mf2_t test___riscv_vdivu_tumu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vdivu_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m1_t test___riscv_vdivu_tumu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vdivu_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m2_t test___riscv_vdivu_tumu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vdivu_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m4_t test___riscv_vdivu_tumu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vdivu_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m8_t test___riscv_vdivu_tumu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vdivu_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m1_t test___riscv_vdivu_tumu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vdivu_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m2_t test___riscv_vdivu_tumu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vdivu_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m4_t test___riscv_vdivu_tumu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vdivu_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m8_t test___riscv_vdivu_tumu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vdivu_tumu(mask,merge,op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*mu\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*mu\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*mu\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vdivu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 4 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vdivu_vx_tumu_rv32-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vdivu_vx_tumu_rv32-2.C
new file mode 100644
index 00000000000..85b7edfac31
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vdivu_vx_tumu_rv32-2.C
@@ -0,0 +1,157 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint8mf8_t test___riscv_vdivu_tumu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vdivu_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint8mf4_t test___riscv_vdivu_tumu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vdivu_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint8mf2_t test___riscv_vdivu_tumu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vdivu_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint8m1_t test___riscv_vdivu_tumu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vdivu_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint8m2_t test___riscv_vdivu_tumu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vdivu_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint8m4_t test___riscv_vdivu_tumu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vdivu_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint8m8_t test___riscv_vdivu_tumu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vdivu_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint16mf4_t test___riscv_vdivu_tumu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vdivu_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint16mf2_t test___riscv_vdivu_tumu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vdivu_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint16m1_t test___riscv_vdivu_tumu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vdivu_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint16m2_t test___riscv_vdivu_tumu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vdivu_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint16m4_t test___riscv_vdivu_tumu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vdivu_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint16m8_t test___riscv_vdivu_tumu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vdivu_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint32mf2_t test___riscv_vdivu_tumu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vdivu_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint32m1_t test___riscv_vdivu_tumu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vdivu_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint32m2_t test___riscv_vdivu_tumu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vdivu_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint32m4_t test___riscv_vdivu_tumu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vdivu_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint32m8_t test___riscv_vdivu_tumu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vdivu_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint64m1_t test___riscv_vdivu_tumu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vdivu_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint64m2_t test___riscv_vdivu_tumu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vdivu_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint64m4_t test___riscv_vdivu_tumu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vdivu_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint64m8_t test___riscv_vdivu_tumu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vdivu_tumu(mask,merge,op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*mu\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*mu\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*mu\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*mu\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*mu\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*mu\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*mu\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*mu\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*mu\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*mu\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*mu\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*mu\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*mu\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*mu\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*mu\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*mu\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*mu\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*mu\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vdivu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 4 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vdivu_vx_tumu_rv32-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vdivu_vx_tumu_rv32-3.C
new file mode 100644
index 00000000000..5fd3cb32bb6
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vdivu_vx_tumu_rv32-3.C
@@ -0,0 +1,157 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint8mf8_t test___riscv_vdivu_tumu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vdivu_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint8mf4_t test___riscv_vdivu_tumu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vdivu_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint8mf2_t test___riscv_vdivu_tumu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vdivu_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint8m1_t test___riscv_vdivu_tumu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vdivu_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint8m2_t test___riscv_vdivu_tumu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vdivu_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint8m4_t test___riscv_vdivu_tumu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vdivu_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint8m8_t test___riscv_vdivu_tumu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vdivu_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint16mf4_t test___riscv_vdivu_tumu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vdivu_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint16mf2_t test___riscv_vdivu_tumu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vdivu_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint16m1_t test___riscv_vdivu_tumu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vdivu_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint16m2_t test___riscv_vdivu_tumu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vdivu_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint16m4_t test___riscv_vdivu_tumu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vdivu_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint16m8_t test___riscv_vdivu_tumu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vdivu_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint32mf2_t test___riscv_vdivu_tumu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vdivu_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint32m1_t test___riscv_vdivu_tumu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vdivu_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint32m2_t test___riscv_vdivu_tumu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vdivu_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint32m4_t test___riscv_vdivu_tumu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vdivu_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint32m8_t test___riscv_vdivu_tumu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vdivu_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint64m1_t test___riscv_vdivu_tumu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vdivu_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint64m2_t test___riscv_vdivu_tumu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vdivu_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint64m4_t test___riscv_vdivu_tumu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vdivu_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint64m8_t test___riscv_vdivu_tumu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vdivu_tumu(mask,merge,op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*mu\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*mu\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*mu\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vdivu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 4 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vdivu_vx_tumu_rv64-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vdivu_vx_tumu_rv64-1.C
new file mode 100644
index 00000000000..3a4f5da7153
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vdivu_vx_tumu_rv64-1.C
@@ -0,0 +1,160 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint8mf8_t test___riscv_vdivu_tumu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vdivu_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint8mf4_t test___riscv_vdivu_tumu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vdivu_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint8mf2_t test___riscv_vdivu_tumu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vdivu_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint8m1_t test___riscv_vdivu_tumu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vdivu_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint8m2_t test___riscv_vdivu_tumu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vdivu_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint8m4_t test___riscv_vdivu_tumu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vdivu_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint8m8_t test___riscv_vdivu_tumu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vdivu_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint16mf4_t test___riscv_vdivu_tumu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vdivu_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint16mf2_t test___riscv_vdivu_tumu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vdivu_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m1_t test___riscv_vdivu_tumu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vdivu_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m2_t test___riscv_vdivu_tumu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vdivu_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m4_t test___riscv_vdivu_tumu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vdivu_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m8_t test___riscv_vdivu_tumu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vdivu_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint32mf2_t test___riscv_vdivu_tumu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vdivu_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m1_t test___riscv_vdivu_tumu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vdivu_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m2_t test___riscv_vdivu_tumu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vdivu_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m4_t test___riscv_vdivu_tumu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vdivu_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m8_t test___riscv_vdivu_tumu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vdivu_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m1_t test___riscv_vdivu_tumu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vdivu_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m2_t test___riscv_vdivu_tumu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vdivu_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m4_t test___riscv_vdivu_tumu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vdivu_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m8_t test___riscv_vdivu_tumu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vdivu_tumu(mask,merge,op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*mu\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*mu\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*mu\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*mu\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*mu\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*mu\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*mu\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vdivu_vx_tumu_rv64-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vdivu_vx_tumu_rv64-2.C
new file mode 100644
index 00000000000..a22891f48b1
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vdivu_vx_tumu_rv64-2.C
@@ -0,0 +1,160 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint8mf8_t test___riscv_vdivu_tumu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vdivu_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint8mf4_t test___riscv_vdivu_tumu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vdivu_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint8mf2_t test___riscv_vdivu_tumu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vdivu_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint8m1_t test___riscv_vdivu_tumu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vdivu_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint8m2_t test___riscv_vdivu_tumu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vdivu_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint8m4_t test___riscv_vdivu_tumu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vdivu_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint8m8_t test___riscv_vdivu_tumu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vdivu_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint16mf4_t test___riscv_vdivu_tumu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vdivu_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint16mf2_t test___riscv_vdivu_tumu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vdivu_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint16m1_t test___riscv_vdivu_tumu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vdivu_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint16m2_t test___riscv_vdivu_tumu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vdivu_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint16m4_t test___riscv_vdivu_tumu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vdivu_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint16m8_t test___riscv_vdivu_tumu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vdivu_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint32mf2_t test___riscv_vdivu_tumu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vdivu_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint32m1_t test___riscv_vdivu_tumu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vdivu_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint32m2_t test___riscv_vdivu_tumu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vdivu_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint32m4_t test___riscv_vdivu_tumu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vdivu_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint32m8_t test___riscv_vdivu_tumu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vdivu_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint64m1_t test___riscv_vdivu_tumu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vdivu_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint64m2_t test___riscv_vdivu_tumu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vdivu_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint64m4_t test___riscv_vdivu_tumu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vdivu_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint64m8_t test___riscv_vdivu_tumu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vdivu_tumu(mask,merge,op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*mu\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*mu\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*mu\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*mu\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*mu\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*mu\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*mu\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*mu\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*mu\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*mu\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*mu\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*mu\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*mu\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*mu\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*mu\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*mu\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*mu\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*mu\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*mu\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*mu\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*mu\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*mu\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vdivu_vx_tumu_rv64-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vdivu_vx_tumu_rv64-3.C
new file mode 100644
index 00000000000..3eec4fe8185
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vdivu_vx_tumu_rv64-3.C
@@ -0,0 +1,160 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint8mf8_t test___riscv_vdivu_tumu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vdivu_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint8mf4_t test___riscv_vdivu_tumu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vdivu_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint8mf2_t test___riscv_vdivu_tumu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vdivu_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint8m1_t test___riscv_vdivu_tumu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vdivu_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint8m2_t test___riscv_vdivu_tumu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vdivu_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint8m4_t test___riscv_vdivu_tumu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vdivu_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint8m8_t test___riscv_vdivu_tumu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vdivu_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint16mf4_t test___riscv_vdivu_tumu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vdivu_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint16mf2_t test___riscv_vdivu_tumu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vdivu_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint16m1_t test___riscv_vdivu_tumu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vdivu_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint16m2_t test___riscv_vdivu_tumu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vdivu_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint16m4_t test___riscv_vdivu_tumu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vdivu_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint16m8_t test___riscv_vdivu_tumu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vdivu_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint32mf2_t test___riscv_vdivu_tumu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vdivu_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint32m1_t test___riscv_vdivu_tumu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vdivu_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint32m2_t test___riscv_vdivu_tumu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vdivu_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint32m4_t test___riscv_vdivu_tumu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vdivu_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint32m8_t test___riscv_vdivu_tumu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vdivu_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint64m1_t test___riscv_vdivu_tumu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vdivu_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint64m2_t test___riscv_vdivu_tumu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vdivu_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint64m4_t test___riscv_vdivu_tumu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vdivu_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint64m8_t test___riscv_vdivu_tumu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vdivu_tumu(mask,merge,op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*mu\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*mu\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*mu\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*mu\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*mu\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*mu\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*mu\s+vdivu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */