From patchwork Fri Feb 3 07:51:54 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "juzhe.zhong@rivai.ai" X-Patchwork-Id: 64226 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id C872B3858C5F for ; Fri, 3 Feb 2023 07:52:59 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from smtpbg153.qq.com (smtpbg153.qq.com [13.245.218.24]) by sourceware.org (Postfix) with ESMTPS id 0070A3858C52 for ; Fri, 3 Feb 2023 07:52:04 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 0070A3858C52 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivai.ai Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivai.ai X-QQ-mid: bizesmtp71t1675410717twp3xr9w Received: from server1.localdomain ( [58.60.1.22]) by bizesmtp.qq.com (ESMTP) with id ; Fri, 03 Feb 2023 15:51:56 +0800 (CST) X-QQ-SSF: 01400000000000E0L000000A0000000 X-QQ-FEAT: 4YCIXoSNyy6ge9RV0wyqZ1azy53+YPHUObQRDsGKw1R9w4yIh2oIgMbFV67SW KjZYQPcBrYdHILtQLIic8uSRKRNwY0RwEj1Aez2qkqjGj2NMz9R1hQlr4zvaKRs1Tlw0Xg0 SZWgwLmHbyjfovEWQohBPdisVmVUYjlsjyXXtGMpAj42QNZP6uvp6NLT667Ww5l7mNUY4hR fDNzbJK9f/Vb4w/K3nRpnwB5V+IzZ5md/hMV5qTQYqYVVxFTxaiDHKgIvAx/9+j1wOfId4C ol4A8ofUCazgQdJzZThhKcabsmycPBODipi7O/XMjd8QlTvwpW+0tu3S2JY13KHZNlZtkcz paW4x+TVZ2nKS+zFSLI4PABPi/DzoNXInWnNIPXr7g9XRv5Oag1xSHksd940z9ziv7nwEFl X-QQ-GoodBg: 2 From: juzhe.zhong@rivai.ai To: gcc-patches@gcc.gnu.org Cc: kito.cheng@gmail.com, Ju-Zhe Zhong Subject: [PATCH] RISC-V: Add vor.vx C++ API tests Date: Fri, 3 Feb 2023 15:51:54 +0800 Message-Id: <20230203075154.207608-1-juzhe.zhong@rivai.ai> X-Mailer: git-send-email 2.36.1 MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:rivai.ai:qybglogicsvr:qybglogicsvr7 X-Spam-Status: No, score=-10.9 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, RCVD_IN_BARRACUDACENTRAL, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_PASS, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" From: Ju-Zhe Zhong gcc/testsuite/ChangeLog: * g++.target/riscv/rvv/base/vor_vx_mu_rv32-1.C: New test. * g++.target/riscv/rvv/base/vor_vx_mu_rv32-2.C: New test. * g++.target/riscv/rvv/base/vor_vx_mu_rv32-3.C: New test. * g++.target/riscv/rvv/base/vor_vx_mu_rv64-1.C: New test. * g++.target/riscv/rvv/base/vor_vx_mu_rv64-2.C: New test. * g++.target/riscv/rvv/base/vor_vx_mu_rv64-3.C: New test. * g++.target/riscv/rvv/base/vor_vx_rv32-1.C: New test. * g++.target/riscv/rvv/base/vor_vx_rv32-2.C: New test. * g++.target/riscv/rvv/base/vor_vx_rv32-3.C: New test. * g++.target/riscv/rvv/base/vor_vx_rv64-1.C: New test. * g++.target/riscv/rvv/base/vor_vx_rv64-2.C: New test. * g++.target/riscv/rvv/base/vor_vx_rv64-3.C: New test. * g++.target/riscv/rvv/base/vor_vx_tu_rv32-1.C: New test. * g++.target/riscv/rvv/base/vor_vx_tu_rv32-2.C: New test. * g++.target/riscv/rvv/base/vor_vx_tu_rv32-3.C: New test. * g++.target/riscv/rvv/base/vor_vx_tu_rv64-1.C: New test. * g++.target/riscv/rvv/base/vor_vx_tu_rv64-2.C: New test. * g++.target/riscv/rvv/base/vor_vx_tu_rv64-3.C: New test. * g++.target/riscv/rvv/base/vor_vx_tum_rv32-1.C: New test. * g++.target/riscv/rvv/base/vor_vx_tum_rv32-2.C: New test. * g++.target/riscv/rvv/base/vor_vx_tum_rv32-3.C: New test. * g++.target/riscv/rvv/base/vor_vx_tum_rv64-1.C: New test. * g++.target/riscv/rvv/base/vor_vx_tum_rv64-2.C: New test. * g++.target/riscv/rvv/base/vor_vx_tum_rv64-3.C: New test. * g++.target/riscv/rvv/base/vor_vx_tumu_rv32-1.C: New test. * g++.target/riscv/rvv/base/vor_vx_tumu_rv32-2.C: New test. * g++.target/riscv/rvv/base/vor_vx_tumu_rv32-3.C: New test. * g++.target/riscv/rvv/base/vor_vx_tumu_rv64-1.C: New test. * g++.target/riscv/rvv/base/vor_vx_tumu_rv64-2.C: New test. * g++.target/riscv/rvv/base/vor_vx_tumu_rv64-3.C: New test. --- .../riscv/rvv/base/vor_vx_mu_rv32-1.C | 289 +++++++++ .../riscv/rvv/base/vor_vx_mu_rv32-2.C | 289 +++++++++ .../riscv/rvv/base/vor_vx_mu_rv32-3.C | 289 +++++++++ .../riscv/rvv/base/vor_vx_mu_rv64-1.C | 292 +++++++++ .../riscv/rvv/base/vor_vx_mu_rv64-2.C | 292 +++++++++ .../riscv/rvv/base/vor_vx_mu_rv64-3.C | 292 +++++++++ .../g++.target/riscv/rvv/base/vor_vx_rv32-1.C | 572 +++++++++++++++++ .../g++.target/riscv/rvv/base/vor_vx_rv32-2.C | 572 +++++++++++++++++ .../g++.target/riscv/rvv/base/vor_vx_rv32-3.C | 572 +++++++++++++++++ .../g++.target/riscv/rvv/base/vor_vx_rv64-1.C | 578 ++++++++++++++++++ .../g++.target/riscv/rvv/base/vor_vx_rv64-2.C | 578 ++++++++++++++++++ .../g++.target/riscv/rvv/base/vor_vx_rv64-3.C | 578 ++++++++++++++++++ .../riscv/rvv/base/vor_vx_tu_rv32-1.C | 289 +++++++++ .../riscv/rvv/base/vor_vx_tu_rv32-2.C | 289 +++++++++ .../riscv/rvv/base/vor_vx_tu_rv32-3.C | 289 +++++++++ .../riscv/rvv/base/vor_vx_tu_rv64-1.C | 292 +++++++++ .../riscv/rvv/base/vor_vx_tu_rv64-2.C | 292 +++++++++ .../riscv/rvv/base/vor_vx_tu_rv64-3.C | 292 +++++++++ .../riscv/rvv/base/vor_vx_tum_rv32-1.C | 289 +++++++++ .../riscv/rvv/base/vor_vx_tum_rv32-2.C | 289 +++++++++ .../riscv/rvv/base/vor_vx_tum_rv32-3.C | 289 +++++++++ .../riscv/rvv/base/vor_vx_tum_rv64-1.C | 292 +++++++++ .../riscv/rvv/base/vor_vx_tum_rv64-2.C | 292 +++++++++ .../riscv/rvv/base/vor_vx_tum_rv64-3.C | 292 +++++++++ .../riscv/rvv/base/vor_vx_tumu_rv32-1.C | 289 +++++++++ .../riscv/rvv/base/vor_vx_tumu_rv32-2.C | 289 +++++++++ .../riscv/rvv/base/vor_vx_tumu_rv32-3.C | 289 +++++++++ .../riscv/rvv/base/vor_vx_tumu_rv64-1.C | 292 +++++++++ .../riscv/rvv/base/vor_vx_tumu_rv64-2.C | 292 +++++++++ .../riscv/rvv/base/vor_vx_tumu_rv64-3.C | 292 +++++++++ 30 files changed, 10422 insertions(+) create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vor_vx_mu_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vor_vx_mu_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vor_vx_mu_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vor_vx_mu_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vor_vx_mu_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vor_vx_mu_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vor_vx_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vor_vx_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vor_vx_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vor_vx_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vor_vx_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vor_vx_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vor_vx_tu_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vor_vx_tu_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vor_vx_tu_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vor_vx_tu_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vor_vx_tu_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vor_vx_tu_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vor_vx_tum_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vor_vx_tum_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vor_vx_tum_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vor_vx_tum_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vor_vx_tum_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vor_vx_tum_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vor_vx_tumu_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vor_vx_tumu_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vor_vx_tumu_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vor_vx_tumu_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vor_vx_tumu_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vor_vx_tumu_rv64-3.C diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vor_vx_mu_rv32-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vor_vx_mu_rv32-1.C new file mode 100644 index 00000000000..6b591dc90b3 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vor_vx_mu_rv32-1.C @@ -0,0 +1,289 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vor_mu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,vl); +} + + +vint8mf4_t test___riscv_vor_mu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,vl); +} + + +vint8mf2_t test___riscv_vor_mu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,vl); +} + + +vint8m1_t test___riscv_vor_mu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,vl); +} + + +vint8m2_t test___riscv_vor_mu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,vl); +} + + +vint8m4_t test___riscv_vor_mu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,vl); +} + + +vint8m8_t test___riscv_vor_mu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,vl); +} + + +vint16mf4_t test___riscv_vor_mu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,vl); +} + + +vint16mf2_t test___riscv_vor_mu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,vl); +} + + +vint16m1_t test___riscv_vor_mu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,vl); +} + + +vint16m2_t test___riscv_vor_mu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,vl); +} + + +vint16m4_t test___riscv_vor_mu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,vl); +} + + +vint16m8_t test___riscv_vor_mu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,vl); +} + + +vint32mf2_t test___riscv_vor_mu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,vl); +} + + +vint32m1_t test___riscv_vor_mu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,vl); +} + + +vint32m2_t test___riscv_vor_mu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,vl); +} + + +vint32m4_t test___riscv_vor_mu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,vl); +} + + +vint32m8_t test___riscv_vor_mu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,vl); +} + + +vint64m1_t test___riscv_vor_mu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,vl); +} + + +vint64m2_t test___riscv_vor_mu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,vl); +} + + +vint64m4_t test___riscv_vor_mu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,vl); +} + + +vint64m8_t test___riscv_vor_mu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,vl); +} + + +vuint8mf8_t test___riscv_vor_mu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,vl); +} + + +vuint8mf4_t test___riscv_vor_mu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,vl); +} + + +vuint8mf2_t test___riscv_vor_mu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,vl); +} + + +vuint8m1_t test___riscv_vor_mu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,vl); +} + + +vuint8m2_t test___riscv_vor_mu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,vl); +} + + +vuint8m4_t test___riscv_vor_mu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,vl); +} + + +vuint8m8_t test___riscv_vor_mu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,vl); +} + + +vuint16mf4_t test___riscv_vor_mu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,vl); +} + + +vuint16mf2_t test___riscv_vor_mu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,vl); +} + + +vuint16m1_t test___riscv_vor_mu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,vl); +} + + +vuint16m2_t test___riscv_vor_mu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,vl); +} + + +vuint16m4_t test___riscv_vor_mu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,vl); +} + + +vuint16m8_t test___riscv_vor_mu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,vl); +} + + +vuint32mf2_t test___riscv_vor_mu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,vl); +} + + +vuint32m1_t test___riscv_vor_mu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,vl); +} + + +vuint32m2_t test___riscv_vor_mu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,vl); +} + + +vuint32m4_t test___riscv_vor_mu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,vl); +} + + +vuint32m8_t test___riscv_vor_mu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,vl); +} + + +vuint64m1_t test___riscv_vor_mu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,vl); +} + + +vuint64m2_t test___riscv_vor_mu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,vl); +} + + +vuint64m4_t test___riscv_vor_mu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,vl); +} + + +vuint64m8_t test___riscv_vor_mu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*mu\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 8 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vor_vx_mu_rv32-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vor_vx_mu_rv32-2.C new file mode 100644 index 00000000000..674cc0805f3 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vor_vx_mu_rv32-2.C @@ -0,0 +1,289 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vor_mu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,31); +} + + +vint8mf4_t test___riscv_vor_mu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,31); +} + + +vint8mf2_t test___riscv_vor_mu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,31); +} + + +vint8m1_t test___riscv_vor_mu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,31); +} + + +vint8m2_t test___riscv_vor_mu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,31); +} + + +vint8m4_t test___riscv_vor_mu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,31); +} + + +vint8m8_t test___riscv_vor_mu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,31); +} + + +vint16mf4_t test___riscv_vor_mu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,31); +} + + +vint16mf2_t test___riscv_vor_mu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,31); +} + + +vint16m1_t test___riscv_vor_mu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,31); +} + + +vint16m2_t test___riscv_vor_mu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,31); +} + + +vint16m4_t test___riscv_vor_mu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,31); +} + + +vint16m8_t test___riscv_vor_mu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,31); +} + + +vint32mf2_t test___riscv_vor_mu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,31); +} + + +vint32m1_t test___riscv_vor_mu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,31); +} + + +vint32m2_t test___riscv_vor_mu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,31); +} + + +vint32m4_t test___riscv_vor_mu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,31); +} + + +vint32m8_t test___riscv_vor_mu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,31); +} + + +vint64m1_t test___riscv_vor_mu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,31); +} + + +vint64m2_t test___riscv_vor_mu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,31); +} + + +vint64m4_t test___riscv_vor_mu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,31); +} + + +vint64m8_t test___riscv_vor_mu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,31); +} + + +vuint8mf8_t test___riscv_vor_mu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,31); +} + + +vuint8mf4_t test___riscv_vor_mu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,31); +} + + +vuint8mf2_t test___riscv_vor_mu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,31); +} + + +vuint8m1_t test___riscv_vor_mu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,31); +} + + +vuint8m2_t test___riscv_vor_mu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,31); +} + + +vuint8m4_t test___riscv_vor_mu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,31); +} + + +vuint8m8_t test___riscv_vor_mu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,31); +} + + +vuint16mf4_t test___riscv_vor_mu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,31); +} + + +vuint16mf2_t test___riscv_vor_mu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,31); +} + + +vuint16m1_t test___riscv_vor_mu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,31); +} + + +vuint16m2_t test___riscv_vor_mu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,31); +} + + +vuint16m4_t test___riscv_vor_mu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,31); +} + + +vuint16m8_t test___riscv_vor_mu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,31); +} + + +vuint32mf2_t test___riscv_vor_mu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,31); +} + + +vuint32m1_t test___riscv_vor_mu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,31); +} + + +vuint32m2_t test___riscv_vor_mu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,31); +} + + +vuint32m4_t test___riscv_vor_mu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,31); +} + + +vuint32m8_t test___riscv_vor_mu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,31); +} + + +vuint64m1_t test___riscv_vor_mu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,31); +} + + +vuint64m2_t test___riscv_vor_mu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,31); +} + + +vuint64m4_t test___riscv_vor_mu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,31); +} + + +vuint64m8_t test___riscv_vor_mu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*mu\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*mu\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*mu\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*mu\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*mu\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*mu\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*mu\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*mu\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*mu\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*mu\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*mu\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*mu\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 8 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vor_vx_mu_rv32-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vor_vx_mu_rv32-3.C new file mode 100644 index 00000000000..d601403d7d8 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vor_vx_mu_rv32-3.C @@ -0,0 +1,289 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vor_mu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,32); +} + + +vint8mf4_t test___riscv_vor_mu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,32); +} + + +vint8mf2_t test___riscv_vor_mu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,32); +} + + +vint8m1_t test___riscv_vor_mu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,32); +} + + +vint8m2_t test___riscv_vor_mu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,32); +} + + +vint8m4_t test___riscv_vor_mu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,32); +} + + +vint8m8_t test___riscv_vor_mu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,32); +} + + +vint16mf4_t test___riscv_vor_mu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,32); +} + + +vint16mf2_t test___riscv_vor_mu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,32); +} + + +vint16m1_t test___riscv_vor_mu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,32); +} + + +vint16m2_t test___riscv_vor_mu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,32); +} + + +vint16m4_t test___riscv_vor_mu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,32); +} + + +vint16m8_t test___riscv_vor_mu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,32); +} + + +vint32mf2_t test___riscv_vor_mu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,32); +} + + +vint32m1_t test___riscv_vor_mu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,32); +} + + +vint32m2_t test___riscv_vor_mu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,32); +} + + +vint32m4_t test___riscv_vor_mu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,32); +} + + +vint32m8_t test___riscv_vor_mu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,32); +} + + +vint64m1_t test___riscv_vor_mu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,32); +} + + +vint64m2_t test___riscv_vor_mu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,32); +} + + +vint64m4_t test___riscv_vor_mu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,32); +} + + +vint64m8_t test___riscv_vor_mu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,32); +} + + +vuint8mf8_t test___riscv_vor_mu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,32); +} + + +vuint8mf4_t test___riscv_vor_mu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,32); +} + + +vuint8mf2_t test___riscv_vor_mu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,32); +} + + +vuint8m1_t test___riscv_vor_mu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,32); +} + + +vuint8m2_t test___riscv_vor_mu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,32); +} + + +vuint8m4_t test___riscv_vor_mu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,32); +} + + +vuint8m8_t test___riscv_vor_mu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,32); +} + + +vuint16mf4_t test___riscv_vor_mu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,32); +} + + +vuint16mf2_t test___riscv_vor_mu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,32); +} + + +vuint16m1_t test___riscv_vor_mu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,32); +} + + +vuint16m2_t test___riscv_vor_mu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,32); +} + + +vuint16m4_t test___riscv_vor_mu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,32); +} + + +vuint16m8_t test___riscv_vor_mu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,32); +} + + +vuint32mf2_t test___riscv_vor_mu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,32); +} + + +vuint32m1_t test___riscv_vor_mu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,32); +} + + +vuint32m2_t test___riscv_vor_mu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,32); +} + + +vuint32m4_t test___riscv_vor_mu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,32); +} + + +vuint32m8_t test___riscv_vor_mu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,32); +} + + +vuint64m1_t test___riscv_vor_mu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,32); +} + + +vuint64m2_t test___riscv_vor_mu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,32); +} + + +vuint64m4_t test___riscv_vor_mu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,32); +} + + +vuint64m8_t test___riscv_vor_mu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*mu\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 8 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vor_vx_mu_rv64-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vor_vx_mu_rv64-1.C new file mode 100644 index 00000000000..4ad2c6d7787 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vor_vx_mu_rv64-1.C @@ -0,0 +1,292 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vor_mu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,vl); +} + + +vint8mf4_t test___riscv_vor_mu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,vl); +} + + +vint8mf2_t test___riscv_vor_mu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,vl); +} + + +vint8m1_t test___riscv_vor_mu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,vl); +} + + +vint8m2_t test___riscv_vor_mu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,vl); +} + + +vint8m4_t test___riscv_vor_mu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,vl); +} + + +vint8m8_t test___riscv_vor_mu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,vl); +} + + +vint16mf4_t test___riscv_vor_mu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,vl); +} + + +vint16mf2_t test___riscv_vor_mu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,vl); +} + + +vint16m1_t test___riscv_vor_mu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,vl); +} + + +vint16m2_t test___riscv_vor_mu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,vl); +} + + +vint16m4_t test___riscv_vor_mu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,vl); +} + + +vint16m8_t test___riscv_vor_mu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,vl); +} + + +vint32mf2_t test___riscv_vor_mu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,vl); +} + + +vint32m1_t test___riscv_vor_mu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,vl); +} + + +vint32m2_t test___riscv_vor_mu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,vl); +} + + +vint32m4_t test___riscv_vor_mu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,vl); +} + + +vint32m8_t test___riscv_vor_mu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,vl); +} + + +vint64m1_t test___riscv_vor_mu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,vl); +} + + +vint64m2_t test___riscv_vor_mu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,vl); +} + + +vint64m4_t test___riscv_vor_mu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,vl); +} + + +vint64m8_t test___riscv_vor_mu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,vl); +} + + +vuint8mf8_t test___riscv_vor_mu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,vl); +} + + +vuint8mf4_t test___riscv_vor_mu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,vl); +} + + +vuint8mf2_t test___riscv_vor_mu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,vl); +} + + +vuint8m1_t test___riscv_vor_mu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,vl); +} + + +vuint8m2_t test___riscv_vor_mu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,vl); +} + + +vuint8m4_t test___riscv_vor_mu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,vl); +} + + +vuint8m8_t test___riscv_vor_mu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,vl); +} + + +vuint16mf4_t test___riscv_vor_mu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,vl); +} + + +vuint16mf2_t test___riscv_vor_mu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,vl); +} + + +vuint16m1_t test___riscv_vor_mu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,vl); +} + + +vuint16m2_t test___riscv_vor_mu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,vl); +} + + +vuint16m4_t test___riscv_vor_mu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,vl); +} + + +vuint16m8_t test___riscv_vor_mu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,vl); +} + + +vuint32mf2_t test___riscv_vor_mu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,vl); +} + + +vuint32m1_t test___riscv_vor_mu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,vl); +} + + +vuint32m2_t test___riscv_vor_mu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,vl); +} + + +vuint32m4_t test___riscv_vor_mu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,vl); +} + + +vuint32m8_t test___riscv_vor_mu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,vl); +} + + +vuint64m1_t test___riscv_vor_mu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,vl); +} + + +vuint64m2_t test___riscv_vor_mu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,vl); +} + + +vuint64m4_t test___riscv_vor_mu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,vl); +} + + +vuint64m8_t test___riscv_vor_mu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*mu\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*mu\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*mu\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*mu\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*mu\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vor_vx_mu_rv64-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vor_vx_mu_rv64-2.C new file mode 100644 index 00000000000..47075c6a3a0 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vor_vx_mu_rv64-2.C @@ -0,0 +1,292 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vor_mu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,31); +} + + +vint8mf4_t test___riscv_vor_mu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,31); +} + + +vint8mf2_t test___riscv_vor_mu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,31); +} + + +vint8m1_t test___riscv_vor_mu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,31); +} + + +vint8m2_t test___riscv_vor_mu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,31); +} + + +vint8m4_t test___riscv_vor_mu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,31); +} + + +vint8m8_t test___riscv_vor_mu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,31); +} + + +vint16mf4_t test___riscv_vor_mu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,31); +} + + +vint16mf2_t test___riscv_vor_mu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,31); +} + + +vint16m1_t test___riscv_vor_mu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,31); +} + + +vint16m2_t test___riscv_vor_mu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,31); +} + + +vint16m4_t test___riscv_vor_mu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,31); +} + + +vint16m8_t test___riscv_vor_mu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,31); +} + + +vint32mf2_t test___riscv_vor_mu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,31); +} + + +vint32m1_t test___riscv_vor_mu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,31); +} + + +vint32m2_t test___riscv_vor_mu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,31); +} + + +vint32m4_t test___riscv_vor_mu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,31); +} + + +vint32m8_t test___riscv_vor_mu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,31); +} + + +vint64m1_t test___riscv_vor_mu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,31); +} + + +vint64m2_t test___riscv_vor_mu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,31); +} + + +vint64m4_t test___riscv_vor_mu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,31); +} + + +vint64m8_t test___riscv_vor_mu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,31); +} + + +vuint8mf8_t test___riscv_vor_mu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,31); +} + + +vuint8mf4_t test___riscv_vor_mu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,31); +} + + +vuint8mf2_t test___riscv_vor_mu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,31); +} + + +vuint8m1_t test___riscv_vor_mu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,31); +} + + +vuint8m2_t test___riscv_vor_mu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,31); +} + + +vuint8m4_t test___riscv_vor_mu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,31); +} + + +vuint8m8_t test___riscv_vor_mu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,31); +} + + +vuint16mf4_t test___riscv_vor_mu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,31); +} + + +vuint16mf2_t test___riscv_vor_mu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,31); +} + + +vuint16m1_t test___riscv_vor_mu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,31); +} + + +vuint16m2_t test___riscv_vor_mu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,31); +} + + +vuint16m4_t test___riscv_vor_mu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,31); +} + + +vuint16m8_t test___riscv_vor_mu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,31); +} + + +vuint32mf2_t test___riscv_vor_mu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,31); +} + + +vuint32m1_t test___riscv_vor_mu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,31); +} + + +vuint32m2_t test___riscv_vor_mu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,31); +} + + +vuint32m4_t test___riscv_vor_mu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,31); +} + + +vuint32m8_t test___riscv_vor_mu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,31); +} + + +vuint64m1_t test___riscv_vor_mu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,31); +} + + +vuint64m2_t test___riscv_vor_mu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,31); +} + + +vuint64m4_t test___riscv_vor_mu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,31); +} + + +vuint64m8_t test___riscv_vor_mu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*mu\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*mu\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*mu\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*mu\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*mu\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*mu\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*mu\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*mu\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*mu\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*mu\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*mu\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*mu\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*mu\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*mu\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*mu\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*mu\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vor_vx_mu_rv64-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vor_vx_mu_rv64-3.C new file mode 100644 index 00000000000..8c71cedba09 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vor_vx_mu_rv64-3.C @@ -0,0 +1,292 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vor_mu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,32); +} + + +vint8mf4_t test___riscv_vor_mu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,32); +} + + +vint8mf2_t test___riscv_vor_mu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,32); +} + + +vint8m1_t test___riscv_vor_mu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,32); +} + + +vint8m2_t test___riscv_vor_mu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,32); +} + + +vint8m4_t test___riscv_vor_mu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,32); +} + + +vint8m8_t test___riscv_vor_mu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,32); +} + + +vint16mf4_t test___riscv_vor_mu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,32); +} + + +vint16mf2_t test___riscv_vor_mu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,32); +} + + +vint16m1_t test___riscv_vor_mu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,32); +} + + +vint16m2_t test___riscv_vor_mu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,32); +} + + +vint16m4_t test___riscv_vor_mu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,32); +} + + +vint16m8_t test___riscv_vor_mu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,32); +} + + +vint32mf2_t test___riscv_vor_mu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,32); +} + + +vint32m1_t test___riscv_vor_mu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,32); +} + + +vint32m2_t test___riscv_vor_mu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,32); +} + + +vint32m4_t test___riscv_vor_mu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,32); +} + + +vint32m8_t test___riscv_vor_mu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,32); +} + + +vint64m1_t test___riscv_vor_mu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,32); +} + + +vint64m2_t test___riscv_vor_mu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,32); +} + + +vint64m4_t test___riscv_vor_mu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,32); +} + + +vint64m8_t test___riscv_vor_mu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,32); +} + + +vuint8mf8_t test___riscv_vor_mu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,32); +} + + +vuint8mf4_t test___riscv_vor_mu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,32); +} + + +vuint8mf2_t test___riscv_vor_mu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,32); +} + + +vuint8m1_t test___riscv_vor_mu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,32); +} + + +vuint8m2_t test___riscv_vor_mu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,32); +} + + +vuint8m4_t test___riscv_vor_mu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,32); +} + + +vuint8m8_t test___riscv_vor_mu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,32); +} + + +vuint16mf4_t test___riscv_vor_mu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,32); +} + + +vuint16mf2_t test___riscv_vor_mu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,32); +} + + +vuint16m1_t test___riscv_vor_mu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,32); +} + + +vuint16m2_t test___riscv_vor_mu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,32); +} + + +vuint16m4_t test___riscv_vor_mu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,32); +} + + +vuint16m8_t test___riscv_vor_mu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,32); +} + + +vuint32mf2_t test___riscv_vor_mu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,32); +} + + +vuint32m1_t test___riscv_vor_mu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,32); +} + + +vuint32m2_t test___riscv_vor_mu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,32); +} + + +vuint32m4_t test___riscv_vor_mu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,32); +} + + +vuint32m8_t test___riscv_vor_mu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,32); +} + + +vuint64m1_t test___riscv_vor_mu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,32); +} + + +vuint64m2_t test___riscv_vor_mu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,32); +} + + +vuint64m4_t test___riscv_vor_mu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,32); +} + + +vuint64m8_t test___riscv_vor_mu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vor_mu(mask,merge,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*mu\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*mu\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*mu\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*mu\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*mu\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vor_vx_rv32-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vor_vx_rv32-1.C new file mode 100644 index 00000000000..63e35fcd308 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vor_vx_rv32-1.C @@ -0,0 +1,572 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vor(vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,vl); +} + + +vint8mf4_t test___riscv_vor(vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,vl); +} + + +vint8mf2_t test___riscv_vor(vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,vl); +} + + +vint8m1_t test___riscv_vor(vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,vl); +} + + +vint8m2_t test___riscv_vor(vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,vl); +} + + +vint8m4_t test___riscv_vor(vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,vl); +} + + +vint8m8_t test___riscv_vor(vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,vl); +} + + +vint16mf4_t test___riscv_vor(vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,vl); +} + + +vint16mf2_t test___riscv_vor(vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,vl); +} + + +vint16m1_t test___riscv_vor(vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,vl); +} + + +vint16m2_t test___riscv_vor(vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,vl); +} + + +vint16m4_t test___riscv_vor(vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,vl); +} + + +vint16m8_t test___riscv_vor(vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,vl); +} + + +vint32mf2_t test___riscv_vor(vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,vl); +} + + +vint32m1_t test___riscv_vor(vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,vl); +} + + +vint32m2_t test___riscv_vor(vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,vl); +} + + +vint32m4_t test___riscv_vor(vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,vl); +} + + +vint32m8_t test___riscv_vor(vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,vl); +} + + +vint64m1_t test___riscv_vor(vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,vl); +} + + +vint64m2_t test___riscv_vor(vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,vl); +} + + +vint64m4_t test___riscv_vor(vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,vl); +} + + +vint64m8_t test___riscv_vor(vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,vl); +} + + +vuint8mf8_t test___riscv_vor(vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,vl); +} + + +vuint8mf4_t test___riscv_vor(vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,vl); +} + + +vuint8mf2_t test___riscv_vor(vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,vl); +} + + +vuint8m1_t test___riscv_vor(vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,vl); +} + + +vuint8m2_t test___riscv_vor(vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,vl); +} + + +vuint8m4_t test___riscv_vor(vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,vl); +} + + +vuint8m8_t test___riscv_vor(vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,vl); +} + + +vuint16mf4_t test___riscv_vor(vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,vl); +} + + +vuint16mf2_t test___riscv_vor(vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,vl); +} + + +vuint16m1_t test___riscv_vor(vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,vl); +} + + +vuint16m2_t test___riscv_vor(vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,vl); +} + + +vuint16m4_t test___riscv_vor(vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,vl); +} + + +vuint16m8_t test___riscv_vor(vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,vl); +} + + +vuint32mf2_t test___riscv_vor(vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,vl); +} + + +vuint32m1_t test___riscv_vor(vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,vl); +} + + +vuint32m2_t test___riscv_vor(vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,vl); +} + + +vuint32m4_t test___riscv_vor(vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,vl); +} + + +vuint32m8_t test___riscv_vor(vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,vl); +} + + +vuint64m1_t test___riscv_vor(vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,vl); +} + + +vuint64m2_t test___riscv_vor(vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,vl); +} + + +vuint64m4_t test___riscv_vor(vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,vl); +} + + +vuint64m8_t test___riscv_vor(vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,vl); +} + + +vint8mf8_t test___riscv_vor(vbool64_t mask,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,vl); +} + + +vint8mf4_t test___riscv_vor(vbool32_t mask,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,vl); +} + + +vint8mf2_t test___riscv_vor(vbool16_t mask,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,vl); +} + + +vint8m1_t test___riscv_vor(vbool8_t mask,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,vl); +} + + +vint8m2_t test___riscv_vor(vbool4_t mask,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,vl); +} + + +vint8m4_t test___riscv_vor(vbool2_t mask,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,vl); +} + + +vint8m8_t test___riscv_vor(vbool1_t mask,vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,vl); +} + + +vint16mf4_t test___riscv_vor(vbool64_t mask,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,vl); +} + + +vint16mf2_t test___riscv_vor(vbool32_t mask,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,vl); +} + + +vint16m1_t test___riscv_vor(vbool16_t mask,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,vl); +} + + +vint16m2_t test___riscv_vor(vbool8_t mask,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,vl); +} + + +vint16m4_t test___riscv_vor(vbool4_t mask,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,vl); +} + + +vint16m8_t test___riscv_vor(vbool2_t mask,vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,vl); +} + + +vint32mf2_t test___riscv_vor(vbool64_t mask,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,vl); +} + + +vint32m1_t test___riscv_vor(vbool32_t mask,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,vl); +} + + +vint32m2_t test___riscv_vor(vbool16_t mask,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,vl); +} + + +vint32m4_t test___riscv_vor(vbool8_t mask,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,vl); +} + + +vint32m8_t test___riscv_vor(vbool4_t mask,vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,vl); +} + + +vint64m1_t test___riscv_vor(vbool64_t mask,vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,vl); +} + + +vint64m2_t test___riscv_vor(vbool32_t mask,vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,vl); +} + + +vint64m4_t test___riscv_vor(vbool16_t mask,vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,vl); +} + + +vint64m8_t test___riscv_vor(vbool8_t mask,vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,vl); +} + + +vuint8mf8_t test___riscv_vor(vbool64_t mask,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,vl); +} + + +vuint8mf4_t test___riscv_vor(vbool32_t mask,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,vl); +} + + +vuint8mf2_t test___riscv_vor(vbool16_t mask,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,vl); +} + + +vuint8m1_t test___riscv_vor(vbool8_t mask,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,vl); +} + + +vuint8m2_t test___riscv_vor(vbool4_t mask,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,vl); +} + + +vuint8m4_t test___riscv_vor(vbool2_t mask,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,vl); +} + + +vuint8m8_t test___riscv_vor(vbool1_t mask,vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,vl); +} + + +vuint16mf4_t test___riscv_vor(vbool64_t mask,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,vl); +} + + +vuint16mf2_t test___riscv_vor(vbool32_t mask,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,vl); +} + + +vuint16m1_t test___riscv_vor(vbool16_t mask,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,vl); +} + + +vuint16m2_t test___riscv_vor(vbool8_t mask,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,vl); +} + + +vuint16m4_t test___riscv_vor(vbool4_t mask,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,vl); +} + + +vuint16m8_t test___riscv_vor(vbool2_t mask,vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,vl); +} + + +vuint32mf2_t test___riscv_vor(vbool64_t mask,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,vl); +} + + +vuint32m1_t test___riscv_vor(vbool32_t mask,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,vl); +} + + +vuint32m2_t test___riscv_vor(vbool16_t mask,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,vl); +} + + +vuint32m4_t test___riscv_vor(vbool8_t mask,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,vl); +} + + +vuint32m8_t test___riscv_vor(vbool4_t mask,vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,vl); +} + + +vuint64m1_t test___riscv_vor(vbool64_t mask,vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,vl); +} + + +vuint64m2_t test___riscv_vor(vbool32_t mask,vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,vl); +} + + +vuint64m4_t test___riscv_vor(vbool16_t mask,vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,vl); +} + + +vuint64m8_t test___riscv_vor(vbool8_t mask,vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 8 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 8 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vor_vx_rv32-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vor_vx_rv32-2.C new file mode 100644 index 00000000000..b8fbfff7fc4 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vor_vx_rv32-2.C @@ -0,0 +1,572 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vor(vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,31); +} + + +vint8mf4_t test___riscv_vor(vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,31); +} + + +vint8mf2_t test___riscv_vor(vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,31); +} + + +vint8m1_t test___riscv_vor(vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,31); +} + + +vint8m2_t test___riscv_vor(vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,31); +} + + +vint8m4_t test___riscv_vor(vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,31); +} + + +vint8m8_t test___riscv_vor(vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,31); +} + + +vint16mf4_t test___riscv_vor(vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,31); +} + + +vint16mf2_t test___riscv_vor(vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,31); +} + + +vint16m1_t test___riscv_vor(vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,31); +} + + +vint16m2_t test___riscv_vor(vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,31); +} + + +vint16m4_t test___riscv_vor(vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,31); +} + + +vint16m8_t test___riscv_vor(vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,31); +} + + +vint32mf2_t test___riscv_vor(vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,31); +} + + +vint32m1_t test___riscv_vor(vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,31); +} + + +vint32m2_t test___riscv_vor(vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,31); +} + + +vint32m4_t test___riscv_vor(vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,31); +} + + +vint32m8_t test___riscv_vor(vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,31); +} + + +vint64m1_t test___riscv_vor(vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,31); +} + + +vint64m2_t test___riscv_vor(vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,31); +} + + +vint64m4_t test___riscv_vor(vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,31); +} + + +vint64m8_t test___riscv_vor(vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,31); +} + + +vuint8mf8_t test___riscv_vor(vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,31); +} + + +vuint8mf4_t test___riscv_vor(vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,31); +} + + +vuint8mf2_t test___riscv_vor(vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,31); +} + + +vuint8m1_t test___riscv_vor(vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,31); +} + + +vuint8m2_t test___riscv_vor(vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,31); +} + + +vuint8m4_t test___riscv_vor(vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,31); +} + + +vuint8m8_t test___riscv_vor(vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,31); +} + + +vuint16mf4_t test___riscv_vor(vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,31); +} + + +vuint16mf2_t test___riscv_vor(vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,31); +} + + +vuint16m1_t test___riscv_vor(vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,31); +} + + +vuint16m2_t test___riscv_vor(vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,31); +} + + +vuint16m4_t test___riscv_vor(vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,31); +} + + +vuint16m8_t test___riscv_vor(vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,31); +} + + +vuint32mf2_t test___riscv_vor(vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,31); +} + + +vuint32m1_t test___riscv_vor(vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,31); +} + + +vuint32m2_t test___riscv_vor(vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,31); +} + + +vuint32m4_t test___riscv_vor(vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,31); +} + + +vuint32m8_t test___riscv_vor(vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,31); +} + + +vuint64m1_t test___riscv_vor(vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,31); +} + + +vuint64m2_t test___riscv_vor(vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,31); +} + + +vuint64m4_t test___riscv_vor(vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,31); +} + + +vuint64m8_t test___riscv_vor(vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,31); +} + + +vint8mf8_t test___riscv_vor(vbool64_t mask,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,31); +} + + +vint8mf4_t test___riscv_vor(vbool32_t mask,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,31); +} + + +vint8mf2_t test___riscv_vor(vbool16_t mask,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,31); +} + + +vint8m1_t test___riscv_vor(vbool8_t mask,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,31); +} + + +vint8m2_t test___riscv_vor(vbool4_t mask,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,31); +} + + +vint8m4_t test___riscv_vor(vbool2_t mask,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,31); +} + + +vint8m8_t test___riscv_vor(vbool1_t mask,vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,31); +} + + +vint16mf4_t test___riscv_vor(vbool64_t mask,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,31); +} + + +vint16mf2_t test___riscv_vor(vbool32_t mask,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,31); +} + + +vint16m1_t test___riscv_vor(vbool16_t mask,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,31); +} + + +vint16m2_t test___riscv_vor(vbool8_t mask,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,31); +} + + +vint16m4_t test___riscv_vor(vbool4_t mask,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,31); +} + + +vint16m8_t test___riscv_vor(vbool2_t mask,vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,31); +} + + +vint32mf2_t test___riscv_vor(vbool64_t mask,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,31); +} + + +vint32m1_t test___riscv_vor(vbool32_t mask,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,31); +} + + +vint32m2_t test___riscv_vor(vbool16_t mask,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,31); +} + + +vint32m4_t test___riscv_vor(vbool8_t mask,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,31); +} + + +vint32m8_t test___riscv_vor(vbool4_t mask,vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,31); +} + + +vint64m1_t test___riscv_vor(vbool64_t mask,vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,31); +} + + +vint64m2_t test___riscv_vor(vbool32_t mask,vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,31); +} + + +vint64m4_t test___riscv_vor(vbool16_t mask,vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,31); +} + + +vint64m8_t test___riscv_vor(vbool8_t mask,vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,31); +} + + +vuint8mf8_t test___riscv_vor(vbool64_t mask,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,31); +} + + +vuint8mf4_t test___riscv_vor(vbool32_t mask,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,31); +} + + +vuint8mf2_t test___riscv_vor(vbool16_t mask,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,31); +} + + +vuint8m1_t test___riscv_vor(vbool8_t mask,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,31); +} + + +vuint8m2_t test___riscv_vor(vbool4_t mask,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,31); +} + + +vuint8m4_t test___riscv_vor(vbool2_t mask,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,31); +} + + +vuint8m8_t test___riscv_vor(vbool1_t mask,vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,31); +} + + +vuint16mf4_t test___riscv_vor(vbool64_t mask,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,31); +} + + +vuint16mf2_t test___riscv_vor(vbool32_t mask,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,31); +} + + +vuint16m1_t test___riscv_vor(vbool16_t mask,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,31); +} + + +vuint16m2_t test___riscv_vor(vbool8_t mask,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,31); +} + + +vuint16m4_t test___riscv_vor(vbool4_t mask,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,31); +} + + +vuint16m8_t test___riscv_vor(vbool2_t mask,vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,31); +} + + +vuint32mf2_t test___riscv_vor(vbool64_t mask,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,31); +} + + +vuint32m1_t test___riscv_vor(vbool32_t mask,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,31); +} + + +vuint32m2_t test___riscv_vor(vbool16_t mask,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,31); +} + + +vuint32m4_t test___riscv_vor(vbool8_t mask,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,31); +} + + +vuint32m8_t test___riscv_vor(vbool4_t mask,vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,31); +} + + +vuint64m1_t test___riscv_vor(vbool64_t mask,vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,31); +} + + +vuint64m2_t test___riscv_vor(vbool32_t mask,vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,31); +} + + +vuint64m4_t test___riscv_vor(vbool16_t mask,vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,31); +} + + +vuint64m8_t test___riscv_vor(vbool8_t mask,vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 8 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 8 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vor_vx_rv32-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vor_vx_rv32-3.C new file mode 100644 index 00000000000..b65486c03db --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vor_vx_rv32-3.C @@ -0,0 +1,572 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vor(vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,32); +} + + +vint8mf4_t test___riscv_vor(vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,32); +} + + +vint8mf2_t test___riscv_vor(vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,32); +} + + +vint8m1_t test___riscv_vor(vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,32); +} + + +vint8m2_t test___riscv_vor(vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,32); +} + + +vint8m4_t test___riscv_vor(vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,32); +} + + +vint8m8_t test___riscv_vor(vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,32); +} + + +vint16mf4_t test___riscv_vor(vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,32); +} + + +vint16mf2_t test___riscv_vor(vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,32); +} + + +vint16m1_t test___riscv_vor(vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,32); +} + + +vint16m2_t test___riscv_vor(vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,32); +} + + +vint16m4_t test___riscv_vor(vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,32); +} + + +vint16m8_t test___riscv_vor(vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,32); +} + + +vint32mf2_t test___riscv_vor(vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,32); +} + + +vint32m1_t test___riscv_vor(vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,32); +} + + +vint32m2_t test___riscv_vor(vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,32); +} + + +vint32m4_t test___riscv_vor(vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,32); +} + + +vint32m8_t test___riscv_vor(vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,32); +} + + +vint64m1_t test___riscv_vor(vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,32); +} + + +vint64m2_t test___riscv_vor(vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,32); +} + + +vint64m4_t test___riscv_vor(vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,32); +} + + +vint64m8_t test___riscv_vor(vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,32); +} + + +vuint8mf8_t test___riscv_vor(vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,32); +} + + +vuint8mf4_t test___riscv_vor(vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,32); +} + + +vuint8mf2_t test___riscv_vor(vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,32); +} + + +vuint8m1_t test___riscv_vor(vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,32); +} + + +vuint8m2_t test___riscv_vor(vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,32); +} + + +vuint8m4_t test___riscv_vor(vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,32); +} + + +vuint8m8_t test___riscv_vor(vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,32); +} + + +vuint16mf4_t test___riscv_vor(vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,32); +} + + +vuint16mf2_t test___riscv_vor(vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,32); +} + + +vuint16m1_t test___riscv_vor(vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,32); +} + + +vuint16m2_t test___riscv_vor(vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,32); +} + + +vuint16m4_t test___riscv_vor(vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,32); +} + + +vuint16m8_t test___riscv_vor(vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,32); +} + + +vuint32mf2_t test___riscv_vor(vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,32); +} + + +vuint32m1_t test___riscv_vor(vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,32); +} + + +vuint32m2_t test___riscv_vor(vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,32); +} + + +vuint32m4_t test___riscv_vor(vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,32); +} + + +vuint32m8_t test___riscv_vor(vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,32); +} + + +vuint64m1_t test___riscv_vor(vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,32); +} + + +vuint64m2_t test___riscv_vor(vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,32); +} + + +vuint64m4_t test___riscv_vor(vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,32); +} + + +vuint64m8_t test___riscv_vor(vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,32); +} + + +vint8mf8_t test___riscv_vor(vbool64_t mask,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,32); +} + + +vint8mf4_t test___riscv_vor(vbool32_t mask,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,32); +} + + +vint8mf2_t test___riscv_vor(vbool16_t mask,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,32); +} + + +vint8m1_t test___riscv_vor(vbool8_t mask,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,32); +} + + +vint8m2_t test___riscv_vor(vbool4_t mask,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,32); +} + + +vint8m4_t test___riscv_vor(vbool2_t mask,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,32); +} + + +vint8m8_t test___riscv_vor(vbool1_t mask,vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,32); +} + + +vint16mf4_t test___riscv_vor(vbool64_t mask,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,32); +} + + +vint16mf2_t test___riscv_vor(vbool32_t mask,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,32); +} + + +vint16m1_t test___riscv_vor(vbool16_t mask,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,32); +} + + +vint16m2_t test___riscv_vor(vbool8_t mask,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,32); +} + + +vint16m4_t test___riscv_vor(vbool4_t mask,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,32); +} + + +vint16m8_t test___riscv_vor(vbool2_t mask,vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,32); +} + + +vint32mf2_t test___riscv_vor(vbool64_t mask,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,32); +} + + +vint32m1_t test___riscv_vor(vbool32_t mask,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,32); +} + + +vint32m2_t test___riscv_vor(vbool16_t mask,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,32); +} + + +vint32m4_t test___riscv_vor(vbool8_t mask,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,32); +} + + +vint32m8_t test___riscv_vor(vbool4_t mask,vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,32); +} + + +vint64m1_t test___riscv_vor(vbool64_t mask,vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,32); +} + + +vint64m2_t test___riscv_vor(vbool32_t mask,vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,32); +} + + +vint64m4_t test___riscv_vor(vbool16_t mask,vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,32); +} + + +vint64m8_t test___riscv_vor(vbool8_t mask,vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,32); +} + + +vuint8mf8_t test___riscv_vor(vbool64_t mask,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,32); +} + + +vuint8mf4_t test___riscv_vor(vbool32_t mask,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,32); +} + + +vuint8mf2_t test___riscv_vor(vbool16_t mask,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,32); +} + + +vuint8m1_t test___riscv_vor(vbool8_t mask,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,32); +} + + +vuint8m2_t test___riscv_vor(vbool4_t mask,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,32); +} + + +vuint8m4_t test___riscv_vor(vbool2_t mask,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,32); +} + + +vuint8m8_t test___riscv_vor(vbool1_t mask,vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,32); +} + + +vuint16mf4_t test___riscv_vor(vbool64_t mask,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,32); +} + + +vuint16mf2_t test___riscv_vor(vbool32_t mask,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,32); +} + + +vuint16m1_t test___riscv_vor(vbool16_t mask,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,32); +} + + +vuint16m2_t test___riscv_vor(vbool8_t mask,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,32); +} + + +vuint16m4_t test___riscv_vor(vbool4_t mask,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,32); +} + + +vuint16m8_t test___riscv_vor(vbool2_t mask,vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,32); +} + + +vuint32mf2_t test___riscv_vor(vbool64_t mask,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,32); +} + + +vuint32m1_t test___riscv_vor(vbool32_t mask,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,32); +} + + +vuint32m2_t test___riscv_vor(vbool16_t mask,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,32); +} + + +vuint32m4_t test___riscv_vor(vbool8_t mask,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,32); +} + + +vuint32m8_t test___riscv_vor(vbool4_t mask,vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,32); +} + + +vuint64m1_t test___riscv_vor(vbool64_t mask,vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,32); +} + + +vuint64m2_t test___riscv_vor(vbool32_t mask,vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,32); +} + + +vuint64m4_t test___riscv_vor(vbool16_t mask,vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,32); +} + + +vuint64m8_t test___riscv_vor(vbool8_t mask,vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 8 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 8 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vor_vx_rv64-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vor_vx_rv64-1.C new file mode 100644 index 00000000000..92265f636d6 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vor_vx_rv64-1.C @@ -0,0 +1,578 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vor(vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,vl); +} + + +vint8mf4_t test___riscv_vor(vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,vl); +} + + +vint8mf2_t test___riscv_vor(vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,vl); +} + + +vint8m1_t test___riscv_vor(vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,vl); +} + + +vint8m2_t test___riscv_vor(vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,vl); +} + + +vint8m4_t test___riscv_vor(vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,vl); +} + + +vint8m8_t test___riscv_vor(vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,vl); +} + + +vint16mf4_t test___riscv_vor(vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,vl); +} + + +vint16mf2_t test___riscv_vor(vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,vl); +} + + +vint16m1_t test___riscv_vor(vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,vl); +} + + +vint16m2_t test___riscv_vor(vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,vl); +} + + +vint16m4_t test___riscv_vor(vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,vl); +} + + +vint16m8_t test___riscv_vor(vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,vl); +} + + +vint32mf2_t test___riscv_vor(vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,vl); +} + + +vint32m1_t test___riscv_vor(vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,vl); +} + + +vint32m2_t test___riscv_vor(vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,vl); +} + + +vint32m4_t test___riscv_vor(vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,vl); +} + + +vint32m8_t test___riscv_vor(vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,vl); +} + + +vint64m1_t test___riscv_vor(vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,vl); +} + + +vint64m2_t test___riscv_vor(vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,vl); +} + + +vint64m4_t test___riscv_vor(vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,vl); +} + + +vint64m8_t test___riscv_vor(vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,vl); +} + + +vuint8mf8_t test___riscv_vor(vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,vl); +} + + +vuint8mf4_t test___riscv_vor(vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,vl); +} + + +vuint8mf2_t test___riscv_vor(vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,vl); +} + + +vuint8m1_t test___riscv_vor(vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,vl); +} + + +vuint8m2_t test___riscv_vor(vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,vl); +} + + +vuint8m4_t test___riscv_vor(vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,vl); +} + + +vuint8m8_t test___riscv_vor(vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,vl); +} + + +vuint16mf4_t test___riscv_vor(vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,vl); +} + + +vuint16mf2_t test___riscv_vor(vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,vl); +} + + +vuint16m1_t test___riscv_vor(vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,vl); +} + + +vuint16m2_t test___riscv_vor(vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,vl); +} + + +vuint16m4_t test___riscv_vor(vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,vl); +} + + +vuint16m8_t test___riscv_vor(vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,vl); +} + + +vuint32mf2_t test___riscv_vor(vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,vl); +} + + +vuint32m1_t test___riscv_vor(vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,vl); +} + + +vuint32m2_t test___riscv_vor(vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,vl); +} + + +vuint32m4_t test___riscv_vor(vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,vl); +} + + +vuint32m8_t test___riscv_vor(vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,vl); +} + + +vuint64m1_t test___riscv_vor(vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,vl); +} + + +vuint64m2_t test___riscv_vor(vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,vl); +} + + +vuint64m4_t test___riscv_vor(vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,vl); +} + + +vuint64m8_t test___riscv_vor(vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,vl); +} + + +vint8mf8_t test___riscv_vor(vbool64_t mask,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,vl); +} + + +vint8mf4_t test___riscv_vor(vbool32_t mask,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,vl); +} + + +vint8mf2_t test___riscv_vor(vbool16_t mask,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,vl); +} + + +vint8m1_t test___riscv_vor(vbool8_t mask,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,vl); +} + + +vint8m2_t test___riscv_vor(vbool4_t mask,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,vl); +} + + +vint8m4_t test___riscv_vor(vbool2_t mask,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,vl); +} + + +vint8m8_t test___riscv_vor(vbool1_t mask,vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,vl); +} + + +vint16mf4_t test___riscv_vor(vbool64_t mask,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,vl); +} + + +vint16mf2_t test___riscv_vor(vbool32_t mask,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,vl); +} + + +vint16m1_t test___riscv_vor(vbool16_t mask,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,vl); +} + + +vint16m2_t test___riscv_vor(vbool8_t mask,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,vl); +} + + +vint16m4_t test___riscv_vor(vbool4_t mask,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,vl); +} + + +vint16m8_t test___riscv_vor(vbool2_t mask,vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,vl); +} + + +vint32mf2_t test___riscv_vor(vbool64_t mask,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,vl); +} + + +vint32m1_t test___riscv_vor(vbool32_t mask,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,vl); +} + + +vint32m2_t test___riscv_vor(vbool16_t mask,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,vl); +} + + +vint32m4_t test___riscv_vor(vbool8_t mask,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,vl); +} + + +vint32m8_t test___riscv_vor(vbool4_t mask,vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,vl); +} + + +vint64m1_t test___riscv_vor(vbool64_t mask,vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,vl); +} + + +vint64m2_t test___riscv_vor(vbool32_t mask,vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,vl); +} + + +vint64m4_t test___riscv_vor(vbool16_t mask,vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,vl); +} + + +vint64m8_t test___riscv_vor(vbool8_t mask,vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,vl); +} + + +vuint8mf8_t test___riscv_vor(vbool64_t mask,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,vl); +} + + +vuint8mf4_t test___riscv_vor(vbool32_t mask,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,vl); +} + + +vuint8mf2_t test___riscv_vor(vbool16_t mask,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,vl); +} + + +vuint8m1_t test___riscv_vor(vbool8_t mask,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,vl); +} + + +vuint8m2_t test___riscv_vor(vbool4_t mask,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,vl); +} + + +vuint8m4_t test___riscv_vor(vbool2_t mask,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,vl); +} + + +vuint8m8_t test___riscv_vor(vbool1_t mask,vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,vl); +} + + +vuint16mf4_t test___riscv_vor(vbool64_t mask,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,vl); +} + + +vuint16mf2_t test___riscv_vor(vbool32_t mask,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,vl); +} + + +vuint16m1_t test___riscv_vor(vbool16_t mask,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,vl); +} + + +vuint16m2_t test___riscv_vor(vbool8_t mask,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,vl); +} + + +vuint16m4_t test___riscv_vor(vbool4_t mask,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,vl); +} + + +vuint16m8_t test___riscv_vor(vbool2_t mask,vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,vl); +} + + +vuint32mf2_t test___riscv_vor(vbool64_t mask,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,vl); +} + + +vuint32m1_t test___riscv_vor(vbool32_t mask,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,vl); +} + + +vuint32m2_t test___riscv_vor(vbool16_t mask,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,vl); +} + + +vuint32m4_t test___riscv_vor(vbool8_t mask,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,vl); +} + + +vuint32m8_t test___riscv_vor(vbool4_t mask,vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,vl); +} + + +vuint64m1_t test___riscv_vor(vbool64_t mask,vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,vl); +} + + +vuint64m2_t test___riscv_vor(vbool32_t mask,vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,vl); +} + + +vuint64m4_t test___riscv_vor(vbool16_t mask,vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,vl); +} + + +vuint64m8_t test___riscv_vor(vbool8_t mask,vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vor_vx_rv64-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vor_vx_rv64-2.C new file mode 100644 index 00000000000..1bbb9730054 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vor_vx_rv64-2.C @@ -0,0 +1,578 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vor(vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,31); +} + + +vint8mf4_t test___riscv_vor(vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,31); +} + + +vint8mf2_t test___riscv_vor(vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,31); +} + + +vint8m1_t test___riscv_vor(vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,31); +} + + +vint8m2_t test___riscv_vor(vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,31); +} + + +vint8m4_t test___riscv_vor(vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,31); +} + + +vint8m8_t test___riscv_vor(vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,31); +} + + +vint16mf4_t test___riscv_vor(vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,31); +} + + +vint16mf2_t test___riscv_vor(vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,31); +} + + +vint16m1_t test___riscv_vor(vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,31); +} + + +vint16m2_t test___riscv_vor(vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,31); +} + + +vint16m4_t test___riscv_vor(vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,31); +} + + +vint16m8_t test___riscv_vor(vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,31); +} + + +vint32mf2_t test___riscv_vor(vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,31); +} + + +vint32m1_t test___riscv_vor(vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,31); +} + + +vint32m2_t test___riscv_vor(vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,31); +} + + +vint32m4_t test___riscv_vor(vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,31); +} + + +vint32m8_t test___riscv_vor(vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,31); +} + + +vint64m1_t test___riscv_vor(vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,31); +} + + +vint64m2_t test___riscv_vor(vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,31); +} + + +vint64m4_t test___riscv_vor(vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,31); +} + + +vint64m8_t test___riscv_vor(vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,31); +} + + +vuint8mf8_t test___riscv_vor(vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,31); +} + + +vuint8mf4_t test___riscv_vor(vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,31); +} + + +vuint8mf2_t test___riscv_vor(vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,31); +} + + +vuint8m1_t test___riscv_vor(vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,31); +} + + +vuint8m2_t test___riscv_vor(vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,31); +} + + +vuint8m4_t test___riscv_vor(vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,31); +} + + +vuint8m8_t test___riscv_vor(vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,31); +} + + +vuint16mf4_t test___riscv_vor(vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,31); +} + + +vuint16mf2_t test___riscv_vor(vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,31); +} + + +vuint16m1_t test___riscv_vor(vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,31); +} + + +vuint16m2_t test___riscv_vor(vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,31); +} + + +vuint16m4_t test___riscv_vor(vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,31); +} + + +vuint16m8_t test___riscv_vor(vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,31); +} + + +vuint32mf2_t test___riscv_vor(vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,31); +} + + +vuint32m1_t test___riscv_vor(vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,31); +} + + +vuint32m2_t test___riscv_vor(vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,31); +} + + +vuint32m4_t test___riscv_vor(vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,31); +} + + +vuint32m8_t test___riscv_vor(vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,31); +} + + +vuint64m1_t test___riscv_vor(vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,31); +} + + +vuint64m2_t test___riscv_vor(vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,31); +} + + +vuint64m4_t test___riscv_vor(vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,31); +} + + +vuint64m8_t test___riscv_vor(vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,31); +} + + +vint8mf8_t test___riscv_vor(vbool64_t mask,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,31); +} + + +vint8mf4_t test___riscv_vor(vbool32_t mask,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,31); +} + + +vint8mf2_t test___riscv_vor(vbool16_t mask,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,31); +} + + +vint8m1_t test___riscv_vor(vbool8_t mask,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,31); +} + + +vint8m2_t test___riscv_vor(vbool4_t mask,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,31); +} + + +vint8m4_t test___riscv_vor(vbool2_t mask,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,31); +} + + +vint8m8_t test___riscv_vor(vbool1_t mask,vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,31); +} + + +vint16mf4_t test___riscv_vor(vbool64_t mask,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,31); +} + + +vint16mf2_t test___riscv_vor(vbool32_t mask,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,31); +} + + +vint16m1_t test___riscv_vor(vbool16_t mask,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,31); +} + + +vint16m2_t test___riscv_vor(vbool8_t mask,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,31); +} + + +vint16m4_t test___riscv_vor(vbool4_t mask,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,31); +} + + +vint16m8_t test___riscv_vor(vbool2_t mask,vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,31); +} + + +vint32mf2_t test___riscv_vor(vbool64_t mask,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,31); +} + + +vint32m1_t test___riscv_vor(vbool32_t mask,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,31); +} + + +vint32m2_t test___riscv_vor(vbool16_t mask,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,31); +} + + +vint32m4_t test___riscv_vor(vbool8_t mask,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,31); +} + + +vint32m8_t test___riscv_vor(vbool4_t mask,vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,31); +} + + +vint64m1_t test___riscv_vor(vbool64_t mask,vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,31); +} + + +vint64m2_t test___riscv_vor(vbool32_t mask,vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,31); +} + + +vint64m4_t test___riscv_vor(vbool16_t mask,vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,31); +} + + +vint64m8_t test___riscv_vor(vbool8_t mask,vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,31); +} + + +vuint8mf8_t test___riscv_vor(vbool64_t mask,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,31); +} + + +vuint8mf4_t test___riscv_vor(vbool32_t mask,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,31); +} + + +vuint8mf2_t test___riscv_vor(vbool16_t mask,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,31); +} + + +vuint8m1_t test___riscv_vor(vbool8_t mask,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,31); +} + + +vuint8m2_t test___riscv_vor(vbool4_t mask,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,31); +} + + +vuint8m4_t test___riscv_vor(vbool2_t mask,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,31); +} + + +vuint8m8_t test___riscv_vor(vbool1_t mask,vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,31); +} + + +vuint16mf4_t test___riscv_vor(vbool64_t mask,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,31); +} + + +vuint16mf2_t test___riscv_vor(vbool32_t mask,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,31); +} + + +vuint16m1_t test___riscv_vor(vbool16_t mask,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,31); +} + + +vuint16m2_t test___riscv_vor(vbool8_t mask,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,31); +} + + +vuint16m4_t test___riscv_vor(vbool4_t mask,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,31); +} + + +vuint16m8_t test___riscv_vor(vbool2_t mask,vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,31); +} + + +vuint32mf2_t test___riscv_vor(vbool64_t mask,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,31); +} + + +vuint32m1_t test___riscv_vor(vbool32_t mask,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,31); +} + + +vuint32m2_t test___riscv_vor(vbool16_t mask,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,31); +} + + +vuint32m4_t test___riscv_vor(vbool8_t mask,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,31); +} + + +vuint32m8_t test___riscv_vor(vbool4_t mask,vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,31); +} + + +vuint64m1_t test___riscv_vor(vbool64_t mask,vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,31); +} + + +vuint64m2_t test___riscv_vor(vbool32_t mask,vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,31); +} + + +vuint64m4_t test___riscv_vor(vbool16_t mask,vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,31); +} + + +vuint64m8_t test___riscv_vor(vbool8_t mask,vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vor_vx_rv64-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vor_vx_rv64-3.C new file mode 100644 index 00000000000..19d178efc75 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vor_vx_rv64-3.C @@ -0,0 +1,578 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vor(vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,32); +} + + +vint8mf4_t test___riscv_vor(vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,32); +} + + +vint8mf2_t test___riscv_vor(vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,32); +} + + +vint8m1_t test___riscv_vor(vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,32); +} + + +vint8m2_t test___riscv_vor(vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,32); +} + + +vint8m4_t test___riscv_vor(vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,32); +} + + +vint8m8_t test___riscv_vor(vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,32); +} + + +vint16mf4_t test___riscv_vor(vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,32); +} + + +vint16mf2_t test___riscv_vor(vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,32); +} + + +vint16m1_t test___riscv_vor(vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,32); +} + + +vint16m2_t test___riscv_vor(vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,32); +} + + +vint16m4_t test___riscv_vor(vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,32); +} + + +vint16m8_t test___riscv_vor(vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,32); +} + + +vint32mf2_t test___riscv_vor(vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,32); +} + + +vint32m1_t test___riscv_vor(vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,32); +} + + +vint32m2_t test___riscv_vor(vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,32); +} + + +vint32m4_t test___riscv_vor(vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,32); +} + + +vint32m8_t test___riscv_vor(vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,32); +} + + +vint64m1_t test___riscv_vor(vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,32); +} + + +vint64m2_t test___riscv_vor(vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,32); +} + + +vint64m4_t test___riscv_vor(vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,32); +} + + +vint64m8_t test___riscv_vor(vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,32); +} + + +vuint8mf8_t test___riscv_vor(vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,32); +} + + +vuint8mf4_t test___riscv_vor(vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,32); +} + + +vuint8mf2_t test___riscv_vor(vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,32); +} + + +vuint8m1_t test___riscv_vor(vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,32); +} + + +vuint8m2_t test___riscv_vor(vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,32); +} + + +vuint8m4_t test___riscv_vor(vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,32); +} + + +vuint8m8_t test___riscv_vor(vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,32); +} + + +vuint16mf4_t test___riscv_vor(vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,32); +} + + +vuint16mf2_t test___riscv_vor(vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,32); +} + + +vuint16m1_t test___riscv_vor(vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,32); +} + + +vuint16m2_t test___riscv_vor(vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,32); +} + + +vuint16m4_t test___riscv_vor(vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,32); +} + + +vuint16m8_t test___riscv_vor(vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,32); +} + + +vuint32mf2_t test___riscv_vor(vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,32); +} + + +vuint32m1_t test___riscv_vor(vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,32); +} + + +vuint32m2_t test___riscv_vor(vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,32); +} + + +vuint32m4_t test___riscv_vor(vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,32); +} + + +vuint32m8_t test___riscv_vor(vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,32); +} + + +vuint64m1_t test___riscv_vor(vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,32); +} + + +vuint64m2_t test___riscv_vor(vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,32); +} + + +vuint64m4_t test___riscv_vor(vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,32); +} + + +vuint64m8_t test___riscv_vor(vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vor(op1,op2,32); +} + + +vint8mf8_t test___riscv_vor(vbool64_t mask,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,32); +} + + +vint8mf4_t test___riscv_vor(vbool32_t mask,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,32); +} + + +vint8mf2_t test___riscv_vor(vbool16_t mask,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,32); +} + + +vint8m1_t test___riscv_vor(vbool8_t mask,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,32); +} + + +vint8m2_t test___riscv_vor(vbool4_t mask,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,32); +} + + +vint8m4_t test___riscv_vor(vbool2_t mask,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,32); +} + + +vint8m8_t test___riscv_vor(vbool1_t mask,vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,32); +} + + +vint16mf4_t test___riscv_vor(vbool64_t mask,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,32); +} + + +vint16mf2_t test___riscv_vor(vbool32_t mask,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,32); +} + + +vint16m1_t test___riscv_vor(vbool16_t mask,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,32); +} + + +vint16m2_t test___riscv_vor(vbool8_t mask,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,32); +} + + +vint16m4_t test___riscv_vor(vbool4_t mask,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,32); +} + + +vint16m8_t test___riscv_vor(vbool2_t mask,vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,32); +} + + +vint32mf2_t test___riscv_vor(vbool64_t mask,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,32); +} + + +vint32m1_t test___riscv_vor(vbool32_t mask,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,32); +} + + +vint32m2_t test___riscv_vor(vbool16_t mask,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,32); +} + + +vint32m4_t test___riscv_vor(vbool8_t mask,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,32); +} + + +vint32m8_t test___riscv_vor(vbool4_t mask,vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,32); +} + + +vint64m1_t test___riscv_vor(vbool64_t mask,vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,32); +} + + +vint64m2_t test___riscv_vor(vbool32_t mask,vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,32); +} + + +vint64m4_t test___riscv_vor(vbool16_t mask,vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,32); +} + + +vint64m8_t test___riscv_vor(vbool8_t mask,vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,32); +} + + +vuint8mf8_t test___riscv_vor(vbool64_t mask,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,32); +} + + +vuint8mf4_t test___riscv_vor(vbool32_t mask,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,32); +} + + +vuint8mf2_t test___riscv_vor(vbool16_t mask,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,32); +} + + +vuint8m1_t test___riscv_vor(vbool8_t mask,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,32); +} + + +vuint8m2_t test___riscv_vor(vbool4_t mask,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,32); +} + + +vuint8m4_t test___riscv_vor(vbool2_t mask,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,32); +} + + +vuint8m8_t test___riscv_vor(vbool1_t mask,vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,32); +} + + +vuint16mf4_t test___riscv_vor(vbool64_t mask,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,32); +} + + +vuint16mf2_t test___riscv_vor(vbool32_t mask,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,32); +} + + +vuint16m1_t test___riscv_vor(vbool16_t mask,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,32); +} + + +vuint16m2_t test___riscv_vor(vbool8_t mask,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,32); +} + + +vuint16m4_t test___riscv_vor(vbool4_t mask,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,32); +} + + +vuint16m8_t test___riscv_vor(vbool2_t mask,vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,32); +} + + +vuint32mf2_t test___riscv_vor(vbool64_t mask,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,32); +} + + +vuint32m1_t test___riscv_vor(vbool32_t mask,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,32); +} + + +vuint32m2_t test___riscv_vor(vbool16_t mask,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,32); +} + + +vuint32m4_t test___riscv_vor(vbool8_t mask,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,32); +} + + +vuint32m8_t test___riscv_vor(vbool4_t mask,vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,32); +} + + +vuint64m1_t test___riscv_vor(vbool64_t mask,vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,32); +} + + +vuint64m2_t test___riscv_vor(vbool32_t mask,vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,32); +} + + +vuint64m4_t test___riscv_vor(vbool16_t mask,vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,32); +} + + +vuint64m8_t test___riscv_vor(vbool8_t mask,vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vor(mask,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vor_vx_tu_rv32-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vor_vx_tu_rv32-1.C new file mode 100644 index 00000000000..2d405e915b4 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vor_vx_tu_rv32-1.C @@ -0,0 +1,289 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vor_tu(vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,vl); +} + + +vint8mf4_t test___riscv_vor_tu(vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,vl); +} + + +vint8mf2_t test___riscv_vor_tu(vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,vl); +} + + +vint8m1_t test___riscv_vor_tu(vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,vl); +} + + +vint8m2_t test___riscv_vor_tu(vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,vl); +} + + +vint8m4_t test___riscv_vor_tu(vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,vl); +} + + +vint8m8_t test___riscv_vor_tu(vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,vl); +} + + +vint16mf4_t test___riscv_vor_tu(vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,vl); +} + + +vint16mf2_t test___riscv_vor_tu(vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,vl); +} + + +vint16m1_t test___riscv_vor_tu(vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,vl); +} + + +vint16m2_t test___riscv_vor_tu(vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,vl); +} + + +vint16m4_t test___riscv_vor_tu(vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,vl); +} + + +vint16m8_t test___riscv_vor_tu(vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,vl); +} + + +vint32mf2_t test___riscv_vor_tu(vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,vl); +} + + +vint32m1_t test___riscv_vor_tu(vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,vl); +} + + +vint32m2_t test___riscv_vor_tu(vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,vl); +} + + +vint32m4_t test___riscv_vor_tu(vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,vl); +} + + +vint32m8_t test___riscv_vor_tu(vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,vl); +} + + +vint64m1_t test___riscv_vor_tu(vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,vl); +} + + +vint64m2_t test___riscv_vor_tu(vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,vl); +} + + +vint64m4_t test___riscv_vor_tu(vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,vl); +} + + +vint64m8_t test___riscv_vor_tu(vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,vl); +} + + +vuint8mf8_t test___riscv_vor_tu(vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,vl); +} + + +vuint8mf4_t test___riscv_vor_tu(vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,vl); +} + + +vuint8mf2_t test___riscv_vor_tu(vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,vl); +} + + +vuint8m1_t test___riscv_vor_tu(vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,vl); +} + + +vuint8m2_t test___riscv_vor_tu(vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,vl); +} + + +vuint8m4_t test___riscv_vor_tu(vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,vl); +} + + +vuint8m8_t test___riscv_vor_tu(vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,vl); +} + + +vuint16mf4_t test___riscv_vor_tu(vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,vl); +} + + +vuint16mf2_t test___riscv_vor_tu(vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,vl); +} + + +vuint16m1_t test___riscv_vor_tu(vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,vl); +} + + +vuint16m2_t test___riscv_vor_tu(vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,vl); +} + + +vuint16m4_t test___riscv_vor_tu(vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,vl); +} + + +vuint16m8_t test___riscv_vor_tu(vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,vl); +} + + +vuint32mf2_t test___riscv_vor_tu(vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,vl); +} + + +vuint32m1_t test___riscv_vor_tu(vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,vl); +} + + +vuint32m2_t test___riscv_vor_tu(vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,vl); +} + + +vuint32m4_t test___riscv_vor_tu(vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,vl); +} + + +vuint32m8_t test___riscv_vor_tu(vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,vl); +} + + +vuint64m1_t test___riscv_vor_tu(vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,vl); +} + + +vuint64m2_t test___riscv_vor_tu(vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,vl); +} + + +vuint64m4_t test___riscv_vor_tu(vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,vl); +} + + +vuint64m8_t test___riscv_vor_tu(vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 8 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vor_vx_tu_rv32-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vor_vx_tu_rv32-2.C new file mode 100644 index 00000000000..83123df8140 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vor_vx_tu_rv32-2.C @@ -0,0 +1,289 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vor_tu(vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,31); +} + + +vint8mf4_t test___riscv_vor_tu(vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,31); +} + + +vint8mf2_t test___riscv_vor_tu(vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,31); +} + + +vint8m1_t test___riscv_vor_tu(vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,31); +} + + +vint8m2_t test___riscv_vor_tu(vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,31); +} + + +vint8m4_t test___riscv_vor_tu(vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,31); +} + + +vint8m8_t test___riscv_vor_tu(vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,31); +} + + +vint16mf4_t test___riscv_vor_tu(vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,31); +} + + +vint16mf2_t test___riscv_vor_tu(vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,31); +} + + +vint16m1_t test___riscv_vor_tu(vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,31); +} + + +vint16m2_t test___riscv_vor_tu(vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,31); +} + + +vint16m4_t test___riscv_vor_tu(vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,31); +} + + +vint16m8_t test___riscv_vor_tu(vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,31); +} + + +vint32mf2_t test___riscv_vor_tu(vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,31); +} + + +vint32m1_t test___riscv_vor_tu(vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,31); +} + + +vint32m2_t test___riscv_vor_tu(vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,31); +} + + +vint32m4_t test___riscv_vor_tu(vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,31); +} + + +vint32m8_t test___riscv_vor_tu(vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,31); +} + + +vint64m1_t test___riscv_vor_tu(vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,31); +} + + +vint64m2_t test___riscv_vor_tu(vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,31); +} + + +vint64m4_t test___riscv_vor_tu(vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,31); +} + + +vint64m8_t test___riscv_vor_tu(vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,31); +} + + +vuint8mf8_t test___riscv_vor_tu(vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,31); +} + + +vuint8mf4_t test___riscv_vor_tu(vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,31); +} + + +vuint8mf2_t test___riscv_vor_tu(vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,31); +} + + +vuint8m1_t test___riscv_vor_tu(vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,31); +} + + +vuint8m2_t test___riscv_vor_tu(vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,31); +} + + +vuint8m4_t test___riscv_vor_tu(vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,31); +} + + +vuint8m8_t test___riscv_vor_tu(vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,31); +} + + +vuint16mf4_t test___riscv_vor_tu(vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,31); +} + + +vuint16mf2_t test___riscv_vor_tu(vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,31); +} + + +vuint16m1_t test___riscv_vor_tu(vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,31); +} + + +vuint16m2_t test___riscv_vor_tu(vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,31); +} + + +vuint16m4_t test___riscv_vor_tu(vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,31); +} + + +vuint16m8_t test___riscv_vor_tu(vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,31); +} + + +vuint32mf2_t test___riscv_vor_tu(vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,31); +} + + +vuint32m1_t test___riscv_vor_tu(vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,31); +} + + +vuint32m2_t test___riscv_vor_tu(vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,31); +} + + +vuint32m4_t test___riscv_vor_tu(vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,31); +} + + +vuint32m8_t test___riscv_vor_tu(vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,31); +} + + +vuint64m1_t test___riscv_vor_tu(vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,31); +} + + +vuint64m2_t test___riscv_vor_tu(vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,31); +} + + +vuint64m4_t test___riscv_vor_tu(vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,31); +} + + +vuint64m8_t test___riscv_vor_tu(vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 8 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vor_vx_tu_rv32-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vor_vx_tu_rv32-3.C new file mode 100644 index 00000000000..30568678e37 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vor_vx_tu_rv32-3.C @@ -0,0 +1,289 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vor_tu(vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,32); +} + + +vint8mf4_t test___riscv_vor_tu(vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,32); +} + + +vint8mf2_t test___riscv_vor_tu(vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,32); +} + + +vint8m1_t test___riscv_vor_tu(vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,32); +} + + +vint8m2_t test___riscv_vor_tu(vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,32); +} + + +vint8m4_t test___riscv_vor_tu(vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,32); +} + + +vint8m8_t test___riscv_vor_tu(vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,32); +} + + +vint16mf4_t test___riscv_vor_tu(vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,32); +} + + +vint16mf2_t test___riscv_vor_tu(vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,32); +} + + +vint16m1_t test___riscv_vor_tu(vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,32); +} + + +vint16m2_t test___riscv_vor_tu(vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,32); +} + + +vint16m4_t test___riscv_vor_tu(vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,32); +} + + +vint16m8_t test___riscv_vor_tu(vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,32); +} + + +vint32mf2_t test___riscv_vor_tu(vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,32); +} + + +vint32m1_t test___riscv_vor_tu(vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,32); +} + + +vint32m2_t test___riscv_vor_tu(vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,32); +} + + +vint32m4_t test___riscv_vor_tu(vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,32); +} + + +vint32m8_t test___riscv_vor_tu(vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,32); +} + + +vint64m1_t test___riscv_vor_tu(vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,32); +} + + +vint64m2_t test___riscv_vor_tu(vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,32); +} + + +vint64m4_t test___riscv_vor_tu(vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,32); +} + + +vint64m8_t test___riscv_vor_tu(vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,32); +} + + +vuint8mf8_t test___riscv_vor_tu(vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,32); +} + + +vuint8mf4_t test___riscv_vor_tu(vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,32); +} + + +vuint8mf2_t test___riscv_vor_tu(vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,32); +} + + +vuint8m1_t test___riscv_vor_tu(vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,32); +} + + +vuint8m2_t test___riscv_vor_tu(vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,32); +} + + +vuint8m4_t test___riscv_vor_tu(vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,32); +} + + +vuint8m8_t test___riscv_vor_tu(vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,32); +} + + +vuint16mf4_t test___riscv_vor_tu(vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,32); +} + + +vuint16mf2_t test___riscv_vor_tu(vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,32); +} + + +vuint16m1_t test___riscv_vor_tu(vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,32); +} + + +vuint16m2_t test___riscv_vor_tu(vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,32); +} + + +vuint16m4_t test___riscv_vor_tu(vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,32); +} + + +vuint16m8_t test___riscv_vor_tu(vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,32); +} + + +vuint32mf2_t test___riscv_vor_tu(vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,32); +} + + +vuint32m1_t test___riscv_vor_tu(vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,32); +} + + +vuint32m2_t test___riscv_vor_tu(vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,32); +} + + +vuint32m4_t test___riscv_vor_tu(vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,32); +} + + +vuint32m8_t test___riscv_vor_tu(vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,32); +} + + +vuint64m1_t test___riscv_vor_tu(vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,32); +} + + +vuint64m2_t test___riscv_vor_tu(vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,32); +} + + +vuint64m4_t test___riscv_vor_tu(vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,32); +} + + +vuint64m8_t test___riscv_vor_tu(vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 8 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vor_vx_tu_rv64-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vor_vx_tu_rv64-1.C new file mode 100644 index 00000000000..2ecff8da082 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vor_vx_tu_rv64-1.C @@ -0,0 +1,292 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vor_tu(vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,vl); +} + + +vint8mf4_t test___riscv_vor_tu(vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,vl); +} + + +vint8mf2_t test___riscv_vor_tu(vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,vl); +} + + +vint8m1_t test___riscv_vor_tu(vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,vl); +} + + +vint8m2_t test___riscv_vor_tu(vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,vl); +} + + +vint8m4_t test___riscv_vor_tu(vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,vl); +} + + +vint8m8_t test___riscv_vor_tu(vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,vl); +} + + +vint16mf4_t test___riscv_vor_tu(vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,vl); +} + + +vint16mf2_t test___riscv_vor_tu(vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,vl); +} + + +vint16m1_t test___riscv_vor_tu(vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,vl); +} + + +vint16m2_t test___riscv_vor_tu(vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,vl); +} + + +vint16m4_t test___riscv_vor_tu(vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,vl); +} + + +vint16m8_t test___riscv_vor_tu(vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,vl); +} + + +vint32mf2_t test___riscv_vor_tu(vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,vl); +} + + +vint32m1_t test___riscv_vor_tu(vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,vl); +} + + +vint32m2_t test___riscv_vor_tu(vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,vl); +} + + +vint32m4_t test___riscv_vor_tu(vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,vl); +} + + +vint32m8_t test___riscv_vor_tu(vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,vl); +} + + +vint64m1_t test___riscv_vor_tu(vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,vl); +} + + +vint64m2_t test___riscv_vor_tu(vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,vl); +} + + +vint64m4_t test___riscv_vor_tu(vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,vl); +} + + +vint64m8_t test___riscv_vor_tu(vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,vl); +} + + +vuint8mf8_t test___riscv_vor_tu(vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,vl); +} + + +vuint8mf4_t test___riscv_vor_tu(vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,vl); +} + + +vuint8mf2_t test___riscv_vor_tu(vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,vl); +} + + +vuint8m1_t test___riscv_vor_tu(vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,vl); +} + + +vuint8m2_t test___riscv_vor_tu(vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,vl); +} + + +vuint8m4_t test___riscv_vor_tu(vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,vl); +} + + +vuint8m8_t test___riscv_vor_tu(vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,vl); +} + + +vuint16mf4_t test___riscv_vor_tu(vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,vl); +} + + +vuint16mf2_t test___riscv_vor_tu(vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,vl); +} + + +vuint16m1_t test___riscv_vor_tu(vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,vl); +} + + +vuint16m2_t test___riscv_vor_tu(vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,vl); +} + + +vuint16m4_t test___riscv_vor_tu(vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,vl); +} + + +vuint16m8_t test___riscv_vor_tu(vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,vl); +} + + +vuint32mf2_t test___riscv_vor_tu(vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,vl); +} + + +vuint32m1_t test___riscv_vor_tu(vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,vl); +} + + +vuint32m2_t test___riscv_vor_tu(vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,vl); +} + + +vuint32m4_t test___riscv_vor_tu(vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,vl); +} + + +vuint32m8_t test___riscv_vor_tu(vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,vl); +} + + +vuint64m1_t test___riscv_vor_tu(vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,vl); +} + + +vuint64m2_t test___riscv_vor_tu(vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,vl); +} + + +vuint64m4_t test___riscv_vor_tu(vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,vl); +} + + +vuint64m8_t test___riscv_vor_tu(vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vor_vx_tu_rv64-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vor_vx_tu_rv64-2.C new file mode 100644 index 00000000000..582bff3cf09 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vor_vx_tu_rv64-2.C @@ -0,0 +1,292 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vor_tu(vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,31); +} + + +vint8mf4_t test___riscv_vor_tu(vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,31); +} + + +vint8mf2_t test___riscv_vor_tu(vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,31); +} + + +vint8m1_t test___riscv_vor_tu(vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,31); +} + + +vint8m2_t test___riscv_vor_tu(vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,31); +} + + +vint8m4_t test___riscv_vor_tu(vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,31); +} + + +vint8m8_t test___riscv_vor_tu(vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,31); +} + + +vint16mf4_t test___riscv_vor_tu(vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,31); +} + + +vint16mf2_t test___riscv_vor_tu(vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,31); +} + + +vint16m1_t test___riscv_vor_tu(vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,31); +} + + +vint16m2_t test___riscv_vor_tu(vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,31); +} + + +vint16m4_t test___riscv_vor_tu(vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,31); +} + + +vint16m8_t test___riscv_vor_tu(vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,31); +} + + +vint32mf2_t test___riscv_vor_tu(vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,31); +} + + +vint32m1_t test___riscv_vor_tu(vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,31); +} + + +vint32m2_t test___riscv_vor_tu(vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,31); +} + + +vint32m4_t test___riscv_vor_tu(vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,31); +} + + +vint32m8_t test___riscv_vor_tu(vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,31); +} + + +vint64m1_t test___riscv_vor_tu(vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,31); +} + + +vint64m2_t test___riscv_vor_tu(vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,31); +} + + +vint64m4_t test___riscv_vor_tu(vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,31); +} + + +vint64m8_t test___riscv_vor_tu(vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,31); +} + + +vuint8mf8_t test___riscv_vor_tu(vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,31); +} + + +vuint8mf4_t test___riscv_vor_tu(vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,31); +} + + +vuint8mf2_t test___riscv_vor_tu(vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,31); +} + + +vuint8m1_t test___riscv_vor_tu(vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,31); +} + + +vuint8m2_t test___riscv_vor_tu(vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,31); +} + + +vuint8m4_t test___riscv_vor_tu(vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,31); +} + + +vuint8m8_t test___riscv_vor_tu(vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,31); +} + + +vuint16mf4_t test___riscv_vor_tu(vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,31); +} + + +vuint16mf2_t test___riscv_vor_tu(vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,31); +} + + +vuint16m1_t test___riscv_vor_tu(vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,31); +} + + +vuint16m2_t test___riscv_vor_tu(vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,31); +} + + +vuint16m4_t test___riscv_vor_tu(vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,31); +} + + +vuint16m8_t test___riscv_vor_tu(vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,31); +} + + +vuint32mf2_t test___riscv_vor_tu(vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,31); +} + + +vuint32m1_t test___riscv_vor_tu(vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,31); +} + + +vuint32m2_t test___riscv_vor_tu(vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,31); +} + + +vuint32m4_t test___riscv_vor_tu(vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,31); +} + + +vuint32m8_t test___riscv_vor_tu(vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,31); +} + + +vuint64m1_t test___riscv_vor_tu(vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,31); +} + + +vuint64m2_t test___riscv_vor_tu(vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,31); +} + + +vuint64m4_t test___riscv_vor_tu(vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,31); +} + + +vuint64m8_t test___riscv_vor_tu(vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vor_vx_tu_rv64-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vor_vx_tu_rv64-3.C new file mode 100644 index 00000000000..38b6f47fcbb --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vor_vx_tu_rv64-3.C @@ -0,0 +1,292 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vor_tu(vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,32); +} + + +vint8mf4_t test___riscv_vor_tu(vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,32); +} + + +vint8mf2_t test___riscv_vor_tu(vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,32); +} + + +vint8m1_t test___riscv_vor_tu(vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,32); +} + + +vint8m2_t test___riscv_vor_tu(vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,32); +} + + +vint8m4_t test___riscv_vor_tu(vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,32); +} + + +vint8m8_t test___riscv_vor_tu(vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,32); +} + + +vint16mf4_t test___riscv_vor_tu(vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,32); +} + + +vint16mf2_t test___riscv_vor_tu(vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,32); +} + + +vint16m1_t test___riscv_vor_tu(vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,32); +} + + +vint16m2_t test___riscv_vor_tu(vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,32); +} + + +vint16m4_t test___riscv_vor_tu(vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,32); +} + + +vint16m8_t test___riscv_vor_tu(vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,32); +} + + +vint32mf2_t test___riscv_vor_tu(vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,32); +} + + +vint32m1_t test___riscv_vor_tu(vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,32); +} + + +vint32m2_t test___riscv_vor_tu(vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,32); +} + + +vint32m4_t test___riscv_vor_tu(vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,32); +} + + +vint32m8_t test___riscv_vor_tu(vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,32); +} + + +vint64m1_t test___riscv_vor_tu(vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,32); +} + + +vint64m2_t test___riscv_vor_tu(vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,32); +} + + +vint64m4_t test___riscv_vor_tu(vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,32); +} + + +vint64m8_t test___riscv_vor_tu(vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,32); +} + + +vuint8mf8_t test___riscv_vor_tu(vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,32); +} + + +vuint8mf4_t test___riscv_vor_tu(vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,32); +} + + +vuint8mf2_t test___riscv_vor_tu(vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,32); +} + + +vuint8m1_t test___riscv_vor_tu(vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,32); +} + + +vuint8m2_t test___riscv_vor_tu(vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,32); +} + + +vuint8m4_t test___riscv_vor_tu(vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,32); +} + + +vuint8m8_t test___riscv_vor_tu(vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,32); +} + + +vuint16mf4_t test___riscv_vor_tu(vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,32); +} + + +vuint16mf2_t test___riscv_vor_tu(vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,32); +} + + +vuint16m1_t test___riscv_vor_tu(vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,32); +} + + +vuint16m2_t test___riscv_vor_tu(vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,32); +} + + +vuint16m4_t test___riscv_vor_tu(vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,32); +} + + +vuint16m8_t test___riscv_vor_tu(vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,32); +} + + +vuint32mf2_t test___riscv_vor_tu(vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,32); +} + + +vuint32m1_t test___riscv_vor_tu(vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,32); +} + + +vuint32m2_t test___riscv_vor_tu(vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,32); +} + + +vuint32m4_t test___riscv_vor_tu(vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,32); +} + + +vuint32m8_t test___riscv_vor_tu(vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,32); +} + + +vuint64m1_t test___riscv_vor_tu(vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,32); +} + + +vuint64m2_t test___riscv_vor_tu(vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,32); +} + + +vuint64m4_t test___riscv_vor_tu(vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,32); +} + + +vuint64m8_t test___riscv_vor_tu(vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vor_tu(merge,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vor_vx_tum_rv32-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vor_vx_tum_rv32-1.C new file mode 100644 index 00000000000..9cdd93277b2 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vor_vx_tum_rv32-1.C @@ -0,0 +1,289 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vor_tum(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,vl); +} + + +vint8mf4_t test___riscv_vor_tum(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,vl); +} + + +vint8mf2_t test___riscv_vor_tum(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,vl); +} + + +vint8m1_t test___riscv_vor_tum(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,vl); +} + + +vint8m2_t test___riscv_vor_tum(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,vl); +} + + +vint8m4_t test___riscv_vor_tum(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,vl); +} + + +vint8m8_t test___riscv_vor_tum(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,vl); +} + + +vint16mf4_t test___riscv_vor_tum(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,vl); +} + + +vint16mf2_t test___riscv_vor_tum(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,vl); +} + + +vint16m1_t test___riscv_vor_tum(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,vl); +} + + +vint16m2_t test___riscv_vor_tum(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,vl); +} + + +vint16m4_t test___riscv_vor_tum(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,vl); +} + + +vint16m8_t test___riscv_vor_tum(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,vl); +} + + +vint32mf2_t test___riscv_vor_tum(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,vl); +} + + +vint32m1_t test___riscv_vor_tum(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,vl); +} + + +vint32m2_t test___riscv_vor_tum(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,vl); +} + + +vint32m4_t test___riscv_vor_tum(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,vl); +} + + +vint32m8_t test___riscv_vor_tum(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,vl); +} + + +vint64m1_t test___riscv_vor_tum(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,vl); +} + + +vint64m2_t test___riscv_vor_tum(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,vl); +} + + +vint64m4_t test___riscv_vor_tum(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,vl); +} + + +vint64m8_t test___riscv_vor_tum(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,vl); +} + + +vuint8mf8_t test___riscv_vor_tum(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,vl); +} + + +vuint8mf4_t test___riscv_vor_tum(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,vl); +} + + +vuint8mf2_t test___riscv_vor_tum(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,vl); +} + + +vuint8m1_t test___riscv_vor_tum(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,vl); +} + + +vuint8m2_t test___riscv_vor_tum(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,vl); +} + + +vuint8m4_t test___riscv_vor_tum(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,vl); +} + + +vuint8m8_t test___riscv_vor_tum(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,vl); +} + + +vuint16mf4_t test___riscv_vor_tum(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,vl); +} + + +vuint16mf2_t test___riscv_vor_tum(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,vl); +} + + +vuint16m1_t test___riscv_vor_tum(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,vl); +} + + +vuint16m2_t test___riscv_vor_tum(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,vl); +} + + +vuint16m4_t test___riscv_vor_tum(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,vl); +} + + +vuint16m8_t test___riscv_vor_tum(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,vl); +} + + +vuint32mf2_t test___riscv_vor_tum(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,vl); +} + + +vuint32m1_t test___riscv_vor_tum(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,vl); +} + + +vuint32m2_t test___riscv_vor_tum(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,vl); +} + + +vuint32m4_t test___riscv_vor_tum(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,vl); +} + + +vuint32m8_t test___riscv_vor_tum(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,vl); +} + + +vuint64m1_t test___riscv_vor_tum(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,vl); +} + + +vuint64m2_t test___riscv_vor_tum(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,vl); +} + + +vuint64m4_t test___riscv_vor_tum(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,vl); +} + + +vuint64m8_t test___riscv_vor_tum(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 8 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vor_vx_tum_rv32-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vor_vx_tum_rv32-2.C new file mode 100644 index 00000000000..28981dc0d67 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vor_vx_tum_rv32-2.C @@ -0,0 +1,289 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vor_tum(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,31); +} + + +vint8mf4_t test___riscv_vor_tum(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,31); +} + + +vint8mf2_t test___riscv_vor_tum(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,31); +} + + +vint8m1_t test___riscv_vor_tum(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,31); +} + + +vint8m2_t test___riscv_vor_tum(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,31); +} + + +vint8m4_t test___riscv_vor_tum(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,31); +} + + +vint8m8_t test___riscv_vor_tum(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,31); +} + + +vint16mf4_t test___riscv_vor_tum(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,31); +} + + +vint16mf2_t test___riscv_vor_tum(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,31); +} + + +vint16m1_t test___riscv_vor_tum(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,31); +} + + +vint16m2_t test___riscv_vor_tum(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,31); +} + + +vint16m4_t test___riscv_vor_tum(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,31); +} + + +vint16m8_t test___riscv_vor_tum(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,31); +} + + +vint32mf2_t test___riscv_vor_tum(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,31); +} + + +vint32m1_t test___riscv_vor_tum(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,31); +} + + +vint32m2_t test___riscv_vor_tum(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,31); +} + + +vint32m4_t test___riscv_vor_tum(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,31); +} + + +vint32m8_t test___riscv_vor_tum(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,31); +} + + +vint64m1_t test___riscv_vor_tum(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,31); +} + + +vint64m2_t test___riscv_vor_tum(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,31); +} + + +vint64m4_t test___riscv_vor_tum(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,31); +} + + +vint64m8_t test___riscv_vor_tum(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,31); +} + + +vuint8mf8_t test___riscv_vor_tum(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,31); +} + + +vuint8mf4_t test___riscv_vor_tum(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,31); +} + + +vuint8mf2_t test___riscv_vor_tum(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,31); +} + + +vuint8m1_t test___riscv_vor_tum(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,31); +} + + +vuint8m2_t test___riscv_vor_tum(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,31); +} + + +vuint8m4_t test___riscv_vor_tum(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,31); +} + + +vuint8m8_t test___riscv_vor_tum(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,31); +} + + +vuint16mf4_t test___riscv_vor_tum(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,31); +} + + +vuint16mf2_t test___riscv_vor_tum(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,31); +} + + +vuint16m1_t test___riscv_vor_tum(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,31); +} + + +vuint16m2_t test___riscv_vor_tum(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,31); +} + + +vuint16m4_t test___riscv_vor_tum(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,31); +} + + +vuint16m8_t test___riscv_vor_tum(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,31); +} + + +vuint32mf2_t test___riscv_vor_tum(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,31); +} + + +vuint32m1_t test___riscv_vor_tum(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,31); +} + + +vuint32m2_t test___riscv_vor_tum(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,31); +} + + +vuint32m4_t test___riscv_vor_tum(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,31); +} + + +vuint32m8_t test___riscv_vor_tum(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,31); +} + + +vuint64m1_t test___riscv_vor_tum(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,31); +} + + +vuint64m2_t test___riscv_vor_tum(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,31); +} + + +vuint64m4_t test___riscv_vor_tum(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,31); +} + + +vuint64m8_t test___riscv_vor_tum(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 8 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vor_vx_tum_rv32-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vor_vx_tum_rv32-3.C new file mode 100644 index 00000000000..9dab02183a1 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vor_vx_tum_rv32-3.C @@ -0,0 +1,289 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vor_tum(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,32); +} + + +vint8mf4_t test___riscv_vor_tum(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,32); +} + + +vint8mf2_t test___riscv_vor_tum(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,32); +} + + +vint8m1_t test___riscv_vor_tum(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,32); +} + + +vint8m2_t test___riscv_vor_tum(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,32); +} + + +vint8m4_t test___riscv_vor_tum(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,32); +} + + +vint8m8_t test___riscv_vor_tum(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,32); +} + + +vint16mf4_t test___riscv_vor_tum(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,32); +} + + +vint16mf2_t test___riscv_vor_tum(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,32); +} + + +vint16m1_t test___riscv_vor_tum(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,32); +} + + +vint16m2_t test___riscv_vor_tum(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,32); +} + + +vint16m4_t test___riscv_vor_tum(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,32); +} + + +vint16m8_t test___riscv_vor_tum(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,32); +} + + +vint32mf2_t test___riscv_vor_tum(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,32); +} + + +vint32m1_t test___riscv_vor_tum(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,32); +} + + +vint32m2_t test___riscv_vor_tum(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,32); +} + + +vint32m4_t test___riscv_vor_tum(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,32); +} + + +vint32m8_t test___riscv_vor_tum(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,32); +} + + +vint64m1_t test___riscv_vor_tum(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,32); +} + + +vint64m2_t test___riscv_vor_tum(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,32); +} + + +vint64m4_t test___riscv_vor_tum(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,32); +} + + +vint64m8_t test___riscv_vor_tum(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,32); +} + + +vuint8mf8_t test___riscv_vor_tum(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,32); +} + + +vuint8mf4_t test___riscv_vor_tum(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,32); +} + + +vuint8mf2_t test___riscv_vor_tum(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,32); +} + + +vuint8m1_t test___riscv_vor_tum(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,32); +} + + +vuint8m2_t test___riscv_vor_tum(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,32); +} + + +vuint8m4_t test___riscv_vor_tum(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,32); +} + + +vuint8m8_t test___riscv_vor_tum(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,32); +} + + +vuint16mf4_t test___riscv_vor_tum(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,32); +} + + +vuint16mf2_t test___riscv_vor_tum(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,32); +} + + +vuint16m1_t test___riscv_vor_tum(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,32); +} + + +vuint16m2_t test___riscv_vor_tum(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,32); +} + + +vuint16m4_t test___riscv_vor_tum(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,32); +} + + +vuint16m8_t test___riscv_vor_tum(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,32); +} + + +vuint32mf2_t test___riscv_vor_tum(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,32); +} + + +vuint32m1_t test___riscv_vor_tum(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,32); +} + + +vuint32m2_t test___riscv_vor_tum(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,32); +} + + +vuint32m4_t test___riscv_vor_tum(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,32); +} + + +vuint32m8_t test___riscv_vor_tum(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,32); +} + + +vuint64m1_t test___riscv_vor_tum(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,32); +} + + +vuint64m2_t test___riscv_vor_tum(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,32); +} + + +vuint64m4_t test___riscv_vor_tum(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,32); +} + + +vuint64m8_t test___riscv_vor_tum(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 8 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vor_vx_tum_rv64-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vor_vx_tum_rv64-1.C new file mode 100644 index 00000000000..0f3dd1fca96 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vor_vx_tum_rv64-1.C @@ -0,0 +1,292 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vor_tum(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,vl); +} + + +vint8mf4_t test___riscv_vor_tum(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,vl); +} + + +vint8mf2_t test___riscv_vor_tum(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,vl); +} + + +vint8m1_t test___riscv_vor_tum(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,vl); +} + + +vint8m2_t test___riscv_vor_tum(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,vl); +} + + +vint8m4_t test___riscv_vor_tum(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,vl); +} + + +vint8m8_t test___riscv_vor_tum(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,vl); +} + + +vint16mf4_t test___riscv_vor_tum(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,vl); +} + + +vint16mf2_t test___riscv_vor_tum(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,vl); +} + + +vint16m1_t test___riscv_vor_tum(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,vl); +} + + +vint16m2_t test___riscv_vor_tum(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,vl); +} + + +vint16m4_t test___riscv_vor_tum(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,vl); +} + + +vint16m8_t test___riscv_vor_tum(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,vl); +} + + +vint32mf2_t test___riscv_vor_tum(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,vl); +} + + +vint32m1_t test___riscv_vor_tum(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,vl); +} + + +vint32m2_t test___riscv_vor_tum(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,vl); +} + + +vint32m4_t test___riscv_vor_tum(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,vl); +} + + +vint32m8_t test___riscv_vor_tum(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,vl); +} + + +vint64m1_t test___riscv_vor_tum(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,vl); +} + + +vint64m2_t test___riscv_vor_tum(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,vl); +} + + +vint64m4_t test___riscv_vor_tum(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,vl); +} + + +vint64m8_t test___riscv_vor_tum(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,vl); +} + + +vuint8mf8_t test___riscv_vor_tum(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,vl); +} + + +vuint8mf4_t test___riscv_vor_tum(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,vl); +} + + +vuint8mf2_t test___riscv_vor_tum(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,vl); +} + + +vuint8m1_t test___riscv_vor_tum(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,vl); +} + + +vuint8m2_t test___riscv_vor_tum(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,vl); +} + + +vuint8m4_t test___riscv_vor_tum(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,vl); +} + + +vuint8m8_t test___riscv_vor_tum(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,vl); +} + + +vuint16mf4_t test___riscv_vor_tum(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,vl); +} + + +vuint16mf2_t test___riscv_vor_tum(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,vl); +} + + +vuint16m1_t test___riscv_vor_tum(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,vl); +} + + +vuint16m2_t test___riscv_vor_tum(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,vl); +} + + +vuint16m4_t test___riscv_vor_tum(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,vl); +} + + +vuint16m8_t test___riscv_vor_tum(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,vl); +} + + +vuint32mf2_t test___riscv_vor_tum(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,vl); +} + + +vuint32m1_t test___riscv_vor_tum(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,vl); +} + + +vuint32m2_t test___riscv_vor_tum(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,vl); +} + + +vuint32m4_t test___riscv_vor_tum(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,vl); +} + + +vuint32m8_t test___riscv_vor_tum(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,vl); +} + + +vuint64m1_t test___riscv_vor_tum(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,vl); +} + + +vuint64m2_t test___riscv_vor_tum(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,vl); +} + + +vuint64m4_t test___riscv_vor_tum(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,vl); +} + + +vuint64m8_t test___riscv_vor_tum(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vor_vx_tum_rv64-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vor_vx_tum_rv64-2.C new file mode 100644 index 00000000000..9f3186efce1 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vor_vx_tum_rv64-2.C @@ -0,0 +1,292 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vor_tum(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,31); +} + + +vint8mf4_t test___riscv_vor_tum(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,31); +} + + +vint8mf2_t test___riscv_vor_tum(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,31); +} + + +vint8m1_t test___riscv_vor_tum(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,31); +} + + +vint8m2_t test___riscv_vor_tum(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,31); +} + + +vint8m4_t test___riscv_vor_tum(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,31); +} + + +vint8m8_t test___riscv_vor_tum(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,31); +} + + +vint16mf4_t test___riscv_vor_tum(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,31); +} + + +vint16mf2_t test___riscv_vor_tum(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,31); +} + + +vint16m1_t test___riscv_vor_tum(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,31); +} + + +vint16m2_t test___riscv_vor_tum(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,31); +} + + +vint16m4_t test___riscv_vor_tum(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,31); +} + + +vint16m8_t test___riscv_vor_tum(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,31); +} + + +vint32mf2_t test___riscv_vor_tum(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,31); +} + + +vint32m1_t test___riscv_vor_tum(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,31); +} + + +vint32m2_t test___riscv_vor_tum(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,31); +} + + +vint32m4_t test___riscv_vor_tum(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,31); +} + + +vint32m8_t test___riscv_vor_tum(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,31); +} + + +vint64m1_t test___riscv_vor_tum(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,31); +} + + +vint64m2_t test___riscv_vor_tum(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,31); +} + + +vint64m4_t test___riscv_vor_tum(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,31); +} + + +vint64m8_t test___riscv_vor_tum(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,31); +} + + +vuint8mf8_t test___riscv_vor_tum(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,31); +} + + +vuint8mf4_t test___riscv_vor_tum(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,31); +} + + +vuint8mf2_t test___riscv_vor_tum(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,31); +} + + +vuint8m1_t test___riscv_vor_tum(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,31); +} + + +vuint8m2_t test___riscv_vor_tum(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,31); +} + + +vuint8m4_t test___riscv_vor_tum(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,31); +} + + +vuint8m8_t test___riscv_vor_tum(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,31); +} + + +vuint16mf4_t test___riscv_vor_tum(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,31); +} + + +vuint16mf2_t test___riscv_vor_tum(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,31); +} + + +vuint16m1_t test___riscv_vor_tum(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,31); +} + + +vuint16m2_t test___riscv_vor_tum(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,31); +} + + +vuint16m4_t test___riscv_vor_tum(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,31); +} + + +vuint16m8_t test___riscv_vor_tum(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,31); +} + + +vuint32mf2_t test___riscv_vor_tum(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,31); +} + + +vuint32m1_t test___riscv_vor_tum(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,31); +} + + +vuint32m2_t test___riscv_vor_tum(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,31); +} + + +vuint32m4_t test___riscv_vor_tum(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,31); +} + + +vuint32m8_t test___riscv_vor_tum(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,31); +} + + +vuint64m1_t test___riscv_vor_tum(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,31); +} + + +vuint64m2_t test___riscv_vor_tum(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,31); +} + + +vuint64m4_t test___riscv_vor_tum(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,31); +} + + +vuint64m8_t test___riscv_vor_tum(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vor_vx_tum_rv64-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vor_vx_tum_rv64-3.C new file mode 100644 index 00000000000..b6edef1582c --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vor_vx_tum_rv64-3.C @@ -0,0 +1,292 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vor_tum(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,32); +} + + +vint8mf4_t test___riscv_vor_tum(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,32); +} + + +vint8mf2_t test___riscv_vor_tum(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,32); +} + + +vint8m1_t test___riscv_vor_tum(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,32); +} + + +vint8m2_t test___riscv_vor_tum(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,32); +} + + +vint8m4_t test___riscv_vor_tum(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,32); +} + + +vint8m8_t test___riscv_vor_tum(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,32); +} + + +vint16mf4_t test___riscv_vor_tum(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,32); +} + + +vint16mf2_t test___riscv_vor_tum(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,32); +} + + +vint16m1_t test___riscv_vor_tum(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,32); +} + + +vint16m2_t test___riscv_vor_tum(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,32); +} + + +vint16m4_t test___riscv_vor_tum(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,32); +} + + +vint16m8_t test___riscv_vor_tum(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,32); +} + + +vint32mf2_t test___riscv_vor_tum(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,32); +} + + +vint32m1_t test___riscv_vor_tum(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,32); +} + + +vint32m2_t test___riscv_vor_tum(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,32); +} + + +vint32m4_t test___riscv_vor_tum(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,32); +} + + +vint32m8_t test___riscv_vor_tum(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,32); +} + + +vint64m1_t test___riscv_vor_tum(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,32); +} + + +vint64m2_t test___riscv_vor_tum(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,32); +} + + +vint64m4_t test___riscv_vor_tum(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,32); +} + + +vint64m8_t test___riscv_vor_tum(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,32); +} + + +vuint8mf8_t test___riscv_vor_tum(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,32); +} + + +vuint8mf4_t test___riscv_vor_tum(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,32); +} + + +vuint8mf2_t test___riscv_vor_tum(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,32); +} + + +vuint8m1_t test___riscv_vor_tum(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,32); +} + + +vuint8m2_t test___riscv_vor_tum(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,32); +} + + +vuint8m4_t test___riscv_vor_tum(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,32); +} + + +vuint8m8_t test___riscv_vor_tum(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,32); +} + + +vuint16mf4_t test___riscv_vor_tum(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,32); +} + + +vuint16mf2_t test___riscv_vor_tum(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,32); +} + + +vuint16m1_t test___riscv_vor_tum(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,32); +} + + +vuint16m2_t test___riscv_vor_tum(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,32); +} + + +vuint16m4_t test___riscv_vor_tum(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,32); +} + + +vuint16m8_t test___riscv_vor_tum(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,32); +} + + +vuint32mf2_t test___riscv_vor_tum(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,32); +} + + +vuint32m1_t test___riscv_vor_tum(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,32); +} + + +vuint32m2_t test___riscv_vor_tum(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,32); +} + + +vuint32m4_t test___riscv_vor_tum(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,32); +} + + +vuint32m8_t test___riscv_vor_tum(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,32); +} + + +vuint64m1_t test___riscv_vor_tum(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,32); +} + + +vuint64m2_t test___riscv_vor_tum(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,32); +} + + +vuint64m4_t test___riscv_vor_tum(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,32); +} + + +vuint64m8_t test___riscv_vor_tum(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vor_tum(mask,merge,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vor_vx_tumu_rv32-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vor_vx_tumu_rv32-1.C new file mode 100644 index 00000000000..db21241580d --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vor_vx_tumu_rv32-1.C @@ -0,0 +1,289 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vor_tumu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,vl); +} + + +vint8mf4_t test___riscv_vor_tumu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,vl); +} + + +vint8mf2_t test___riscv_vor_tumu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,vl); +} + + +vint8m1_t test___riscv_vor_tumu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,vl); +} + + +vint8m2_t test___riscv_vor_tumu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,vl); +} + + +vint8m4_t test___riscv_vor_tumu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,vl); +} + + +vint8m8_t test___riscv_vor_tumu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,vl); +} + + +vint16mf4_t test___riscv_vor_tumu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,vl); +} + + +vint16mf2_t test___riscv_vor_tumu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,vl); +} + + +vint16m1_t test___riscv_vor_tumu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,vl); +} + + +vint16m2_t test___riscv_vor_tumu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,vl); +} + + +vint16m4_t test___riscv_vor_tumu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,vl); +} + + +vint16m8_t test___riscv_vor_tumu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,vl); +} + + +vint32mf2_t test___riscv_vor_tumu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,vl); +} + + +vint32m1_t test___riscv_vor_tumu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,vl); +} + + +vint32m2_t test___riscv_vor_tumu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,vl); +} + + +vint32m4_t test___riscv_vor_tumu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,vl); +} + + +vint32m8_t test___riscv_vor_tumu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,vl); +} + + +vint64m1_t test___riscv_vor_tumu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,vl); +} + + +vint64m2_t test___riscv_vor_tumu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,vl); +} + + +vint64m4_t test___riscv_vor_tumu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,vl); +} + + +vint64m8_t test___riscv_vor_tumu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,vl); +} + + +vuint8mf8_t test___riscv_vor_tumu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,vl); +} + + +vuint8mf4_t test___riscv_vor_tumu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,vl); +} + + +vuint8mf2_t test___riscv_vor_tumu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,vl); +} + + +vuint8m1_t test___riscv_vor_tumu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,vl); +} + + +vuint8m2_t test___riscv_vor_tumu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,vl); +} + + +vuint8m4_t test___riscv_vor_tumu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,vl); +} + + +vuint8m8_t test___riscv_vor_tumu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,vl); +} + + +vuint16mf4_t test___riscv_vor_tumu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,vl); +} + + +vuint16mf2_t test___riscv_vor_tumu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,vl); +} + + +vuint16m1_t test___riscv_vor_tumu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,vl); +} + + +vuint16m2_t test___riscv_vor_tumu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,vl); +} + + +vuint16m4_t test___riscv_vor_tumu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,vl); +} + + +vuint16m8_t test___riscv_vor_tumu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,vl); +} + + +vuint32mf2_t test___riscv_vor_tumu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,vl); +} + + +vuint32m1_t test___riscv_vor_tumu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,vl); +} + + +vuint32m2_t test___riscv_vor_tumu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,vl); +} + + +vuint32m4_t test___riscv_vor_tumu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,vl); +} + + +vuint32m8_t test___riscv_vor_tumu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,vl); +} + + +vuint64m1_t test___riscv_vor_tumu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,vl); +} + + +vuint64m2_t test___riscv_vor_tumu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,vl); +} + + +vuint64m4_t test___riscv_vor_tumu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,vl); +} + + +vuint64m8_t test___riscv_vor_tumu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*mu\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*mu\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*mu\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 8 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vor_vx_tumu_rv32-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vor_vx_tumu_rv32-2.C new file mode 100644 index 00000000000..4bdd4871aec --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vor_vx_tumu_rv32-2.C @@ -0,0 +1,289 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vor_tumu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,31); +} + + +vint8mf4_t test___riscv_vor_tumu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,31); +} + + +vint8mf2_t test___riscv_vor_tumu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,31); +} + + +vint8m1_t test___riscv_vor_tumu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,31); +} + + +vint8m2_t test___riscv_vor_tumu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,31); +} + + +vint8m4_t test___riscv_vor_tumu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,31); +} + + +vint8m8_t test___riscv_vor_tumu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,31); +} + + +vint16mf4_t test___riscv_vor_tumu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,31); +} + + +vint16mf2_t test___riscv_vor_tumu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,31); +} + + +vint16m1_t test___riscv_vor_tumu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,31); +} + + +vint16m2_t test___riscv_vor_tumu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,31); +} + + +vint16m4_t test___riscv_vor_tumu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,31); +} + + +vint16m8_t test___riscv_vor_tumu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,31); +} + + +vint32mf2_t test___riscv_vor_tumu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,31); +} + + +vint32m1_t test___riscv_vor_tumu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,31); +} + + +vint32m2_t test___riscv_vor_tumu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,31); +} + + +vint32m4_t test___riscv_vor_tumu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,31); +} + + +vint32m8_t test___riscv_vor_tumu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,31); +} + + +vint64m1_t test___riscv_vor_tumu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,31); +} + + +vint64m2_t test___riscv_vor_tumu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,31); +} + + +vint64m4_t test___riscv_vor_tumu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,31); +} + + +vint64m8_t test___riscv_vor_tumu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,31); +} + + +vuint8mf8_t test___riscv_vor_tumu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,31); +} + + +vuint8mf4_t test___riscv_vor_tumu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,31); +} + + +vuint8mf2_t test___riscv_vor_tumu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,31); +} + + +vuint8m1_t test___riscv_vor_tumu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,31); +} + + +vuint8m2_t test___riscv_vor_tumu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,31); +} + + +vuint8m4_t test___riscv_vor_tumu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,31); +} + + +vuint8m8_t test___riscv_vor_tumu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,31); +} + + +vuint16mf4_t test___riscv_vor_tumu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,31); +} + + +vuint16mf2_t test___riscv_vor_tumu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,31); +} + + +vuint16m1_t test___riscv_vor_tumu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,31); +} + + +vuint16m2_t test___riscv_vor_tumu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,31); +} + + +vuint16m4_t test___riscv_vor_tumu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,31); +} + + +vuint16m8_t test___riscv_vor_tumu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,31); +} + + +vuint32mf2_t test___riscv_vor_tumu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,31); +} + + +vuint32m1_t test___riscv_vor_tumu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,31); +} + + +vuint32m2_t test___riscv_vor_tumu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,31); +} + + +vuint32m4_t test___riscv_vor_tumu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,31); +} + + +vuint32m8_t test___riscv_vor_tumu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,31); +} + + +vuint64m1_t test___riscv_vor_tumu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,31); +} + + +vuint64m2_t test___riscv_vor_tumu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,31); +} + + +vuint64m4_t test___riscv_vor_tumu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,31); +} + + +vuint64m8_t test___riscv_vor_tumu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*mu\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*mu\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*mu\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*mu\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*mu\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*mu\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*mu\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*mu\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*mu\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*mu\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*mu\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*mu\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*mu\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*mu\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*mu\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*mu\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*mu\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*mu\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 8 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vor_vx_tumu_rv32-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vor_vx_tumu_rv32-3.C new file mode 100644 index 00000000000..44dd42ea23a --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vor_vx_tumu_rv32-3.C @@ -0,0 +1,289 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vor_tumu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,32); +} + + +vint8mf4_t test___riscv_vor_tumu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,32); +} + + +vint8mf2_t test___riscv_vor_tumu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,32); +} + + +vint8m1_t test___riscv_vor_tumu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,32); +} + + +vint8m2_t test___riscv_vor_tumu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,32); +} + + +vint8m4_t test___riscv_vor_tumu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,32); +} + + +vint8m8_t test___riscv_vor_tumu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,32); +} + + +vint16mf4_t test___riscv_vor_tumu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,32); +} + + +vint16mf2_t test___riscv_vor_tumu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,32); +} + + +vint16m1_t test___riscv_vor_tumu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,32); +} + + +vint16m2_t test___riscv_vor_tumu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,32); +} + + +vint16m4_t test___riscv_vor_tumu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,32); +} + + +vint16m8_t test___riscv_vor_tumu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,32); +} + + +vint32mf2_t test___riscv_vor_tumu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,32); +} + + +vint32m1_t test___riscv_vor_tumu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,32); +} + + +vint32m2_t test___riscv_vor_tumu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,32); +} + + +vint32m4_t test___riscv_vor_tumu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,32); +} + + +vint32m8_t test___riscv_vor_tumu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,32); +} + + +vint64m1_t test___riscv_vor_tumu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,32); +} + + +vint64m2_t test___riscv_vor_tumu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,32); +} + + +vint64m4_t test___riscv_vor_tumu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,32); +} + + +vint64m8_t test___riscv_vor_tumu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,32); +} + + +vuint8mf8_t test___riscv_vor_tumu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,32); +} + + +vuint8mf4_t test___riscv_vor_tumu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,32); +} + + +vuint8mf2_t test___riscv_vor_tumu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,32); +} + + +vuint8m1_t test___riscv_vor_tumu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,32); +} + + +vuint8m2_t test___riscv_vor_tumu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,32); +} + + +vuint8m4_t test___riscv_vor_tumu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,32); +} + + +vuint8m8_t test___riscv_vor_tumu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,32); +} + + +vuint16mf4_t test___riscv_vor_tumu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,32); +} + + +vuint16mf2_t test___riscv_vor_tumu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,32); +} + + +vuint16m1_t test___riscv_vor_tumu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,32); +} + + +vuint16m2_t test___riscv_vor_tumu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,32); +} + + +vuint16m4_t test___riscv_vor_tumu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,32); +} + + +vuint16m8_t test___riscv_vor_tumu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,32); +} + + +vuint32mf2_t test___riscv_vor_tumu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,32); +} + + +vuint32m1_t test___riscv_vor_tumu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,32); +} + + +vuint32m2_t test___riscv_vor_tumu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,32); +} + + +vuint32m4_t test___riscv_vor_tumu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,32); +} + + +vuint32m8_t test___riscv_vor_tumu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,32); +} + + +vuint64m1_t test___riscv_vor_tumu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,32); +} + + +vuint64m2_t test___riscv_vor_tumu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,32); +} + + +vuint64m4_t test___riscv_vor_tumu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,32); +} + + +vuint64m8_t test___riscv_vor_tumu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*mu\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*mu\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*mu\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 8 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vor_vx_tumu_rv64-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vor_vx_tumu_rv64-1.C new file mode 100644 index 00000000000..e0ecca6efae --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vor_vx_tumu_rv64-1.C @@ -0,0 +1,292 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vor_tumu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,vl); +} + + +vint8mf4_t test___riscv_vor_tumu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,vl); +} + + +vint8mf2_t test___riscv_vor_tumu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,vl); +} + + +vint8m1_t test___riscv_vor_tumu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,vl); +} + + +vint8m2_t test___riscv_vor_tumu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,vl); +} + + +vint8m4_t test___riscv_vor_tumu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,vl); +} + + +vint8m8_t test___riscv_vor_tumu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,vl); +} + + +vint16mf4_t test___riscv_vor_tumu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,vl); +} + + +vint16mf2_t test___riscv_vor_tumu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,vl); +} + + +vint16m1_t test___riscv_vor_tumu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,vl); +} + + +vint16m2_t test___riscv_vor_tumu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,vl); +} + + +vint16m4_t test___riscv_vor_tumu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,vl); +} + + +vint16m8_t test___riscv_vor_tumu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,vl); +} + + +vint32mf2_t test___riscv_vor_tumu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,vl); +} + + +vint32m1_t test___riscv_vor_tumu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,vl); +} + + +vint32m2_t test___riscv_vor_tumu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,vl); +} + + +vint32m4_t test___riscv_vor_tumu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,vl); +} + + +vint32m8_t test___riscv_vor_tumu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,vl); +} + + +vint64m1_t test___riscv_vor_tumu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,vl); +} + + +vint64m2_t test___riscv_vor_tumu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,vl); +} + + +vint64m4_t test___riscv_vor_tumu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,vl); +} + + +vint64m8_t test___riscv_vor_tumu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,vl); +} + + +vuint8mf8_t test___riscv_vor_tumu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,vl); +} + + +vuint8mf4_t test___riscv_vor_tumu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,vl); +} + + +vuint8mf2_t test___riscv_vor_tumu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,vl); +} + + +vuint8m1_t test___riscv_vor_tumu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,vl); +} + + +vuint8m2_t test___riscv_vor_tumu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,vl); +} + + +vuint8m4_t test___riscv_vor_tumu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,vl); +} + + +vuint8m8_t test___riscv_vor_tumu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,vl); +} + + +vuint16mf4_t test___riscv_vor_tumu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,vl); +} + + +vuint16mf2_t test___riscv_vor_tumu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,vl); +} + + +vuint16m1_t test___riscv_vor_tumu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,vl); +} + + +vuint16m2_t test___riscv_vor_tumu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,vl); +} + + +vuint16m4_t test___riscv_vor_tumu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,vl); +} + + +vuint16m8_t test___riscv_vor_tumu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,vl); +} + + +vuint32mf2_t test___riscv_vor_tumu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,vl); +} + + +vuint32m1_t test___riscv_vor_tumu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,vl); +} + + +vuint32m2_t test___riscv_vor_tumu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,vl); +} + + +vuint32m4_t test___riscv_vor_tumu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,vl); +} + + +vuint32m8_t test___riscv_vor_tumu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,vl); +} + + +vuint64m1_t test___riscv_vor_tumu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,vl); +} + + +vuint64m2_t test___riscv_vor_tumu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,vl); +} + + +vuint64m4_t test___riscv_vor_tumu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,vl); +} + + +vuint64m8_t test___riscv_vor_tumu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*mu\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*mu\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*mu\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*mu\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*mu\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*mu\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*mu\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vor_vx_tumu_rv64-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vor_vx_tumu_rv64-2.C new file mode 100644 index 00000000000..8111d61acf6 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vor_vx_tumu_rv64-2.C @@ -0,0 +1,292 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vor_tumu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,31); +} + + +vint8mf4_t test___riscv_vor_tumu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,31); +} + + +vint8mf2_t test___riscv_vor_tumu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,31); +} + + +vint8m1_t test___riscv_vor_tumu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,31); +} + + +vint8m2_t test___riscv_vor_tumu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,31); +} + + +vint8m4_t test___riscv_vor_tumu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,31); +} + + +vint8m8_t test___riscv_vor_tumu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,31); +} + + +vint16mf4_t test___riscv_vor_tumu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,31); +} + + +vint16mf2_t test___riscv_vor_tumu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,31); +} + + +vint16m1_t test___riscv_vor_tumu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,31); +} + + +vint16m2_t test___riscv_vor_tumu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,31); +} + + +vint16m4_t test___riscv_vor_tumu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,31); +} + + +vint16m8_t test___riscv_vor_tumu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,31); +} + + +vint32mf2_t test___riscv_vor_tumu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,31); +} + + +vint32m1_t test___riscv_vor_tumu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,31); +} + + +vint32m2_t test___riscv_vor_tumu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,31); +} + + +vint32m4_t test___riscv_vor_tumu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,31); +} + + +vint32m8_t test___riscv_vor_tumu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,31); +} + + +vint64m1_t test___riscv_vor_tumu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,31); +} + + +vint64m2_t test___riscv_vor_tumu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,31); +} + + +vint64m4_t test___riscv_vor_tumu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,31); +} + + +vint64m8_t test___riscv_vor_tumu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,31); +} + + +vuint8mf8_t test___riscv_vor_tumu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,31); +} + + +vuint8mf4_t test___riscv_vor_tumu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,31); +} + + +vuint8mf2_t test___riscv_vor_tumu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,31); +} + + +vuint8m1_t test___riscv_vor_tumu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,31); +} + + +vuint8m2_t test___riscv_vor_tumu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,31); +} + + +vuint8m4_t test___riscv_vor_tumu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,31); +} + + +vuint8m8_t test___riscv_vor_tumu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,31); +} + + +vuint16mf4_t test___riscv_vor_tumu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,31); +} + + +vuint16mf2_t test___riscv_vor_tumu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,31); +} + + +vuint16m1_t test___riscv_vor_tumu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,31); +} + + +vuint16m2_t test___riscv_vor_tumu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,31); +} + + +vuint16m4_t test___riscv_vor_tumu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,31); +} + + +vuint16m8_t test___riscv_vor_tumu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,31); +} + + +vuint32mf2_t test___riscv_vor_tumu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,31); +} + + +vuint32m1_t test___riscv_vor_tumu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,31); +} + + +vuint32m2_t test___riscv_vor_tumu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,31); +} + + +vuint32m4_t test___riscv_vor_tumu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,31); +} + + +vuint32m8_t test___riscv_vor_tumu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,31); +} + + +vuint64m1_t test___riscv_vor_tumu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,31); +} + + +vuint64m2_t test___riscv_vor_tumu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,31); +} + + +vuint64m4_t test___riscv_vor_tumu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,31); +} + + +vuint64m8_t test___riscv_vor_tumu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*mu\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*mu\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*mu\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*mu\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*mu\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*mu\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*mu\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*mu\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*mu\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*mu\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*mu\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*mu\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*mu\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*mu\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*mu\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*mu\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*mu\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*mu\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*mu\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*mu\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*mu\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*mu\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vor_vx_tumu_rv64-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vor_vx_tumu_rv64-3.C new file mode 100644 index 00000000000..d19f92e3ce9 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vor_vx_tumu_rv64-3.C @@ -0,0 +1,292 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vor_tumu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,32); +} + + +vint8mf4_t test___riscv_vor_tumu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,32); +} + + +vint8mf2_t test___riscv_vor_tumu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,32); +} + + +vint8m1_t test___riscv_vor_tumu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,32); +} + + +vint8m2_t test___riscv_vor_tumu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,32); +} + + +vint8m4_t test___riscv_vor_tumu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,32); +} + + +vint8m8_t test___riscv_vor_tumu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,32); +} + + +vint16mf4_t test___riscv_vor_tumu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,32); +} + + +vint16mf2_t test___riscv_vor_tumu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,32); +} + + +vint16m1_t test___riscv_vor_tumu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,32); +} + + +vint16m2_t test___riscv_vor_tumu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,32); +} + + +vint16m4_t test___riscv_vor_tumu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,32); +} + + +vint16m8_t test___riscv_vor_tumu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,32); +} + + +vint32mf2_t test___riscv_vor_tumu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,32); +} + + +vint32m1_t test___riscv_vor_tumu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,32); +} + + +vint32m2_t test___riscv_vor_tumu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,32); +} + + +vint32m4_t test___riscv_vor_tumu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,32); +} + + +vint32m8_t test___riscv_vor_tumu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,32); +} + + +vint64m1_t test___riscv_vor_tumu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,32); +} + + +vint64m2_t test___riscv_vor_tumu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,32); +} + + +vint64m4_t test___riscv_vor_tumu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,32); +} + + +vint64m8_t test___riscv_vor_tumu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,32); +} + + +vuint8mf8_t test___riscv_vor_tumu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,32); +} + + +vuint8mf4_t test___riscv_vor_tumu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,32); +} + + +vuint8mf2_t test___riscv_vor_tumu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,32); +} + + +vuint8m1_t test___riscv_vor_tumu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,32); +} + + +vuint8m2_t test___riscv_vor_tumu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,32); +} + + +vuint8m4_t test___riscv_vor_tumu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,32); +} + + +vuint8m8_t test___riscv_vor_tumu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,32); +} + + +vuint16mf4_t test___riscv_vor_tumu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,32); +} + + +vuint16mf2_t test___riscv_vor_tumu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,32); +} + + +vuint16m1_t test___riscv_vor_tumu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,32); +} + + +vuint16m2_t test___riscv_vor_tumu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,32); +} + + +vuint16m4_t test___riscv_vor_tumu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,32); +} + + +vuint16m8_t test___riscv_vor_tumu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,32); +} + + +vuint32mf2_t test___riscv_vor_tumu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,32); +} + + +vuint32m1_t test___riscv_vor_tumu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,32); +} + + +vuint32m2_t test___riscv_vor_tumu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,32); +} + + +vuint32m4_t test___riscv_vor_tumu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,32); +} + + +vuint32m8_t test___riscv_vor_tumu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,32); +} + + +vuint64m1_t test___riscv_vor_tumu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,32); +} + + +vuint64m2_t test___riscv_vor_tumu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,32); +} + + +vuint64m4_t test___riscv_vor_tumu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,32); +} + + +vuint64m8_t test___riscv_vor_tumu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vor_tumu(mask,merge,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*mu\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*mu\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*mu\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*mu\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*mu\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*mu\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*mu\s+vor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */