From patchwork Fri Feb 3 07:45:23 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "juzhe.zhong@rivai.ai" X-Patchwork-Id: 64223 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 81DDE385B530 for ; Fri, 3 Feb 2023 07:46:25 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from smtpbguseast3.qq.com (smtpbguseast3.qq.com [54.243.244.52]) by sourceware.org (Postfix) with ESMTPS id A3B14385B502 for ; Fri, 3 Feb 2023 07:45:30 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org A3B14385B502 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivai.ai Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivai.ai X-QQ-mid: bizesmtp85t1675410325t4bl7z1w Received: from server1.localdomain ( [58.60.1.22]) by bizesmtp.qq.com (ESMTP) with id ; Fri, 03 Feb 2023 15:45:24 +0800 (CST) X-QQ-SSF: 01400000000000E0L000000A0000000 X-QQ-FEAT: q+EIYT+FhZpkcTm7QVeJ87bkP0w+aizo8x2160IeVHZsW22ALo+pve5eVapcH OoQCOzjm+wmdrI0SMp6JqTavCecqI6dvW7032bYQ6gO7iADDQDOD4XSZeK/Id926H7In+ni Q5h+++BJmkdokc6UzLv92unanHREmd2Rg5Yq4sxU9J2yWX7oUTq4nwLdkHvhInit3HA6LDK sYbzlIlWXz9FTTG02hc3eIgd2jGpnrodzBz7gVFAczHKHDLb3pkLNd3vs9Np88MGEQ8N9uM sqqjMSO/FLu4X0FAf4y3YoWdvQk61Hbf+XEaucl6d/Zy2jztXtN1C1LsPMlc6fSOOJLfyJM H7fhASmIc6LGCmhAPRKK04K4ABbWygg875g2UbKpXHuFytRAfnbt4vbt3O3eIY+x2JjnAEk X-QQ-GoodBg: 2 From: juzhe.zhong@rivai.ai To: gcc-patches@gcc.gnu.org Cc: kito.cheng@gmail.com, Ju-Zhe Zhong Subject: [PATCH] RISC-V: Add vadd.vx C++ API tests Date: Fri, 3 Feb 2023 15:45:23 +0800 Message-Id: <20230203074523.201447-1-juzhe.zhong@rivai.ai> X-Mailer: git-send-email 2.36.1 MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:rivai.ai:qybglogicsvr:qybglogicsvr7 X-Spam-Status: No, score=-10.9 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, RCVD_IN_BARRACUDACENTRAL, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_PASS, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" From: Ju-Zhe Zhong gcc/testsuite/ChangeLog: * g++.target/riscv/rvv/base/vadd_vx_mu_rv32-1.C: New test. * g++.target/riscv/rvv/base/vadd_vx_mu_rv32-2.C: New test. * g++.target/riscv/rvv/base/vadd_vx_mu_rv32-3.C: New test. * g++.target/riscv/rvv/base/vadd_vx_mu_rv64-1.C: New test. * g++.target/riscv/rvv/base/vadd_vx_mu_rv64-2.C: New test. * g++.target/riscv/rvv/base/vadd_vx_mu_rv64-3.C: New test. * g++.target/riscv/rvv/base/vadd_vx_rv32-1.C: New test. * g++.target/riscv/rvv/base/vadd_vx_rv32-2.C: New test. * g++.target/riscv/rvv/base/vadd_vx_rv32-3.C: New test. * g++.target/riscv/rvv/base/vadd_vx_rv64-1.C: New test. * g++.target/riscv/rvv/base/vadd_vx_rv64-2.C: New test. * g++.target/riscv/rvv/base/vadd_vx_rv64-3.C: New test. * g++.target/riscv/rvv/base/vadd_vx_tu_rv32-1.C: New test. * g++.target/riscv/rvv/base/vadd_vx_tu_rv32-2.C: New test. * g++.target/riscv/rvv/base/vadd_vx_tu_rv32-3.C: New test. * g++.target/riscv/rvv/base/vadd_vx_tu_rv64-1.C: New test. * g++.target/riscv/rvv/base/vadd_vx_tu_rv64-2.C: New test. * g++.target/riscv/rvv/base/vadd_vx_tu_rv64-3.C: New test. * g++.target/riscv/rvv/base/vadd_vx_tum_rv32-1.C: New test. * g++.target/riscv/rvv/base/vadd_vx_tum_rv32-2.C: New test. * g++.target/riscv/rvv/base/vadd_vx_tum_rv32-3.C: New test. * g++.target/riscv/rvv/base/vadd_vx_tum_rv64-1.C: New test. * g++.target/riscv/rvv/base/vadd_vx_tum_rv64-2.C: New test. * g++.target/riscv/rvv/base/vadd_vx_tum_rv64-3.C: New test. * g++.target/riscv/rvv/base/vadd_vx_tumu_rv32-1.C: New test. * g++.target/riscv/rvv/base/vadd_vx_tumu_rv32-2.C: New test. * g++.target/riscv/rvv/base/vadd_vx_tumu_rv32-3.C: New test. * g++.target/riscv/rvv/base/vadd_vx_tumu_rv64-1.C: New test. * g++.target/riscv/rvv/base/vadd_vx_tumu_rv64-2.C: New test. * g++.target/riscv/rvv/base/vadd_vx_tumu_rv64-3.C: New test. --- .../riscv/rvv/base/vadd_vx_mu_rv32-1.C | 289 +++++++++ .../riscv/rvv/base/vadd_vx_mu_rv32-2.C | 289 +++++++++ .../riscv/rvv/base/vadd_vx_mu_rv32-3.C | 289 +++++++++ .../riscv/rvv/base/vadd_vx_mu_rv64-1.C | 292 +++++++++ .../riscv/rvv/base/vadd_vx_mu_rv64-2.C | 292 +++++++++ .../riscv/rvv/base/vadd_vx_mu_rv64-3.C | 292 +++++++++ .../riscv/rvv/base/vadd_vx_rv32-1.C | 572 +++++++++++++++++ .../riscv/rvv/base/vadd_vx_rv32-2.C | 572 +++++++++++++++++ .../riscv/rvv/base/vadd_vx_rv32-3.C | 572 +++++++++++++++++ .../riscv/rvv/base/vadd_vx_rv64-1.C | 578 ++++++++++++++++++ .../riscv/rvv/base/vadd_vx_rv64-2.C | 578 ++++++++++++++++++ .../riscv/rvv/base/vadd_vx_rv64-3.C | 578 ++++++++++++++++++ .../riscv/rvv/base/vadd_vx_tu_rv32-1.C | 289 +++++++++ .../riscv/rvv/base/vadd_vx_tu_rv32-2.C | 289 +++++++++ .../riscv/rvv/base/vadd_vx_tu_rv32-3.C | 289 +++++++++ .../riscv/rvv/base/vadd_vx_tu_rv64-1.C | 292 +++++++++ .../riscv/rvv/base/vadd_vx_tu_rv64-2.C | 292 +++++++++ .../riscv/rvv/base/vadd_vx_tu_rv64-3.C | 292 +++++++++ .../riscv/rvv/base/vadd_vx_tum_rv32-1.C | 289 +++++++++ .../riscv/rvv/base/vadd_vx_tum_rv32-2.C | 289 +++++++++ .../riscv/rvv/base/vadd_vx_tum_rv32-3.C | 289 +++++++++ .../riscv/rvv/base/vadd_vx_tum_rv64-1.C | 292 +++++++++ .../riscv/rvv/base/vadd_vx_tum_rv64-2.C | 292 +++++++++ .../riscv/rvv/base/vadd_vx_tum_rv64-3.C | 292 +++++++++ .../riscv/rvv/base/vadd_vx_tumu_rv32-1.C | 289 +++++++++ .../riscv/rvv/base/vadd_vx_tumu_rv32-2.C | 289 +++++++++ .../riscv/rvv/base/vadd_vx_tumu_rv32-3.C | 289 +++++++++ .../riscv/rvv/base/vadd_vx_tumu_rv64-1.C | 292 +++++++++ .../riscv/rvv/base/vadd_vx_tumu_rv64-2.C | 292 +++++++++ .../riscv/rvv/base/vadd_vx_tumu_rv64-3.C | 292 +++++++++ 30 files changed, 10422 insertions(+) create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_mu_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_mu_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_mu_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_mu_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_mu_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_mu_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_tu_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_tu_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_tu_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_tu_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_tu_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_tu_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_tum_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_tum_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_tum_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_tum_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_tum_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_tum_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_tumu_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_tumu_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_tumu_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_tumu_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_tumu_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_tumu_rv64-3.C diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_mu_rv32-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_mu_rv32-1.C new file mode 100644 index 00000000000..24c5d51a289 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_mu_rv32-1.C @@ -0,0 +1,289 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vadd_mu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,vl); +} + + +vint8mf4_t test___riscv_vadd_mu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,vl); +} + + +vint8mf2_t test___riscv_vadd_mu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,vl); +} + + +vint8m1_t test___riscv_vadd_mu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,vl); +} + + +vint8m2_t test___riscv_vadd_mu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,vl); +} + + +vint8m4_t test___riscv_vadd_mu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,vl); +} + + +vint8m8_t test___riscv_vadd_mu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,vl); +} + + +vint16mf4_t test___riscv_vadd_mu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,vl); +} + + +vint16mf2_t test___riscv_vadd_mu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,vl); +} + + +vint16m1_t test___riscv_vadd_mu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,vl); +} + + +vint16m2_t test___riscv_vadd_mu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,vl); +} + + +vint16m4_t test___riscv_vadd_mu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,vl); +} + + +vint16m8_t test___riscv_vadd_mu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,vl); +} + + +vint32mf2_t test___riscv_vadd_mu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,vl); +} + + +vint32m1_t test___riscv_vadd_mu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,vl); +} + + +vint32m2_t test___riscv_vadd_mu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,vl); +} + + +vint32m4_t test___riscv_vadd_mu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,vl); +} + + +vint32m8_t test___riscv_vadd_mu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,vl); +} + + +vint64m1_t test___riscv_vadd_mu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,vl); +} + + +vint64m2_t test___riscv_vadd_mu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,vl); +} + + +vint64m4_t test___riscv_vadd_mu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,vl); +} + + +vint64m8_t test___riscv_vadd_mu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,vl); +} + + +vuint8mf8_t test___riscv_vadd_mu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,vl); +} + + +vuint8mf4_t test___riscv_vadd_mu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,vl); +} + + +vuint8mf2_t test___riscv_vadd_mu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,vl); +} + + +vuint8m1_t test___riscv_vadd_mu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,vl); +} + + +vuint8m2_t test___riscv_vadd_mu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,vl); +} + + +vuint8m4_t test___riscv_vadd_mu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,vl); +} + + +vuint8m8_t test___riscv_vadd_mu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,vl); +} + + +vuint16mf4_t test___riscv_vadd_mu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,vl); +} + + +vuint16mf2_t test___riscv_vadd_mu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,vl); +} + + +vuint16m1_t test___riscv_vadd_mu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,vl); +} + + +vuint16m2_t test___riscv_vadd_mu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,vl); +} + + +vuint16m4_t test___riscv_vadd_mu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,vl); +} + + +vuint16m8_t test___riscv_vadd_mu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,vl); +} + + +vuint32mf2_t test___riscv_vadd_mu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,vl); +} + + +vuint32m1_t test___riscv_vadd_mu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,vl); +} + + +vuint32m2_t test___riscv_vadd_mu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,vl); +} + + +vuint32m4_t test___riscv_vadd_mu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,vl); +} + + +vuint32m8_t test___riscv_vadd_mu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,vl); +} + + +vuint64m1_t test___riscv_vadd_mu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,vl); +} + + +vuint64m2_t test___riscv_vadd_mu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,vl); +} + + +vuint64m4_t test___riscv_vadd_mu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,vl); +} + + +vuint64m8_t test___riscv_vadd_mu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 8 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_mu_rv32-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_mu_rv32-2.C new file mode 100644 index 00000000000..7f296881f5e --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_mu_rv32-2.C @@ -0,0 +1,289 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vadd_mu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,31); +} + + +vint8mf4_t test___riscv_vadd_mu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,31); +} + + +vint8mf2_t test___riscv_vadd_mu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,31); +} + + +vint8m1_t test___riscv_vadd_mu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,31); +} + + +vint8m2_t test___riscv_vadd_mu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,31); +} + + +vint8m4_t test___riscv_vadd_mu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,31); +} + + +vint8m8_t test___riscv_vadd_mu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,31); +} + + +vint16mf4_t test___riscv_vadd_mu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,31); +} + + +vint16mf2_t test___riscv_vadd_mu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,31); +} + + +vint16m1_t test___riscv_vadd_mu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,31); +} + + +vint16m2_t test___riscv_vadd_mu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,31); +} + + +vint16m4_t test___riscv_vadd_mu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,31); +} + + +vint16m8_t test___riscv_vadd_mu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,31); +} + + +vint32mf2_t test___riscv_vadd_mu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,31); +} + + +vint32m1_t test___riscv_vadd_mu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,31); +} + + +vint32m2_t test___riscv_vadd_mu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,31); +} + + +vint32m4_t test___riscv_vadd_mu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,31); +} + + +vint32m8_t test___riscv_vadd_mu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,31); +} + + +vint64m1_t test___riscv_vadd_mu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,31); +} + + +vint64m2_t test___riscv_vadd_mu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,31); +} + + +vint64m4_t test___riscv_vadd_mu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,31); +} + + +vint64m8_t test___riscv_vadd_mu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,31); +} + + +vuint8mf8_t test___riscv_vadd_mu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,31); +} + + +vuint8mf4_t test___riscv_vadd_mu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,31); +} + + +vuint8mf2_t test___riscv_vadd_mu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,31); +} + + +vuint8m1_t test___riscv_vadd_mu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,31); +} + + +vuint8m2_t test___riscv_vadd_mu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,31); +} + + +vuint8m4_t test___riscv_vadd_mu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,31); +} + + +vuint8m8_t test___riscv_vadd_mu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,31); +} + + +vuint16mf4_t test___riscv_vadd_mu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,31); +} + + +vuint16mf2_t test___riscv_vadd_mu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,31); +} + + +vuint16m1_t test___riscv_vadd_mu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,31); +} + + +vuint16m2_t test___riscv_vadd_mu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,31); +} + + +vuint16m4_t test___riscv_vadd_mu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,31); +} + + +vuint16m8_t test___riscv_vadd_mu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,31); +} + + +vuint32mf2_t test___riscv_vadd_mu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,31); +} + + +vuint32m1_t test___riscv_vadd_mu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,31); +} + + +vuint32m2_t test___riscv_vadd_mu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,31); +} + + +vuint32m4_t test___riscv_vadd_mu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,31); +} + + +vuint32m8_t test___riscv_vadd_mu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,31); +} + + +vuint64m1_t test___riscv_vadd_mu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,31); +} + + +vuint64m2_t test___riscv_vadd_mu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,31); +} + + +vuint64m4_t test___riscv_vadd_mu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,31); +} + + +vuint64m8_t test___riscv_vadd_mu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 8 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_mu_rv32-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_mu_rv32-3.C new file mode 100644 index 00000000000..f56c55a2154 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_mu_rv32-3.C @@ -0,0 +1,289 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vadd_mu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,32); +} + + +vint8mf4_t test___riscv_vadd_mu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,32); +} + + +vint8mf2_t test___riscv_vadd_mu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,32); +} + + +vint8m1_t test___riscv_vadd_mu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,32); +} + + +vint8m2_t test___riscv_vadd_mu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,32); +} + + +vint8m4_t test___riscv_vadd_mu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,32); +} + + +vint8m8_t test___riscv_vadd_mu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,32); +} + + +vint16mf4_t test___riscv_vadd_mu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,32); +} + + +vint16mf2_t test___riscv_vadd_mu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,32); +} + + +vint16m1_t test___riscv_vadd_mu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,32); +} + + +vint16m2_t test___riscv_vadd_mu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,32); +} + + +vint16m4_t test___riscv_vadd_mu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,32); +} + + +vint16m8_t test___riscv_vadd_mu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,32); +} + + +vint32mf2_t test___riscv_vadd_mu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,32); +} + + +vint32m1_t test___riscv_vadd_mu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,32); +} + + +vint32m2_t test___riscv_vadd_mu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,32); +} + + +vint32m4_t test___riscv_vadd_mu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,32); +} + + +vint32m8_t test___riscv_vadd_mu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,32); +} + + +vint64m1_t test___riscv_vadd_mu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,32); +} + + +vint64m2_t test___riscv_vadd_mu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,32); +} + + +vint64m4_t test___riscv_vadd_mu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,32); +} + + +vint64m8_t test___riscv_vadd_mu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,32); +} + + +vuint8mf8_t test___riscv_vadd_mu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,32); +} + + +vuint8mf4_t test___riscv_vadd_mu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,32); +} + + +vuint8mf2_t test___riscv_vadd_mu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,32); +} + + +vuint8m1_t test___riscv_vadd_mu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,32); +} + + +vuint8m2_t test___riscv_vadd_mu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,32); +} + + +vuint8m4_t test___riscv_vadd_mu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,32); +} + + +vuint8m8_t test___riscv_vadd_mu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,32); +} + + +vuint16mf4_t test___riscv_vadd_mu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,32); +} + + +vuint16mf2_t test___riscv_vadd_mu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,32); +} + + +vuint16m1_t test___riscv_vadd_mu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,32); +} + + +vuint16m2_t test___riscv_vadd_mu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,32); +} + + +vuint16m4_t test___riscv_vadd_mu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,32); +} + + +vuint16m8_t test___riscv_vadd_mu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,32); +} + + +vuint32mf2_t test___riscv_vadd_mu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,32); +} + + +vuint32m1_t test___riscv_vadd_mu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,32); +} + + +vuint32m2_t test___riscv_vadd_mu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,32); +} + + +vuint32m4_t test___riscv_vadd_mu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,32); +} + + +vuint32m8_t test___riscv_vadd_mu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,32); +} + + +vuint64m1_t test___riscv_vadd_mu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,32); +} + + +vuint64m2_t test___riscv_vadd_mu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,32); +} + + +vuint64m4_t test___riscv_vadd_mu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,32); +} + + +vuint64m8_t test___riscv_vadd_mu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 8 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_mu_rv64-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_mu_rv64-1.C new file mode 100644 index 00000000000..973751af9b8 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_mu_rv64-1.C @@ -0,0 +1,292 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vadd_mu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,vl); +} + + +vint8mf4_t test___riscv_vadd_mu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,vl); +} + + +vint8mf2_t test___riscv_vadd_mu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,vl); +} + + +vint8m1_t test___riscv_vadd_mu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,vl); +} + + +vint8m2_t test___riscv_vadd_mu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,vl); +} + + +vint8m4_t test___riscv_vadd_mu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,vl); +} + + +vint8m8_t test___riscv_vadd_mu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,vl); +} + + +vint16mf4_t test___riscv_vadd_mu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,vl); +} + + +vint16mf2_t test___riscv_vadd_mu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,vl); +} + + +vint16m1_t test___riscv_vadd_mu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,vl); +} + + +vint16m2_t test___riscv_vadd_mu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,vl); +} + + +vint16m4_t test___riscv_vadd_mu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,vl); +} + + +vint16m8_t test___riscv_vadd_mu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,vl); +} + + +vint32mf2_t test___riscv_vadd_mu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,vl); +} + + +vint32m1_t test___riscv_vadd_mu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,vl); +} + + +vint32m2_t test___riscv_vadd_mu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,vl); +} + + +vint32m4_t test___riscv_vadd_mu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,vl); +} + + +vint32m8_t test___riscv_vadd_mu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,vl); +} + + +vint64m1_t test___riscv_vadd_mu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,vl); +} + + +vint64m2_t test___riscv_vadd_mu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,vl); +} + + +vint64m4_t test___riscv_vadd_mu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,vl); +} + + +vint64m8_t test___riscv_vadd_mu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,vl); +} + + +vuint8mf8_t test___riscv_vadd_mu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,vl); +} + + +vuint8mf4_t test___riscv_vadd_mu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,vl); +} + + +vuint8mf2_t test___riscv_vadd_mu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,vl); +} + + +vuint8m1_t test___riscv_vadd_mu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,vl); +} + + +vuint8m2_t test___riscv_vadd_mu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,vl); +} + + +vuint8m4_t test___riscv_vadd_mu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,vl); +} + + +vuint8m8_t test___riscv_vadd_mu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,vl); +} + + +vuint16mf4_t test___riscv_vadd_mu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,vl); +} + + +vuint16mf2_t test___riscv_vadd_mu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,vl); +} + + +vuint16m1_t test___riscv_vadd_mu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,vl); +} + + +vuint16m2_t test___riscv_vadd_mu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,vl); +} + + +vuint16m4_t test___riscv_vadd_mu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,vl); +} + + +vuint16m8_t test___riscv_vadd_mu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,vl); +} + + +vuint32mf2_t test___riscv_vadd_mu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,vl); +} + + +vuint32m1_t test___riscv_vadd_mu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,vl); +} + + +vuint32m2_t test___riscv_vadd_mu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,vl); +} + + +vuint32m4_t test___riscv_vadd_mu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,vl); +} + + +vuint32m8_t test___riscv_vadd_mu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,vl); +} + + +vuint64m1_t test___riscv_vadd_mu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,vl); +} + + +vuint64m2_t test___riscv_vadd_mu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,vl); +} + + +vuint64m4_t test___riscv_vadd_mu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,vl); +} + + +vuint64m8_t test___riscv_vadd_mu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_mu_rv64-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_mu_rv64-2.C new file mode 100644 index 00000000000..23e5a4604ec --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_mu_rv64-2.C @@ -0,0 +1,292 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vadd_mu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,31); +} + + +vint8mf4_t test___riscv_vadd_mu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,31); +} + + +vint8mf2_t test___riscv_vadd_mu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,31); +} + + +vint8m1_t test___riscv_vadd_mu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,31); +} + + +vint8m2_t test___riscv_vadd_mu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,31); +} + + +vint8m4_t test___riscv_vadd_mu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,31); +} + + +vint8m8_t test___riscv_vadd_mu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,31); +} + + +vint16mf4_t test___riscv_vadd_mu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,31); +} + + +vint16mf2_t test___riscv_vadd_mu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,31); +} + + +vint16m1_t test___riscv_vadd_mu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,31); +} + + +vint16m2_t test___riscv_vadd_mu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,31); +} + + +vint16m4_t test___riscv_vadd_mu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,31); +} + + +vint16m8_t test___riscv_vadd_mu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,31); +} + + +vint32mf2_t test___riscv_vadd_mu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,31); +} + + +vint32m1_t test___riscv_vadd_mu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,31); +} + + +vint32m2_t test___riscv_vadd_mu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,31); +} + + +vint32m4_t test___riscv_vadd_mu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,31); +} + + +vint32m8_t test___riscv_vadd_mu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,31); +} + + +vint64m1_t test___riscv_vadd_mu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,31); +} + + +vint64m2_t test___riscv_vadd_mu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,31); +} + + +vint64m4_t test___riscv_vadd_mu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,31); +} + + +vint64m8_t test___riscv_vadd_mu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,31); +} + + +vuint8mf8_t test___riscv_vadd_mu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,31); +} + + +vuint8mf4_t test___riscv_vadd_mu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,31); +} + + +vuint8mf2_t test___riscv_vadd_mu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,31); +} + + +vuint8m1_t test___riscv_vadd_mu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,31); +} + + +vuint8m2_t test___riscv_vadd_mu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,31); +} + + +vuint8m4_t test___riscv_vadd_mu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,31); +} + + +vuint8m8_t test___riscv_vadd_mu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,31); +} + + +vuint16mf4_t test___riscv_vadd_mu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,31); +} + + +vuint16mf2_t test___riscv_vadd_mu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,31); +} + + +vuint16m1_t test___riscv_vadd_mu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,31); +} + + +vuint16m2_t test___riscv_vadd_mu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,31); +} + + +vuint16m4_t test___riscv_vadd_mu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,31); +} + + +vuint16m8_t test___riscv_vadd_mu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,31); +} + + +vuint32mf2_t test___riscv_vadd_mu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,31); +} + + +vuint32m1_t test___riscv_vadd_mu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,31); +} + + +vuint32m2_t test___riscv_vadd_mu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,31); +} + + +vuint32m4_t test___riscv_vadd_mu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,31); +} + + +vuint32m8_t test___riscv_vadd_mu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,31); +} + + +vuint64m1_t test___riscv_vadd_mu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,31); +} + + +vuint64m2_t test___riscv_vadd_mu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,31); +} + + +vuint64m4_t test___riscv_vadd_mu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,31); +} + + +vuint64m8_t test___riscv_vadd_mu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_mu_rv64-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_mu_rv64-3.C new file mode 100644 index 00000000000..d9addcc1676 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_mu_rv64-3.C @@ -0,0 +1,292 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vadd_mu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,32); +} + + +vint8mf4_t test___riscv_vadd_mu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,32); +} + + +vint8mf2_t test___riscv_vadd_mu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,32); +} + + +vint8m1_t test___riscv_vadd_mu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,32); +} + + +vint8m2_t test___riscv_vadd_mu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,32); +} + + +vint8m4_t test___riscv_vadd_mu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,32); +} + + +vint8m8_t test___riscv_vadd_mu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,32); +} + + +vint16mf4_t test___riscv_vadd_mu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,32); +} + + +vint16mf2_t test___riscv_vadd_mu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,32); +} + + +vint16m1_t test___riscv_vadd_mu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,32); +} + + +vint16m2_t test___riscv_vadd_mu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,32); +} + + +vint16m4_t test___riscv_vadd_mu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,32); +} + + +vint16m8_t test___riscv_vadd_mu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,32); +} + + +vint32mf2_t test___riscv_vadd_mu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,32); +} + + +vint32m1_t test___riscv_vadd_mu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,32); +} + + +vint32m2_t test___riscv_vadd_mu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,32); +} + + +vint32m4_t test___riscv_vadd_mu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,32); +} + + +vint32m8_t test___riscv_vadd_mu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,32); +} + + +vint64m1_t test___riscv_vadd_mu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,32); +} + + +vint64m2_t test___riscv_vadd_mu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,32); +} + + +vint64m4_t test___riscv_vadd_mu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,32); +} + + +vint64m8_t test___riscv_vadd_mu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,32); +} + + +vuint8mf8_t test___riscv_vadd_mu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,32); +} + + +vuint8mf4_t test___riscv_vadd_mu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,32); +} + + +vuint8mf2_t test___riscv_vadd_mu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,32); +} + + +vuint8m1_t test___riscv_vadd_mu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,32); +} + + +vuint8m2_t test___riscv_vadd_mu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,32); +} + + +vuint8m4_t test___riscv_vadd_mu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,32); +} + + +vuint8m8_t test___riscv_vadd_mu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,32); +} + + +vuint16mf4_t test___riscv_vadd_mu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,32); +} + + +vuint16mf2_t test___riscv_vadd_mu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,32); +} + + +vuint16m1_t test___riscv_vadd_mu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,32); +} + + +vuint16m2_t test___riscv_vadd_mu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,32); +} + + +vuint16m4_t test___riscv_vadd_mu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,32); +} + + +vuint16m8_t test___riscv_vadd_mu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,32); +} + + +vuint32mf2_t test___riscv_vadd_mu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,32); +} + + +vuint32m1_t test___riscv_vadd_mu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,32); +} + + +vuint32m2_t test___riscv_vadd_mu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,32); +} + + +vuint32m4_t test___riscv_vadd_mu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,32); +} + + +vuint32m8_t test___riscv_vadd_mu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,32); +} + + +vuint64m1_t test___riscv_vadd_mu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,32); +} + + +vuint64m2_t test___riscv_vadd_mu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,32); +} + + +vuint64m4_t test___riscv_vadd_mu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,32); +} + + +vuint64m8_t test___riscv_vadd_mu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_rv32-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_rv32-1.C new file mode 100644 index 00000000000..486d80fd2e4 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_rv32-1.C @@ -0,0 +1,572 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vadd(vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,vl); +} + + +vint8mf4_t test___riscv_vadd(vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,vl); +} + + +vint8mf2_t test___riscv_vadd(vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,vl); +} + + +vint8m1_t test___riscv_vadd(vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,vl); +} + + +vint8m2_t test___riscv_vadd(vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,vl); +} + + +vint8m4_t test___riscv_vadd(vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,vl); +} + + +vint8m8_t test___riscv_vadd(vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,vl); +} + + +vint16mf4_t test___riscv_vadd(vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,vl); +} + + +vint16mf2_t test___riscv_vadd(vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,vl); +} + + +vint16m1_t test___riscv_vadd(vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,vl); +} + + +vint16m2_t test___riscv_vadd(vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,vl); +} + + +vint16m4_t test___riscv_vadd(vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,vl); +} + + +vint16m8_t test___riscv_vadd(vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,vl); +} + + +vint32mf2_t test___riscv_vadd(vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,vl); +} + + +vint32m1_t test___riscv_vadd(vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,vl); +} + + +vint32m2_t test___riscv_vadd(vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,vl); +} + + +vint32m4_t test___riscv_vadd(vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,vl); +} + + +vint32m8_t test___riscv_vadd(vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,vl); +} + + +vint64m1_t test___riscv_vadd(vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,vl); +} + + +vint64m2_t test___riscv_vadd(vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,vl); +} + + +vint64m4_t test___riscv_vadd(vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,vl); +} + + +vint64m8_t test___riscv_vadd(vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,vl); +} + + +vuint8mf8_t test___riscv_vadd(vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,vl); +} + + +vuint8mf4_t test___riscv_vadd(vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,vl); +} + + +vuint8mf2_t test___riscv_vadd(vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,vl); +} + + +vuint8m1_t test___riscv_vadd(vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,vl); +} + + +vuint8m2_t test___riscv_vadd(vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,vl); +} + + +vuint8m4_t test___riscv_vadd(vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,vl); +} + + +vuint8m8_t test___riscv_vadd(vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,vl); +} + + +vuint16mf4_t test___riscv_vadd(vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,vl); +} + + +vuint16mf2_t test___riscv_vadd(vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,vl); +} + + +vuint16m1_t test___riscv_vadd(vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,vl); +} + + +vuint16m2_t test___riscv_vadd(vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,vl); +} + + +vuint16m4_t test___riscv_vadd(vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,vl); +} + + +vuint16m8_t test___riscv_vadd(vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,vl); +} + + +vuint32mf2_t test___riscv_vadd(vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,vl); +} + + +vuint32m1_t test___riscv_vadd(vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,vl); +} + + +vuint32m2_t test___riscv_vadd(vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,vl); +} + + +vuint32m4_t test___riscv_vadd(vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,vl); +} + + +vuint32m8_t test___riscv_vadd(vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,vl); +} + + +vuint64m1_t test___riscv_vadd(vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,vl); +} + + +vuint64m2_t test___riscv_vadd(vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,vl); +} + + +vuint64m4_t test___riscv_vadd(vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,vl); +} + + +vuint64m8_t test___riscv_vadd(vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,vl); +} + + +vint8mf8_t test___riscv_vadd(vbool64_t mask,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,vl); +} + + +vint8mf4_t test___riscv_vadd(vbool32_t mask,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,vl); +} + + +vint8mf2_t test___riscv_vadd(vbool16_t mask,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,vl); +} + + +vint8m1_t test___riscv_vadd(vbool8_t mask,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,vl); +} + + +vint8m2_t test___riscv_vadd(vbool4_t mask,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,vl); +} + + +vint8m4_t test___riscv_vadd(vbool2_t mask,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,vl); +} + + +vint8m8_t test___riscv_vadd(vbool1_t mask,vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,vl); +} + + +vint16mf4_t test___riscv_vadd(vbool64_t mask,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,vl); +} + + +vint16mf2_t test___riscv_vadd(vbool32_t mask,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,vl); +} + + +vint16m1_t test___riscv_vadd(vbool16_t mask,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,vl); +} + + +vint16m2_t test___riscv_vadd(vbool8_t mask,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,vl); +} + + +vint16m4_t test___riscv_vadd(vbool4_t mask,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,vl); +} + + +vint16m8_t test___riscv_vadd(vbool2_t mask,vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,vl); +} + + +vint32mf2_t test___riscv_vadd(vbool64_t mask,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,vl); +} + + +vint32m1_t test___riscv_vadd(vbool32_t mask,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,vl); +} + + +vint32m2_t test___riscv_vadd(vbool16_t mask,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,vl); +} + + +vint32m4_t test___riscv_vadd(vbool8_t mask,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,vl); +} + + +vint32m8_t test___riscv_vadd(vbool4_t mask,vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,vl); +} + + +vint64m1_t test___riscv_vadd(vbool64_t mask,vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,vl); +} + + +vint64m2_t test___riscv_vadd(vbool32_t mask,vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,vl); +} + + +vint64m4_t test___riscv_vadd(vbool16_t mask,vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,vl); +} + + +vint64m8_t test___riscv_vadd(vbool8_t mask,vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,vl); +} + + +vuint8mf8_t test___riscv_vadd(vbool64_t mask,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,vl); +} + + +vuint8mf4_t test___riscv_vadd(vbool32_t mask,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,vl); +} + + +vuint8mf2_t test___riscv_vadd(vbool16_t mask,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,vl); +} + + +vuint8m1_t test___riscv_vadd(vbool8_t mask,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,vl); +} + + +vuint8m2_t test___riscv_vadd(vbool4_t mask,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,vl); +} + + +vuint8m4_t test___riscv_vadd(vbool2_t mask,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,vl); +} + + +vuint8m8_t test___riscv_vadd(vbool1_t mask,vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,vl); +} + + +vuint16mf4_t test___riscv_vadd(vbool64_t mask,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,vl); +} + + +vuint16mf2_t test___riscv_vadd(vbool32_t mask,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,vl); +} + + +vuint16m1_t test___riscv_vadd(vbool16_t mask,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,vl); +} + + +vuint16m2_t test___riscv_vadd(vbool8_t mask,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,vl); +} + + +vuint16m4_t test___riscv_vadd(vbool4_t mask,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,vl); +} + + +vuint16m8_t test___riscv_vadd(vbool2_t mask,vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,vl); +} + + +vuint32mf2_t test___riscv_vadd(vbool64_t mask,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,vl); +} + + +vuint32m1_t test___riscv_vadd(vbool32_t mask,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,vl); +} + + +vuint32m2_t test___riscv_vadd(vbool16_t mask,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,vl); +} + + +vuint32m4_t test___riscv_vadd(vbool8_t mask,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,vl); +} + + +vuint32m8_t test___riscv_vadd(vbool4_t mask,vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,vl); +} + + +vuint64m1_t test___riscv_vadd(vbool64_t mask,vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,vl); +} + + +vuint64m2_t test___riscv_vadd(vbool32_t mask,vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,vl); +} + + +vuint64m4_t test___riscv_vadd(vbool16_t mask,vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,vl); +} + + +vuint64m8_t test___riscv_vadd(vbool8_t mask,vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 8 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 8 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_rv32-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_rv32-2.C new file mode 100644 index 00000000000..57df9c7b74e --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_rv32-2.C @@ -0,0 +1,572 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vadd(vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,31); +} + + +vint8mf4_t test___riscv_vadd(vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,31); +} + + +vint8mf2_t test___riscv_vadd(vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,31); +} + + +vint8m1_t test___riscv_vadd(vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,31); +} + + +vint8m2_t test___riscv_vadd(vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,31); +} + + +vint8m4_t test___riscv_vadd(vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,31); +} + + +vint8m8_t test___riscv_vadd(vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,31); +} + + +vint16mf4_t test___riscv_vadd(vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,31); +} + + +vint16mf2_t test___riscv_vadd(vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,31); +} + + +vint16m1_t test___riscv_vadd(vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,31); +} + + +vint16m2_t test___riscv_vadd(vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,31); +} + + +vint16m4_t test___riscv_vadd(vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,31); +} + + +vint16m8_t test___riscv_vadd(vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,31); +} + + +vint32mf2_t test___riscv_vadd(vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,31); +} + + +vint32m1_t test___riscv_vadd(vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,31); +} + + +vint32m2_t test___riscv_vadd(vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,31); +} + + +vint32m4_t test___riscv_vadd(vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,31); +} + + +vint32m8_t test___riscv_vadd(vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,31); +} + + +vint64m1_t test___riscv_vadd(vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,31); +} + + +vint64m2_t test___riscv_vadd(vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,31); +} + + +vint64m4_t test___riscv_vadd(vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,31); +} + + +vint64m8_t test___riscv_vadd(vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,31); +} + + +vuint8mf8_t test___riscv_vadd(vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,31); +} + + +vuint8mf4_t test___riscv_vadd(vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,31); +} + + +vuint8mf2_t test___riscv_vadd(vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,31); +} + + +vuint8m1_t test___riscv_vadd(vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,31); +} + + +vuint8m2_t test___riscv_vadd(vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,31); +} + + +vuint8m4_t test___riscv_vadd(vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,31); +} + + +vuint8m8_t test___riscv_vadd(vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,31); +} + + +vuint16mf4_t test___riscv_vadd(vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,31); +} + + +vuint16mf2_t test___riscv_vadd(vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,31); +} + + +vuint16m1_t test___riscv_vadd(vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,31); +} + + +vuint16m2_t test___riscv_vadd(vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,31); +} + + +vuint16m4_t test___riscv_vadd(vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,31); +} + + +vuint16m8_t test___riscv_vadd(vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,31); +} + + +vuint32mf2_t test___riscv_vadd(vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,31); +} + + +vuint32m1_t test___riscv_vadd(vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,31); +} + + +vuint32m2_t test___riscv_vadd(vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,31); +} + + +vuint32m4_t test___riscv_vadd(vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,31); +} + + +vuint32m8_t test___riscv_vadd(vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,31); +} + + +vuint64m1_t test___riscv_vadd(vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,31); +} + + +vuint64m2_t test___riscv_vadd(vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,31); +} + + +vuint64m4_t test___riscv_vadd(vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,31); +} + + +vuint64m8_t test___riscv_vadd(vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,31); +} + + +vint8mf8_t test___riscv_vadd(vbool64_t mask,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,31); +} + + +vint8mf4_t test___riscv_vadd(vbool32_t mask,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,31); +} + + +vint8mf2_t test___riscv_vadd(vbool16_t mask,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,31); +} + + +vint8m1_t test___riscv_vadd(vbool8_t mask,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,31); +} + + +vint8m2_t test___riscv_vadd(vbool4_t mask,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,31); +} + + +vint8m4_t test___riscv_vadd(vbool2_t mask,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,31); +} + + +vint8m8_t test___riscv_vadd(vbool1_t mask,vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,31); +} + + +vint16mf4_t test___riscv_vadd(vbool64_t mask,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,31); +} + + +vint16mf2_t test___riscv_vadd(vbool32_t mask,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,31); +} + + +vint16m1_t test___riscv_vadd(vbool16_t mask,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,31); +} + + +vint16m2_t test___riscv_vadd(vbool8_t mask,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,31); +} + + +vint16m4_t test___riscv_vadd(vbool4_t mask,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,31); +} + + +vint16m8_t test___riscv_vadd(vbool2_t mask,vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,31); +} + + +vint32mf2_t test___riscv_vadd(vbool64_t mask,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,31); +} + + +vint32m1_t test___riscv_vadd(vbool32_t mask,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,31); +} + + +vint32m2_t test___riscv_vadd(vbool16_t mask,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,31); +} + + +vint32m4_t test___riscv_vadd(vbool8_t mask,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,31); +} + + +vint32m8_t test___riscv_vadd(vbool4_t mask,vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,31); +} + + +vint64m1_t test___riscv_vadd(vbool64_t mask,vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,31); +} + + +vint64m2_t test___riscv_vadd(vbool32_t mask,vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,31); +} + + +vint64m4_t test___riscv_vadd(vbool16_t mask,vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,31); +} + + +vint64m8_t test___riscv_vadd(vbool8_t mask,vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,31); +} + + +vuint8mf8_t test___riscv_vadd(vbool64_t mask,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,31); +} + + +vuint8mf4_t test___riscv_vadd(vbool32_t mask,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,31); +} + + +vuint8mf2_t test___riscv_vadd(vbool16_t mask,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,31); +} + + +vuint8m1_t test___riscv_vadd(vbool8_t mask,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,31); +} + + +vuint8m2_t test___riscv_vadd(vbool4_t mask,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,31); +} + + +vuint8m4_t test___riscv_vadd(vbool2_t mask,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,31); +} + + +vuint8m8_t test___riscv_vadd(vbool1_t mask,vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,31); +} + + +vuint16mf4_t test___riscv_vadd(vbool64_t mask,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,31); +} + + +vuint16mf2_t test___riscv_vadd(vbool32_t mask,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,31); +} + + +vuint16m1_t test___riscv_vadd(vbool16_t mask,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,31); +} + + +vuint16m2_t test___riscv_vadd(vbool8_t mask,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,31); +} + + +vuint16m4_t test___riscv_vadd(vbool4_t mask,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,31); +} + + +vuint16m8_t test___riscv_vadd(vbool2_t mask,vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,31); +} + + +vuint32mf2_t test___riscv_vadd(vbool64_t mask,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,31); +} + + +vuint32m1_t test___riscv_vadd(vbool32_t mask,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,31); +} + + +vuint32m2_t test___riscv_vadd(vbool16_t mask,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,31); +} + + +vuint32m4_t test___riscv_vadd(vbool8_t mask,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,31); +} + + +vuint32m8_t test___riscv_vadd(vbool4_t mask,vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,31); +} + + +vuint64m1_t test___riscv_vadd(vbool64_t mask,vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,31); +} + + +vuint64m2_t test___riscv_vadd(vbool32_t mask,vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,31); +} + + +vuint64m4_t test___riscv_vadd(vbool16_t mask,vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,31); +} + + +vuint64m8_t test___riscv_vadd(vbool8_t mask,vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 8 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 8 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_rv32-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_rv32-3.C new file mode 100644 index 00000000000..5b3fc3da4f5 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_rv32-3.C @@ -0,0 +1,572 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vadd(vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,32); +} + + +vint8mf4_t test___riscv_vadd(vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,32); +} + + +vint8mf2_t test___riscv_vadd(vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,32); +} + + +vint8m1_t test___riscv_vadd(vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,32); +} + + +vint8m2_t test___riscv_vadd(vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,32); +} + + +vint8m4_t test___riscv_vadd(vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,32); +} + + +vint8m8_t test___riscv_vadd(vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,32); +} + + +vint16mf4_t test___riscv_vadd(vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,32); +} + + +vint16mf2_t test___riscv_vadd(vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,32); +} + + +vint16m1_t test___riscv_vadd(vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,32); +} + + +vint16m2_t test___riscv_vadd(vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,32); +} + + +vint16m4_t test___riscv_vadd(vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,32); +} + + +vint16m8_t test___riscv_vadd(vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,32); +} + + +vint32mf2_t test___riscv_vadd(vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,32); +} + + +vint32m1_t test___riscv_vadd(vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,32); +} + + +vint32m2_t test___riscv_vadd(vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,32); +} + + +vint32m4_t test___riscv_vadd(vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,32); +} + + +vint32m8_t test___riscv_vadd(vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,32); +} + + +vint64m1_t test___riscv_vadd(vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,32); +} + + +vint64m2_t test___riscv_vadd(vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,32); +} + + +vint64m4_t test___riscv_vadd(vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,32); +} + + +vint64m8_t test___riscv_vadd(vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,32); +} + + +vuint8mf8_t test___riscv_vadd(vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,32); +} + + +vuint8mf4_t test___riscv_vadd(vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,32); +} + + +vuint8mf2_t test___riscv_vadd(vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,32); +} + + +vuint8m1_t test___riscv_vadd(vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,32); +} + + +vuint8m2_t test___riscv_vadd(vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,32); +} + + +vuint8m4_t test___riscv_vadd(vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,32); +} + + +vuint8m8_t test___riscv_vadd(vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,32); +} + + +vuint16mf4_t test___riscv_vadd(vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,32); +} + + +vuint16mf2_t test___riscv_vadd(vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,32); +} + + +vuint16m1_t test___riscv_vadd(vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,32); +} + + +vuint16m2_t test___riscv_vadd(vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,32); +} + + +vuint16m4_t test___riscv_vadd(vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,32); +} + + +vuint16m8_t test___riscv_vadd(vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,32); +} + + +vuint32mf2_t test___riscv_vadd(vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,32); +} + + +vuint32m1_t test___riscv_vadd(vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,32); +} + + +vuint32m2_t test___riscv_vadd(vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,32); +} + + +vuint32m4_t test___riscv_vadd(vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,32); +} + + +vuint32m8_t test___riscv_vadd(vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,32); +} + + +vuint64m1_t test___riscv_vadd(vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,32); +} + + +vuint64m2_t test___riscv_vadd(vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,32); +} + + +vuint64m4_t test___riscv_vadd(vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,32); +} + + +vuint64m8_t test___riscv_vadd(vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,32); +} + + +vint8mf8_t test___riscv_vadd(vbool64_t mask,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,32); +} + + +vint8mf4_t test___riscv_vadd(vbool32_t mask,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,32); +} + + +vint8mf2_t test___riscv_vadd(vbool16_t mask,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,32); +} + + +vint8m1_t test___riscv_vadd(vbool8_t mask,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,32); +} + + +vint8m2_t test___riscv_vadd(vbool4_t mask,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,32); +} + + +vint8m4_t test___riscv_vadd(vbool2_t mask,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,32); +} + + +vint8m8_t test___riscv_vadd(vbool1_t mask,vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,32); +} + + +vint16mf4_t test___riscv_vadd(vbool64_t mask,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,32); +} + + +vint16mf2_t test___riscv_vadd(vbool32_t mask,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,32); +} + + +vint16m1_t test___riscv_vadd(vbool16_t mask,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,32); +} + + +vint16m2_t test___riscv_vadd(vbool8_t mask,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,32); +} + + +vint16m4_t test___riscv_vadd(vbool4_t mask,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,32); +} + + +vint16m8_t test___riscv_vadd(vbool2_t mask,vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,32); +} + + +vint32mf2_t test___riscv_vadd(vbool64_t mask,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,32); +} + + +vint32m1_t test___riscv_vadd(vbool32_t mask,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,32); +} + + +vint32m2_t test___riscv_vadd(vbool16_t mask,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,32); +} + + +vint32m4_t test___riscv_vadd(vbool8_t mask,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,32); +} + + +vint32m8_t test___riscv_vadd(vbool4_t mask,vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,32); +} + + +vint64m1_t test___riscv_vadd(vbool64_t mask,vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,32); +} + + +vint64m2_t test___riscv_vadd(vbool32_t mask,vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,32); +} + + +vint64m4_t test___riscv_vadd(vbool16_t mask,vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,32); +} + + +vint64m8_t test___riscv_vadd(vbool8_t mask,vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,32); +} + + +vuint8mf8_t test___riscv_vadd(vbool64_t mask,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,32); +} + + +vuint8mf4_t test___riscv_vadd(vbool32_t mask,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,32); +} + + +vuint8mf2_t test___riscv_vadd(vbool16_t mask,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,32); +} + + +vuint8m1_t test___riscv_vadd(vbool8_t mask,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,32); +} + + +vuint8m2_t test___riscv_vadd(vbool4_t mask,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,32); +} + + +vuint8m4_t test___riscv_vadd(vbool2_t mask,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,32); +} + + +vuint8m8_t test___riscv_vadd(vbool1_t mask,vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,32); +} + + +vuint16mf4_t test___riscv_vadd(vbool64_t mask,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,32); +} + + +vuint16mf2_t test___riscv_vadd(vbool32_t mask,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,32); +} + + +vuint16m1_t test___riscv_vadd(vbool16_t mask,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,32); +} + + +vuint16m2_t test___riscv_vadd(vbool8_t mask,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,32); +} + + +vuint16m4_t test___riscv_vadd(vbool4_t mask,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,32); +} + + +vuint16m8_t test___riscv_vadd(vbool2_t mask,vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,32); +} + + +vuint32mf2_t test___riscv_vadd(vbool64_t mask,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,32); +} + + +vuint32m1_t test___riscv_vadd(vbool32_t mask,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,32); +} + + +vuint32m2_t test___riscv_vadd(vbool16_t mask,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,32); +} + + +vuint32m4_t test___riscv_vadd(vbool8_t mask,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,32); +} + + +vuint32m8_t test___riscv_vadd(vbool4_t mask,vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,32); +} + + +vuint64m1_t test___riscv_vadd(vbool64_t mask,vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,32); +} + + +vuint64m2_t test___riscv_vadd(vbool32_t mask,vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,32); +} + + +vuint64m4_t test___riscv_vadd(vbool16_t mask,vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,32); +} + + +vuint64m8_t test___riscv_vadd(vbool8_t mask,vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 8 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 8 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_rv64-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_rv64-1.C new file mode 100644 index 00000000000..0d52c4ac0a4 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_rv64-1.C @@ -0,0 +1,578 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vadd(vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,vl); +} + + +vint8mf4_t test___riscv_vadd(vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,vl); +} + + +vint8mf2_t test___riscv_vadd(vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,vl); +} + + +vint8m1_t test___riscv_vadd(vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,vl); +} + + +vint8m2_t test___riscv_vadd(vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,vl); +} + + +vint8m4_t test___riscv_vadd(vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,vl); +} + + +vint8m8_t test___riscv_vadd(vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,vl); +} + + +vint16mf4_t test___riscv_vadd(vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,vl); +} + + +vint16mf2_t test___riscv_vadd(vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,vl); +} + + +vint16m1_t test___riscv_vadd(vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,vl); +} + + +vint16m2_t test___riscv_vadd(vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,vl); +} + + +vint16m4_t test___riscv_vadd(vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,vl); +} + + +vint16m8_t test___riscv_vadd(vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,vl); +} + + +vint32mf2_t test___riscv_vadd(vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,vl); +} + + +vint32m1_t test___riscv_vadd(vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,vl); +} + + +vint32m2_t test___riscv_vadd(vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,vl); +} + + +vint32m4_t test___riscv_vadd(vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,vl); +} + + +vint32m8_t test___riscv_vadd(vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,vl); +} + + +vint64m1_t test___riscv_vadd(vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,vl); +} + + +vint64m2_t test___riscv_vadd(vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,vl); +} + + +vint64m4_t test___riscv_vadd(vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,vl); +} + + +vint64m8_t test___riscv_vadd(vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,vl); +} + + +vuint8mf8_t test___riscv_vadd(vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,vl); +} + + +vuint8mf4_t test___riscv_vadd(vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,vl); +} + + +vuint8mf2_t test___riscv_vadd(vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,vl); +} + + +vuint8m1_t test___riscv_vadd(vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,vl); +} + + +vuint8m2_t test___riscv_vadd(vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,vl); +} + + +vuint8m4_t test___riscv_vadd(vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,vl); +} + + +vuint8m8_t test___riscv_vadd(vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,vl); +} + + +vuint16mf4_t test___riscv_vadd(vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,vl); +} + + +vuint16mf2_t test___riscv_vadd(vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,vl); +} + + +vuint16m1_t test___riscv_vadd(vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,vl); +} + + +vuint16m2_t test___riscv_vadd(vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,vl); +} + + +vuint16m4_t test___riscv_vadd(vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,vl); +} + + +vuint16m8_t test___riscv_vadd(vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,vl); +} + + +vuint32mf2_t test___riscv_vadd(vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,vl); +} + + +vuint32m1_t test___riscv_vadd(vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,vl); +} + + +vuint32m2_t test___riscv_vadd(vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,vl); +} + + +vuint32m4_t test___riscv_vadd(vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,vl); +} + + +vuint32m8_t test___riscv_vadd(vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,vl); +} + + +vuint64m1_t test___riscv_vadd(vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,vl); +} + + +vuint64m2_t test___riscv_vadd(vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,vl); +} + + +vuint64m4_t test___riscv_vadd(vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,vl); +} + + +vuint64m8_t test___riscv_vadd(vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,vl); +} + + +vint8mf8_t test___riscv_vadd(vbool64_t mask,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,vl); +} + + +vint8mf4_t test___riscv_vadd(vbool32_t mask,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,vl); +} + + +vint8mf2_t test___riscv_vadd(vbool16_t mask,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,vl); +} + + +vint8m1_t test___riscv_vadd(vbool8_t mask,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,vl); +} + + +vint8m2_t test___riscv_vadd(vbool4_t mask,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,vl); +} + + +vint8m4_t test___riscv_vadd(vbool2_t mask,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,vl); +} + + +vint8m8_t test___riscv_vadd(vbool1_t mask,vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,vl); +} + + +vint16mf4_t test___riscv_vadd(vbool64_t mask,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,vl); +} + + +vint16mf2_t test___riscv_vadd(vbool32_t mask,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,vl); +} + + +vint16m1_t test___riscv_vadd(vbool16_t mask,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,vl); +} + + +vint16m2_t test___riscv_vadd(vbool8_t mask,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,vl); +} + + +vint16m4_t test___riscv_vadd(vbool4_t mask,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,vl); +} + + +vint16m8_t test___riscv_vadd(vbool2_t mask,vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,vl); +} + + +vint32mf2_t test___riscv_vadd(vbool64_t mask,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,vl); +} + + +vint32m1_t test___riscv_vadd(vbool32_t mask,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,vl); +} + + +vint32m2_t test___riscv_vadd(vbool16_t mask,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,vl); +} + + +vint32m4_t test___riscv_vadd(vbool8_t mask,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,vl); +} + + +vint32m8_t test___riscv_vadd(vbool4_t mask,vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,vl); +} + + +vint64m1_t test___riscv_vadd(vbool64_t mask,vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,vl); +} + + +vint64m2_t test___riscv_vadd(vbool32_t mask,vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,vl); +} + + +vint64m4_t test___riscv_vadd(vbool16_t mask,vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,vl); +} + + +vint64m8_t test___riscv_vadd(vbool8_t mask,vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,vl); +} + + +vuint8mf8_t test___riscv_vadd(vbool64_t mask,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,vl); +} + + +vuint8mf4_t test___riscv_vadd(vbool32_t mask,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,vl); +} + + +vuint8mf2_t test___riscv_vadd(vbool16_t mask,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,vl); +} + + +vuint8m1_t test___riscv_vadd(vbool8_t mask,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,vl); +} + + +vuint8m2_t test___riscv_vadd(vbool4_t mask,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,vl); +} + + +vuint8m4_t test___riscv_vadd(vbool2_t mask,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,vl); +} + + +vuint8m8_t test___riscv_vadd(vbool1_t mask,vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,vl); +} + + +vuint16mf4_t test___riscv_vadd(vbool64_t mask,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,vl); +} + + +vuint16mf2_t test___riscv_vadd(vbool32_t mask,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,vl); +} + + +vuint16m1_t test___riscv_vadd(vbool16_t mask,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,vl); +} + + +vuint16m2_t test___riscv_vadd(vbool8_t mask,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,vl); +} + + +vuint16m4_t test___riscv_vadd(vbool4_t mask,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,vl); +} + + +vuint16m8_t test___riscv_vadd(vbool2_t mask,vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,vl); +} + + +vuint32mf2_t test___riscv_vadd(vbool64_t mask,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,vl); +} + + +vuint32m1_t test___riscv_vadd(vbool32_t mask,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,vl); +} + + +vuint32m2_t test___riscv_vadd(vbool16_t mask,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,vl); +} + + +vuint32m4_t test___riscv_vadd(vbool8_t mask,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,vl); +} + + +vuint32m8_t test___riscv_vadd(vbool4_t mask,vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,vl); +} + + +vuint64m1_t test___riscv_vadd(vbool64_t mask,vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,vl); +} + + +vuint64m2_t test___riscv_vadd(vbool32_t mask,vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,vl); +} + + +vuint64m4_t test___riscv_vadd(vbool16_t mask,vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,vl); +} + + +vuint64m8_t test___riscv_vadd(vbool8_t mask,vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_rv64-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_rv64-2.C new file mode 100644 index 00000000000..cbed2852b82 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_rv64-2.C @@ -0,0 +1,578 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vadd(vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,31); +} + + +vint8mf4_t test___riscv_vadd(vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,31); +} + + +vint8mf2_t test___riscv_vadd(vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,31); +} + + +vint8m1_t test___riscv_vadd(vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,31); +} + + +vint8m2_t test___riscv_vadd(vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,31); +} + + +vint8m4_t test___riscv_vadd(vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,31); +} + + +vint8m8_t test___riscv_vadd(vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,31); +} + + +vint16mf4_t test___riscv_vadd(vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,31); +} + + +vint16mf2_t test___riscv_vadd(vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,31); +} + + +vint16m1_t test___riscv_vadd(vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,31); +} + + +vint16m2_t test___riscv_vadd(vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,31); +} + + +vint16m4_t test___riscv_vadd(vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,31); +} + + +vint16m8_t test___riscv_vadd(vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,31); +} + + +vint32mf2_t test___riscv_vadd(vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,31); +} + + +vint32m1_t test___riscv_vadd(vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,31); +} + + +vint32m2_t test___riscv_vadd(vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,31); +} + + +vint32m4_t test___riscv_vadd(vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,31); +} + + +vint32m8_t test___riscv_vadd(vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,31); +} + + +vint64m1_t test___riscv_vadd(vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,31); +} + + +vint64m2_t test___riscv_vadd(vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,31); +} + + +vint64m4_t test___riscv_vadd(vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,31); +} + + +vint64m8_t test___riscv_vadd(vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,31); +} + + +vuint8mf8_t test___riscv_vadd(vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,31); +} + + +vuint8mf4_t test___riscv_vadd(vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,31); +} + + +vuint8mf2_t test___riscv_vadd(vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,31); +} + + +vuint8m1_t test___riscv_vadd(vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,31); +} + + +vuint8m2_t test___riscv_vadd(vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,31); +} + + +vuint8m4_t test___riscv_vadd(vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,31); +} + + +vuint8m8_t test___riscv_vadd(vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,31); +} + + +vuint16mf4_t test___riscv_vadd(vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,31); +} + + +vuint16mf2_t test___riscv_vadd(vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,31); +} + + +vuint16m1_t test___riscv_vadd(vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,31); +} + + +vuint16m2_t test___riscv_vadd(vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,31); +} + + +vuint16m4_t test___riscv_vadd(vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,31); +} + + +vuint16m8_t test___riscv_vadd(vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,31); +} + + +vuint32mf2_t test___riscv_vadd(vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,31); +} + + +vuint32m1_t test___riscv_vadd(vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,31); +} + + +vuint32m2_t test___riscv_vadd(vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,31); +} + + +vuint32m4_t test___riscv_vadd(vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,31); +} + + +vuint32m8_t test___riscv_vadd(vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,31); +} + + +vuint64m1_t test___riscv_vadd(vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,31); +} + + +vuint64m2_t test___riscv_vadd(vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,31); +} + + +vuint64m4_t test___riscv_vadd(vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,31); +} + + +vuint64m8_t test___riscv_vadd(vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,31); +} + + +vint8mf8_t test___riscv_vadd(vbool64_t mask,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,31); +} + + +vint8mf4_t test___riscv_vadd(vbool32_t mask,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,31); +} + + +vint8mf2_t test___riscv_vadd(vbool16_t mask,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,31); +} + + +vint8m1_t test___riscv_vadd(vbool8_t mask,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,31); +} + + +vint8m2_t test___riscv_vadd(vbool4_t mask,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,31); +} + + +vint8m4_t test___riscv_vadd(vbool2_t mask,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,31); +} + + +vint8m8_t test___riscv_vadd(vbool1_t mask,vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,31); +} + + +vint16mf4_t test___riscv_vadd(vbool64_t mask,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,31); +} + + +vint16mf2_t test___riscv_vadd(vbool32_t mask,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,31); +} + + +vint16m1_t test___riscv_vadd(vbool16_t mask,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,31); +} + + +vint16m2_t test___riscv_vadd(vbool8_t mask,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,31); +} + + +vint16m4_t test___riscv_vadd(vbool4_t mask,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,31); +} + + +vint16m8_t test___riscv_vadd(vbool2_t mask,vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,31); +} + + +vint32mf2_t test___riscv_vadd(vbool64_t mask,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,31); +} + + +vint32m1_t test___riscv_vadd(vbool32_t mask,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,31); +} + + +vint32m2_t test___riscv_vadd(vbool16_t mask,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,31); +} + + +vint32m4_t test___riscv_vadd(vbool8_t mask,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,31); +} + + +vint32m8_t test___riscv_vadd(vbool4_t mask,vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,31); +} + + +vint64m1_t test___riscv_vadd(vbool64_t mask,vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,31); +} + + +vint64m2_t test___riscv_vadd(vbool32_t mask,vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,31); +} + + +vint64m4_t test___riscv_vadd(vbool16_t mask,vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,31); +} + + +vint64m8_t test___riscv_vadd(vbool8_t mask,vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,31); +} + + +vuint8mf8_t test___riscv_vadd(vbool64_t mask,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,31); +} + + +vuint8mf4_t test___riscv_vadd(vbool32_t mask,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,31); +} + + +vuint8mf2_t test___riscv_vadd(vbool16_t mask,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,31); +} + + +vuint8m1_t test___riscv_vadd(vbool8_t mask,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,31); +} + + +vuint8m2_t test___riscv_vadd(vbool4_t mask,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,31); +} + + +vuint8m4_t test___riscv_vadd(vbool2_t mask,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,31); +} + + +vuint8m8_t test___riscv_vadd(vbool1_t mask,vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,31); +} + + +vuint16mf4_t test___riscv_vadd(vbool64_t mask,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,31); +} + + +vuint16mf2_t test___riscv_vadd(vbool32_t mask,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,31); +} + + +vuint16m1_t test___riscv_vadd(vbool16_t mask,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,31); +} + + +vuint16m2_t test___riscv_vadd(vbool8_t mask,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,31); +} + + +vuint16m4_t test___riscv_vadd(vbool4_t mask,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,31); +} + + +vuint16m8_t test___riscv_vadd(vbool2_t mask,vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,31); +} + + +vuint32mf2_t test___riscv_vadd(vbool64_t mask,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,31); +} + + +vuint32m1_t test___riscv_vadd(vbool32_t mask,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,31); +} + + +vuint32m2_t test___riscv_vadd(vbool16_t mask,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,31); +} + + +vuint32m4_t test___riscv_vadd(vbool8_t mask,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,31); +} + + +vuint32m8_t test___riscv_vadd(vbool4_t mask,vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,31); +} + + +vuint64m1_t test___riscv_vadd(vbool64_t mask,vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,31); +} + + +vuint64m2_t test___riscv_vadd(vbool32_t mask,vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,31); +} + + +vuint64m4_t test___riscv_vadd(vbool16_t mask,vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,31); +} + + +vuint64m8_t test___riscv_vadd(vbool8_t mask,vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_rv64-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_rv64-3.C new file mode 100644 index 00000000000..a1f5e590443 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_rv64-3.C @@ -0,0 +1,578 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vadd(vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,32); +} + + +vint8mf4_t test___riscv_vadd(vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,32); +} + + +vint8mf2_t test___riscv_vadd(vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,32); +} + + +vint8m1_t test___riscv_vadd(vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,32); +} + + +vint8m2_t test___riscv_vadd(vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,32); +} + + +vint8m4_t test___riscv_vadd(vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,32); +} + + +vint8m8_t test___riscv_vadd(vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,32); +} + + +vint16mf4_t test___riscv_vadd(vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,32); +} + + +vint16mf2_t test___riscv_vadd(vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,32); +} + + +vint16m1_t test___riscv_vadd(vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,32); +} + + +vint16m2_t test___riscv_vadd(vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,32); +} + + +vint16m4_t test___riscv_vadd(vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,32); +} + + +vint16m8_t test___riscv_vadd(vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,32); +} + + +vint32mf2_t test___riscv_vadd(vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,32); +} + + +vint32m1_t test___riscv_vadd(vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,32); +} + + +vint32m2_t test___riscv_vadd(vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,32); +} + + +vint32m4_t test___riscv_vadd(vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,32); +} + + +vint32m8_t test___riscv_vadd(vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,32); +} + + +vint64m1_t test___riscv_vadd(vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,32); +} + + +vint64m2_t test___riscv_vadd(vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,32); +} + + +vint64m4_t test___riscv_vadd(vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,32); +} + + +vint64m8_t test___riscv_vadd(vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,32); +} + + +vuint8mf8_t test___riscv_vadd(vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,32); +} + + +vuint8mf4_t test___riscv_vadd(vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,32); +} + + +vuint8mf2_t test___riscv_vadd(vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,32); +} + + +vuint8m1_t test___riscv_vadd(vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,32); +} + + +vuint8m2_t test___riscv_vadd(vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,32); +} + + +vuint8m4_t test___riscv_vadd(vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,32); +} + + +vuint8m8_t test___riscv_vadd(vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,32); +} + + +vuint16mf4_t test___riscv_vadd(vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,32); +} + + +vuint16mf2_t test___riscv_vadd(vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,32); +} + + +vuint16m1_t test___riscv_vadd(vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,32); +} + + +vuint16m2_t test___riscv_vadd(vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,32); +} + + +vuint16m4_t test___riscv_vadd(vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,32); +} + + +vuint16m8_t test___riscv_vadd(vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,32); +} + + +vuint32mf2_t test___riscv_vadd(vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,32); +} + + +vuint32m1_t test___riscv_vadd(vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,32); +} + + +vuint32m2_t test___riscv_vadd(vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,32); +} + + +vuint32m4_t test___riscv_vadd(vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,32); +} + + +vuint32m8_t test___riscv_vadd(vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,32); +} + + +vuint64m1_t test___riscv_vadd(vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,32); +} + + +vuint64m2_t test___riscv_vadd(vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,32); +} + + +vuint64m4_t test___riscv_vadd(vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,32); +} + + +vuint64m8_t test___riscv_vadd(vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,32); +} + + +vint8mf8_t test___riscv_vadd(vbool64_t mask,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,32); +} + + +vint8mf4_t test___riscv_vadd(vbool32_t mask,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,32); +} + + +vint8mf2_t test___riscv_vadd(vbool16_t mask,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,32); +} + + +vint8m1_t test___riscv_vadd(vbool8_t mask,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,32); +} + + +vint8m2_t test___riscv_vadd(vbool4_t mask,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,32); +} + + +vint8m4_t test___riscv_vadd(vbool2_t mask,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,32); +} + + +vint8m8_t test___riscv_vadd(vbool1_t mask,vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,32); +} + + +vint16mf4_t test___riscv_vadd(vbool64_t mask,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,32); +} + + +vint16mf2_t test___riscv_vadd(vbool32_t mask,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,32); +} + + +vint16m1_t test___riscv_vadd(vbool16_t mask,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,32); +} + + +vint16m2_t test___riscv_vadd(vbool8_t mask,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,32); +} + + +vint16m4_t test___riscv_vadd(vbool4_t mask,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,32); +} + + +vint16m8_t test___riscv_vadd(vbool2_t mask,vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,32); +} + + +vint32mf2_t test___riscv_vadd(vbool64_t mask,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,32); +} + + +vint32m1_t test___riscv_vadd(vbool32_t mask,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,32); +} + + +vint32m2_t test___riscv_vadd(vbool16_t mask,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,32); +} + + +vint32m4_t test___riscv_vadd(vbool8_t mask,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,32); +} + + +vint32m8_t test___riscv_vadd(vbool4_t mask,vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,32); +} + + +vint64m1_t test___riscv_vadd(vbool64_t mask,vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,32); +} + + +vint64m2_t test___riscv_vadd(vbool32_t mask,vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,32); +} + + +vint64m4_t test___riscv_vadd(vbool16_t mask,vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,32); +} + + +vint64m8_t test___riscv_vadd(vbool8_t mask,vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,32); +} + + +vuint8mf8_t test___riscv_vadd(vbool64_t mask,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,32); +} + + +vuint8mf4_t test___riscv_vadd(vbool32_t mask,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,32); +} + + +vuint8mf2_t test___riscv_vadd(vbool16_t mask,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,32); +} + + +vuint8m1_t test___riscv_vadd(vbool8_t mask,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,32); +} + + +vuint8m2_t test___riscv_vadd(vbool4_t mask,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,32); +} + + +vuint8m4_t test___riscv_vadd(vbool2_t mask,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,32); +} + + +vuint8m8_t test___riscv_vadd(vbool1_t mask,vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,32); +} + + +vuint16mf4_t test___riscv_vadd(vbool64_t mask,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,32); +} + + +vuint16mf2_t test___riscv_vadd(vbool32_t mask,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,32); +} + + +vuint16m1_t test___riscv_vadd(vbool16_t mask,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,32); +} + + +vuint16m2_t test___riscv_vadd(vbool8_t mask,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,32); +} + + +vuint16m4_t test___riscv_vadd(vbool4_t mask,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,32); +} + + +vuint16m8_t test___riscv_vadd(vbool2_t mask,vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,32); +} + + +vuint32mf2_t test___riscv_vadd(vbool64_t mask,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,32); +} + + +vuint32m1_t test___riscv_vadd(vbool32_t mask,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,32); +} + + +vuint32m2_t test___riscv_vadd(vbool16_t mask,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,32); +} + + +vuint32m4_t test___riscv_vadd(vbool8_t mask,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,32); +} + + +vuint32m8_t test___riscv_vadd(vbool4_t mask,vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,32); +} + + +vuint64m1_t test___riscv_vadd(vbool64_t mask,vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,32); +} + + +vuint64m2_t test___riscv_vadd(vbool32_t mask,vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,32); +} + + +vuint64m4_t test___riscv_vadd(vbool16_t mask,vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,32); +} + + +vuint64m8_t test___riscv_vadd(vbool8_t mask,vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_tu_rv32-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_tu_rv32-1.C new file mode 100644 index 00000000000..95c078f3798 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_tu_rv32-1.C @@ -0,0 +1,289 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vadd_tu(vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,vl); +} + + +vint8mf4_t test___riscv_vadd_tu(vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,vl); +} + + +vint8mf2_t test___riscv_vadd_tu(vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,vl); +} + + +vint8m1_t test___riscv_vadd_tu(vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,vl); +} + + +vint8m2_t test___riscv_vadd_tu(vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,vl); +} + + +vint8m4_t test___riscv_vadd_tu(vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,vl); +} + + +vint8m8_t test___riscv_vadd_tu(vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,vl); +} + + +vint16mf4_t test___riscv_vadd_tu(vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,vl); +} + + +vint16mf2_t test___riscv_vadd_tu(vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,vl); +} + + +vint16m1_t test___riscv_vadd_tu(vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,vl); +} + + +vint16m2_t test___riscv_vadd_tu(vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,vl); +} + + +vint16m4_t test___riscv_vadd_tu(vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,vl); +} + + +vint16m8_t test___riscv_vadd_tu(vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,vl); +} + + +vint32mf2_t test___riscv_vadd_tu(vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,vl); +} + + +vint32m1_t test___riscv_vadd_tu(vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,vl); +} + + +vint32m2_t test___riscv_vadd_tu(vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,vl); +} + + +vint32m4_t test___riscv_vadd_tu(vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,vl); +} + + +vint32m8_t test___riscv_vadd_tu(vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,vl); +} + + +vint64m1_t test___riscv_vadd_tu(vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,vl); +} + + +vint64m2_t test___riscv_vadd_tu(vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,vl); +} + + +vint64m4_t test___riscv_vadd_tu(vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,vl); +} + + +vint64m8_t test___riscv_vadd_tu(vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,vl); +} + + +vuint8mf8_t test___riscv_vadd_tu(vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,vl); +} + + +vuint8mf4_t test___riscv_vadd_tu(vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,vl); +} + + +vuint8mf2_t test___riscv_vadd_tu(vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,vl); +} + + +vuint8m1_t test___riscv_vadd_tu(vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,vl); +} + + +vuint8m2_t test___riscv_vadd_tu(vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,vl); +} + + +vuint8m4_t test___riscv_vadd_tu(vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,vl); +} + + +vuint8m8_t test___riscv_vadd_tu(vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,vl); +} + + +vuint16mf4_t test___riscv_vadd_tu(vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,vl); +} + + +vuint16mf2_t test___riscv_vadd_tu(vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,vl); +} + + +vuint16m1_t test___riscv_vadd_tu(vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,vl); +} + + +vuint16m2_t test___riscv_vadd_tu(vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,vl); +} + + +vuint16m4_t test___riscv_vadd_tu(vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,vl); +} + + +vuint16m8_t test___riscv_vadd_tu(vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,vl); +} + + +vuint32mf2_t test___riscv_vadd_tu(vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,vl); +} + + +vuint32m1_t test___riscv_vadd_tu(vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,vl); +} + + +vuint32m2_t test___riscv_vadd_tu(vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,vl); +} + + +vuint32m4_t test___riscv_vadd_tu(vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,vl); +} + + +vuint32m8_t test___riscv_vadd_tu(vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,vl); +} + + +vuint64m1_t test___riscv_vadd_tu(vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,vl); +} + + +vuint64m2_t test___riscv_vadd_tu(vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,vl); +} + + +vuint64m4_t test___riscv_vadd_tu(vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,vl); +} + + +vuint64m8_t test___riscv_vadd_tu(vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 8 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_tu_rv32-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_tu_rv32-2.C new file mode 100644 index 00000000000..fb3e812499a --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_tu_rv32-2.C @@ -0,0 +1,289 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vadd_tu(vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,31); +} + + +vint8mf4_t test___riscv_vadd_tu(vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,31); +} + + +vint8mf2_t test___riscv_vadd_tu(vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,31); +} + + +vint8m1_t test___riscv_vadd_tu(vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,31); +} + + +vint8m2_t test___riscv_vadd_tu(vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,31); +} + + +vint8m4_t test___riscv_vadd_tu(vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,31); +} + + +vint8m8_t test___riscv_vadd_tu(vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,31); +} + + +vint16mf4_t test___riscv_vadd_tu(vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,31); +} + + +vint16mf2_t test___riscv_vadd_tu(vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,31); +} + + +vint16m1_t test___riscv_vadd_tu(vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,31); +} + + +vint16m2_t test___riscv_vadd_tu(vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,31); +} + + +vint16m4_t test___riscv_vadd_tu(vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,31); +} + + +vint16m8_t test___riscv_vadd_tu(vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,31); +} + + +vint32mf2_t test___riscv_vadd_tu(vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,31); +} + + +vint32m1_t test___riscv_vadd_tu(vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,31); +} + + +vint32m2_t test___riscv_vadd_tu(vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,31); +} + + +vint32m4_t test___riscv_vadd_tu(vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,31); +} + + +vint32m8_t test___riscv_vadd_tu(vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,31); +} + + +vint64m1_t test___riscv_vadd_tu(vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,31); +} + + +vint64m2_t test___riscv_vadd_tu(vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,31); +} + + +vint64m4_t test___riscv_vadd_tu(vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,31); +} + + +vint64m8_t test___riscv_vadd_tu(vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,31); +} + + +vuint8mf8_t test___riscv_vadd_tu(vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,31); +} + + +vuint8mf4_t test___riscv_vadd_tu(vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,31); +} + + +vuint8mf2_t test___riscv_vadd_tu(vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,31); +} + + +vuint8m1_t test___riscv_vadd_tu(vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,31); +} + + +vuint8m2_t test___riscv_vadd_tu(vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,31); +} + + +vuint8m4_t test___riscv_vadd_tu(vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,31); +} + + +vuint8m8_t test___riscv_vadd_tu(vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,31); +} + + +vuint16mf4_t test___riscv_vadd_tu(vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,31); +} + + +vuint16mf2_t test___riscv_vadd_tu(vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,31); +} + + +vuint16m1_t test___riscv_vadd_tu(vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,31); +} + + +vuint16m2_t test___riscv_vadd_tu(vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,31); +} + + +vuint16m4_t test___riscv_vadd_tu(vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,31); +} + + +vuint16m8_t test___riscv_vadd_tu(vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,31); +} + + +vuint32mf2_t test___riscv_vadd_tu(vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,31); +} + + +vuint32m1_t test___riscv_vadd_tu(vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,31); +} + + +vuint32m2_t test___riscv_vadd_tu(vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,31); +} + + +vuint32m4_t test___riscv_vadd_tu(vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,31); +} + + +vuint32m8_t test___riscv_vadd_tu(vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,31); +} + + +vuint64m1_t test___riscv_vadd_tu(vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,31); +} + + +vuint64m2_t test___riscv_vadd_tu(vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,31); +} + + +vuint64m4_t test___riscv_vadd_tu(vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,31); +} + + +vuint64m8_t test___riscv_vadd_tu(vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 8 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_tu_rv32-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_tu_rv32-3.C new file mode 100644 index 00000000000..44aed96a6c9 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_tu_rv32-3.C @@ -0,0 +1,289 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vadd_tu(vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,32); +} + + +vint8mf4_t test___riscv_vadd_tu(vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,32); +} + + +vint8mf2_t test___riscv_vadd_tu(vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,32); +} + + +vint8m1_t test___riscv_vadd_tu(vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,32); +} + + +vint8m2_t test___riscv_vadd_tu(vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,32); +} + + +vint8m4_t test___riscv_vadd_tu(vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,32); +} + + +vint8m8_t test___riscv_vadd_tu(vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,32); +} + + +vint16mf4_t test___riscv_vadd_tu(vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,32); +} + + +vint16mf2_t test___riscv_vadd_tu(vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,32); +} + + +vint16m1_t test___riscv_vadd_tu(vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,32); +} + + +vint16m2_t test___riscv_vadd_tu(vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,32); +} + + +vint16m4_t test___riscv_vadd_tu(vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,32); +} + + +vint16m8_t test___riscv_vadd_tu(vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,32); +} + + +vint32mf2_t test___riscv_vadd_tu(vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,32); +} + + +vint32m1_t test___riscv_vadd_tu(vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,32); +} + + +vint32m2_t test___riscv_vadd_tu(vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,32); +} + + +vint32m4_t test___riscv_vadd_tu(vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,32); +} + + +vint32m8_t test___riscv_vadd_tu(vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,32); +} + + +vint64m1_t test___riscv_vadd_tu(vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,32); +} + + +vint64m2_t test___riscv_vadd_tu(vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,32); +} + + +vint64m4_t test___riscv_vadd_tu(vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,32); +} + + +vint64m8_t test___riscv_vadd_tu(vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,32); +} + + +vuint8mf8_t test___riscv_vadd_tu(vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,32); +} + + +vuint8mf4_t test___riscv_vadd_tu(vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,32); +} + + +vuint8mf2_t test___riscv_vadd_tu(vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,32); +} + + +vuint8m1_t test___riscv_vadd_tu(vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,32); +} + + +vuint8m2_t test___riscv_vadd_tu(vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,32); +} + + +vuint8m4_t test___riscv_vadd_tu(vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,32); +} + + +vuint8m8_t test___riscv_vadd_tu(vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,32); +} + + +vuint16mf4_t test___riscv_vadd_tu(vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,32); +} + + +vuint16mf2_t test___riscv_vadd_tu(vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,32); +} + + +vuint16m1_t test___riscv_vadd_tu(vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,32); +} + + +vuint16m2_t test___riscv_vadd_tu(vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,32); +} + + +vuint16m4_t test___riscv_vadd_tu(vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,32); +} + + +vuint16m8_t test___riscv_vadd_tu(vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,32); +} + + +vuint32mf2_t test___riscv_vadd_tu(vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,32); +} + + +vuint32m1_t test___riscv_vadd_tu(vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,32); +} + + +vuint32m2_t test___riscv_vadd_tu(vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,32); +} + + +vuint32m4_t test___riscv_vadd_tu(vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,32); +} + + +vuint32m8_t test___riscv_vadd_tu(vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,32); +} + + +vuint64m1_t test___riscv_vadd_tu(vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,32); +} + + +vuint64m2_t test___riscv_vadd_tu(vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,32); +} + + +vuint64m4_t test___riscv_vadd_tu(vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,32); +} + + +vuint64m8_t test___riscv_vadd_tu(vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 8 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_tu_rv64-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_tu_rv64-1.C new file mode 100644 index 00000000000..9d525139ed8 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_tu_rv64-1.C @@ -0,0 +1,292 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vadd_tu(vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,vl); +} + + +vint8mf4_t test___riscv_vadd_tu(vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,vl); +} + + +vint8mf2_t test___riscv_vadd_tu(vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,vl); +} + + +vint8m1_t test___riscv_vadd_tu(vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,vl); +} + + +vint8m2_t test___riscv_vadd_tu(vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,vl); +} + + +vint8m4_t test___riscv_vadd_tu(vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,vl); +} + + +vint8m8_t test___riscv_vadd_tu(vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,vl); +} + + +vint16mf4_t test___riscv_vadd_tu(vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,vl); +} + + +vint16mf2_t test___riscv_vadd_tu(vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,vl); +} + + +vint16m1_t test___riscv_vadd_tu(vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,vl); +} + + +vint16m2_t test___riscv_vadd_tu(vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,vl); +} + + +vint16m4_t test___riscv_vadd_tu(vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,vl); +} + + +vint16m8_t test___riscv_vadd_tu(vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,vl); +} + + +vint32mf2_t test___riscv_vadd_tu(vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,vl); +} + + +vint32m1_t test___riscv_vadd_tu(vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,vl); +} + + +vint32m2_t test___riscv_vadd_tu(vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,vl); +} + + +vint32m4_t test___riscv_vadd_tu(vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,vl); +} + + +vint32m8_t test___riscv_vadd_tu(vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,vl); +} + + +vint64m1_t test___riscv_vadd_tu(vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,vl); +} + + +vint64m2_t test___riscv_vadd_tu(vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,vl); +} + + +vint64m4_t test___riscv_vadd_tu(vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,vl); +} + + +vint64m8_t test___riscv_vadd_tu(vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,vl); +} + + +vuint8mf8_t test___riscv_vadd_tu(vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,vl); +} + + +vuint8mf4_t test___riscv_vadd_tu(vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,vl); +} + + +vuint8mf2_t test___riscv_vadd_tu(vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,vl); +} + + +vuint8m1_t test___riscv_vadd_tu(vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,vl); +} + + +vuint8m2_t test___riscv_vadd_tu(vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,vl); +} + + +vuint8m4_t test___riscv_vadd_tu(vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,vl); +} + + +vuint8m8_t test___riscv_vadd_tu(vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,vl); +} + + +vuint16mf4_t test___riscv_vadd_tu(vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,vl); +} + + +vuint16mf2_t test___riscv_vadd_tu(vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,vl); +} + + +vuint16m1_t test___riscv_vadd_tu(vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,vl); +} + + +vuint16m2_t test___riscv_vadd_tu(vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,vl); +} + + +vuint16m4_t test___riscv_vadd_tu(vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,vl); +} + + +vuint16m8_t test___riscv_vadd_tu(vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,vl); +} + + +vuint32mf2_t test___riscv_vadd_tu(vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,vl); +} + + +vuint32m1_t test___riscv_vadd_tu(vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,vl); +} + + +vuint32m2_t test___riscv_vadd_tu(vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,vl); +} + + +vuint32m4_t test___riscv_vadd_tu(vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,vl); +} + + +vuint32m8_t test___riscv_vadd_tu(vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,vl); +} + + +vuint64m1_t test___riscv_vadd_tu(vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,vl); +} + + +vuint64m2_t test___riscv_vadd_tu(vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,vl); +} + + +vuint64m4_t test___riscv_vadd_tu(vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,vl); +} + + +vuint64m8_t test___riscv_vadd_tu(vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_tu_rv64-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_tu_rv64-2.C new file mode 100644 index 00000000000..0eaab87d547 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_tu_rv64-2.C @@ -0,0 +1,292 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vadd_tu(vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,31); +} + + +vint8mf4_t test___riscv_vadd_tu(vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,31); +} + + +vint8mf2_t test___riscv_vadd_tu(vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,31); +} + + +vint8m1_t test___riscv_vadd_tu(vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,31); +} + + +vint8m2_t test___riscv_vadd_tu(vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,31); +} + + +vint8m4_t test___riscv_vadd_tu(vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,31); +} + + +vint8m8_t test___riscv_vadd_tu(vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,31); +} + + +vint16mf4_t test___riscv_vadd_tu(vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,31); +} + + +vint16mf2_t test___riscv_vadd_tu(vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,31); +} + + +vint16m1_t test___riscv_vadd_tu(vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,31); +} + + +vint16m2_t test___riscv_vadd_tu(vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,31); +} + + +vint16m4_t test___riscv_vadd_tu(vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,31); +} + + +vint16m8_t test___riscv_vadd_tu(vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,31); +} + + +vint32mf2_t test___riscv_vadd_tu(vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,31); +} + + +vint32m1_t test___riscv_vadd_tu(vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,31); +} + + +vint32m2_t test___riscv_vadd_tu(vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,31); +} + + +vint32m4_t test___riscv_vadd_tu(vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,31); +} + + +vint32m8_t test___riscv_vadd_tu(vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,31); +} + + +vint64m1_t test___riscv_vadd_tu(vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,31); +} + + +vint64m2_t test___riscv_vadd_tu(vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,31); +} + + +vint64m4_t test___riscv_vadd_tu(vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,31); +} + + +vint64m8_t test___riscv_vadd_tu(vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,31); +} + + +vuint8mf8_t test___riscv_vadd_tu(vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,31); +} + + +vuint8mf4_t test___riscv_vadd_tu(vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,31); +} + + +vuint8mf2_t test___riscv_vadd_tu(vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,31); +} + + +vuint8m1_t test___riscv_vadd_tu(vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,31); +} + + +vuint8m2_t test___riscv_vadd_tu(vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,31); +} + + +vuint8m4_t test___riscv_vadd_tu(vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,31); +} + + +vuint8m8_t test___riscv_vadd_tu(vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,31); +} + + +vuint16mf4_t test___riscv_vadd_tu(vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,31); +} + + +vuint16mf2_t test___riscv_vadd_tu(vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,31); +} + + +vuint16m1_t test___riscv_vadd_tu(vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,31); +} + + +vuint16m2_t test___riscv_vadd_tu(vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,31); +} + + +vuint16m4_t test___riscv_vadd_tu(vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,31); +} + + +vuint16m8_t test___riscv_vadd_tu(vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,31); +} + + +vuint32mf2_t test___riscv_vadd_tu(vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,31); +} + + +vuint32m1_t test___riscv_vadd_tu(vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,31); +} + + +vuint32m2_t test___riscv_vadd_tu(vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,31); +} + + +vuint32m4_t test___riscv_vadd_tu(vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,31); +} + + +vuint32m8_t test___riscv_vadd_tu(vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,31); +} + + +vuint64m1_t test___riscv_vadd_tu(vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,31); +} + + +vuint64m2_t test___riscv_vadd_tu(vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,31); +} + + +vuint64m4_t test___riscv_vadd_tu(vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,31); +} + + +vuint64m8_t test___riscv_vadd_tu(vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_tu_rv64-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_tu_rv64-3.C new file mode 100644 index 00000000000..d933b7fdeb9 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_tu_rv64-3.C @@ -0,0 +1,292 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vadd_tu(vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,32); +} + + +vint8mf4_t test___riscv_vadd_tu(vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,32); +} + + +vint8mf2_t test___riscv_vadd_tu(vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,32); +} + + +vint8m1_t test___riscv_vadd_tu(vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,32); +} + + +vint8m2_t test___riscv_vadd_tu(vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,32); +} + + +vint8m4_t test___riscv_vadd_tu(vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,32); +} + + +vint8m8_t test___riscv_vadd_tu(vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,32); +} + + +vint16mf4_t test___riscv_vadd_tu(vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,32); +} + + +vint16mf2_t test___riscv_vadd_tu(vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,32); +} + + +vint16m1_t test___riscv_vadd_tu(vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,32); +} + + +vint16m2_t test___riscv_vadd_tu(vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,32); +} + + +vint16m4_t test___riscv_vadd_tu(vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,32); +} + + +vint16m8_t test___riscv_vadd_tu(vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,32); +} + + +vint32mf2_t test___riscv_vadd_tu(vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,32); +} + + +vint32m1_t test___riscv_vadd_tu(vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,32); +} + + +vint32m2_t test___riscv_vadd_tu(vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,32); +} + + +vint32m4_t test___riscv_vadd_tu(vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,32); +} + + +vint32m8_t test___riscv_vadd_tu(vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,32); +} + + +vint64m1_t test___riscv_vadd_tu(vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,32); +} + + +vint64m2_t test___riscv_vadd_tu(vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,32); +} + + +vint64m4_t test___riscv_vadd_tu(vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,32); +} + + +vint64m8_t test___riscv_vadd_tu(vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,32); +} + + +vuint8mf8_t test___riscv_vadd_tu(vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,32); +} + + +vuint8mf4_t test___riscv_vadd_tu(vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,32); +} + + +vuint8mf2_t test___riscv_vadd_tu(vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,32); +} + + +vuint8m1_t test___riscv_vadd_tu(vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,32); +} + + +vuint8m2_t test___riscv_vadd_tu(vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,32); +} + + +vuint8m4_t test___riscv_vadd_tu(vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,32); +} + + +vuint8m8_t test___riscv_vadd_tu(vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,32); +} + + +vuint16mf4_t test___riscv_vadd_tu(vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,32); +} + + +vuint16mf2_t test___riscv_vadd_tu(vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,32); +} + + +vuint16m1_t test___riscv_vadd_tu(vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,32); +} + + +vuint16m2_t test___riscv_vadd_tu(vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,32); +} + + +vuint16m4_t test___riscv_vadd_tu(vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,32); +} + + +vuint16m8_t test___riscv_vadd_tu(vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,32); +} + + +vuint32mf2_t test___riscv_vadd_tu(vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,32); +} + + +vuint32m1_t test___riscv_vadd_tu(vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,32); +} + + +vuint32m2_t test___riscv_vadd_tu(vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,32); +} + + +vuint32m4_t test___riscv_vadd_tu(vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,32); +} + + +vuint32m8_t test___riscv_vadd_tu(vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,32); +} + + +vuint64m1_t test___riscv_vadd_tu(vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,32); +} + + +vuint64m2_t test___riscv_vadd_tu(vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,32); +} + + +vuint64m4_t test___riscv_vadd_tu(vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,32); +} + + +vuint64m8_t test___riscv_vadd_tu(vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_tum_rv32-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_tum_rv32-1.C new file mode 100644 index 00000000000..4f43005659e --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_tum_rv32-1.C @@ -0,0 +1,289 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vadd_tum(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,vl); +} + + +vint8mf4_t test___riscv_vadd_tum(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,vl); +} + + +vint8mf2_t test___riscv_vadd_tum(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,vl); +} + + +vint8m1_t test___riscv_vadd_tum(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,vl); +} + + +vint8m2_t test___riscv_vadd_tum(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,vl); +} + + +vint8m4_t test___riscv_vadd_tum(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,vl); +} + + +vint8m8_t test___riscv_vadd_tum(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,vl); +} + + +vint16mf4_t test___riscv_vadd_tum(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,vl); +} + + +vint16mf2_t test___riscv_vadd_tum(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,vl); +} + + +vint16m1_t test___riscv_vadd_tum(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,vl); +} + + +vint16m2_t test___riscv_vadd_tum(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,vl); +} + + +vint16m4_t test___riscv_vadd_tum(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,vl); +} + + +vint16m8_t test___riscv_vadd_tum(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,vl); +} + + +vint32mf2_t test___riscv_vadd_tum(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,vl); +} + + +vint32m1_t test___riscv_vadd_tum(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,vl); +} + + +vint32m2_t test___riscv_vadd_tum(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,vl); +} + + +vint32m4_t test___riscv_vadd_tum(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,vl); +} + + +vint32m8_t test___riscv_vadd_tum(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,vl); +} + + +vint64m1_t test___riscv_vadd_tum(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,vl); +} + + +vint64m2_t test___riscv_vadd_tum(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,vl); +} + + +vint64m4_t test___riscv_vadd_tum(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,vl); +} + + +vint64m8_t test___riscv_vadd_tum(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,vl); +} + + +vuint8mf8_t test___riscv_vadd_tum(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,vl); +} + + +vuint8mf4_t test___riscv_vadd_tum(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,vl); +} + + +vuint8mf2_t test___riscv_vadd_tum(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,vl); +} + + +vuint8m1_t test___riscv_vadd_tum(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,vl); +} + + +vuint8m2_t test___riscv_vadd_tum(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,vl); +} + + +vuint8m4_t test___riscv_vadd_tum(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,vl); +} + + +vuint8m8_t test___riscv_vadd_tum(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,vl); +} + + +vuint16mf4_t test___riscv_vadd_tum(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,vl); +} + + +vuint16mf2_t test___riscv_vadd_tum(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,vl); +} + + +vuint16m1_t test___riscv_vadd_tum(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,vl); +} + + +vuint16m2_t test___riscv_vadd_tum(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,vl); +} + + +vuint16m4_t test___riscv_vadd_tum(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,vl); +} + + +vuint16m8_t test___riscv_vadd_tum(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,vl); +} + + +vuint32mf2_t test___riscv_vadd_tum(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,vl); +} + + +vuint32m1_t test___riscv_vadd_tum(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,vl); +} + + +vuint32m2_t test___riscv_vadd_tum(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,vl); +} + + +vuint32m4_t test___riscv_vadd_tum(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,vl); +} + + +vuint32m8_t test___riscv_vadd_tum(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,vl); +} + + +vuint64m1_t test___riscv_vadd_tum(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,vl); +} + + +vuint64m2_t test___riscv_vadd_tum(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,vl); +} + + +vuint64m4_t test___riscv_vadd_tum(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,vl); +} + + +vuint64m8_t test___riscv_vadd_tum(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 8 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_tum_rv32-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_tum_rv32-2.C new file mode 100644 index 00000000000..3af29aaaef1 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_tum_rv32-2.C @@ -0,0 +1,289 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vadd_tum(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,31); +} + + +vint8mf4_t test___riscv_vadd_tum(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,31); +} + + +vint8mf2_t test___riscv_vadd_tum(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,31); +} + + +vint8m1_t test___riscv_vadd_tum(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,31); +} + + +vint8m2_t test___riscv_vadd_tum(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,31); +} + + +vint8m4_t test___riscv_vadd_tum(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,31); +} + + +vint8m8_t test___riscv_vadd_tum(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,31); +} + + +vint16mf4_t test___riscv_vadd_tum(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,31); +} + + +vint16mf2_t test___riscv_vadd_tum(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,31); +} + + +vint16m1_t test___riscv_vadd_tum(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,31); +} + + +vint16m2_t test___riscv_vadd_tum(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,31); +} + + +vint16m4_t test___riscv_vadd_tum(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,31); +} + + +vint16m8_t test___riscv_vadd_tum(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,31); +} + + +vint32mf2_t test___riscv_vadd_tum(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,31); +} + + +vint32m1_t test___riscv_vadd_tum(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,31); +} + + +vint32m2_t test___riscv_vadd_tum(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,31); +} + + +vint32m4_t test___riscv_vadd_tum(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,31); +} + + +vint32m8_t test___riscv_vadd_tum(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,31); +} + + +vint64m1_t test___riscv_vadd_tum(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,31); +} + + +vint64m2_t test___riscv_vadd_tum(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,31); +} + + +vint64m4_t test___riscv_vadd_tum(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,31); +} + + +vint64m8_t test___riscv_vadd_tum(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,31); +} + + +vuint8mf8_t test___riscv_vadd_tum(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,31); +} + + +vuint8mf4_t test___riscv_vadd_tum(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,31); +} + + +vuint8mf2_t test___riscv_vadd_tum(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,31); +} + + +vuint8m1_t test___riscv_vadd_tum(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,31); +} + + +vuint8m2_t test___riscv_vadd_tum(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,31); +} + + +vuint8m4_t test___riscv_vadd_tum(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,31); +} + + +vuint8m8_t test___riscv_vadd_tum(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,31); +} + + +vuint16mf4_t test___riscv_vadd_tum(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,31); +} + + +vuint16mf2_t test___riscv_vadd_tum(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,31); +} + + +vuint16m1_t test___riscv_vadd_tum(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,31); +} + + +vuint16m2_t test___riscv_vadd_tum(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,31); +} + + +vuint16m4_t test___riscv_vadd_tum(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,31); +} + + +vuint16m8_t test___riscv_vadd_tum(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,31); +} + + +vuint32mf2_t test___riscv_vadd_tum(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,31); +} + + +vuint32m1_t test___riscv_vadd_tum(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,31); +} + + +vuint32m2_t test___riscv_vadd_tum(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,31); +} + + +vuint32m4_t test___riscv_vadd_tum(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,31); +} + + +vuint32m8_t test___riscv_vadd_tum(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,31); +} + + +vuint64m1_t test___riscv_vadd_tum(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,31); +} + + +vuint64m2_t test___riscv_vadd_tum(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,31); +} + + +vuint64m4_t test___riscv_vadd_tum(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,31); +} + + +vuint64m8_t test___riscv_vadd_tum(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 8 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_tum_rv32-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_tum_rv32-3.C new file mode 100644 index 00000000000..db3f0f10cde --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_tum_rv32-3.C @@ -0,0 +1,289 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vadd_tum(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,32); +} + + +vint8mf4_t test___riscv_vadd_tum(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,32); +} + + +vint8mf2_t test___riscv_vadd_tum(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,32); +} + + +vint8m1_t test___riscv_vadd_tum(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,32); +} + + +vint8m2_t test___riscv_vadd_tum(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,32); +} + + +vint8m4_t test___riscv_vadd_tum(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,32); +} + + +vint8m8_t test___riscv_vadd_tum(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,32); +} + + +vint16mf4_t test___riscv_vadd_tum(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,32); +} + + +vint16mf2_t test___riscv_vadd_tum(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,32); +} + + +vint16m1_t test___riscv_vadd_tum(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,32); +} + + +vint16m2_t test___riscv_vadd_tum(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,32); +} + + +vint16m4_t test___riscv_vadd_tum(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,32); +} + + +vint16m8_t test___riscv_vadd_tum(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,32); +} + + +vint32mf2_t test___riscv_vadd_tum(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,32); +} + + +vint32m1_t test___riscv_vadd_tum(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,32); +} + + +vint32m2_t test___riscv_vadd_tum(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,32); +} + + +vint32m4_t test___riscv_vadd_tum(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,32); +} + + +vint32m8_t test___riscv_vadd_tum(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,32); +} + + +vint64m1_t test___riscv_vadd_tum(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,32); +} + + +vint64m2_t test___riscv_vadd_tum(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,32); +} + + +vint64m4_t test___riscv_vadd_tum(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,32); +} + + +vint64m8_t test___riscv_vadd_tum(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,32); +} + + +vuint8mf8_t test___riscv_vadd_tum(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,32); +} + + +vuint8mf4_t test___riscv_vadd_tum(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,32); +} + + +vuint8mf2_t test___riscv_vadd_tum(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,32); +} + + +vuint8m1_t test___riscv_vadd_tum(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,32); +} + + +vuint8m2_t test___riscv_vadd_tum(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,32); +} + + +vuint8m4_t test___riscv_vadd_tum(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,32); +} + + +vuint8m8_t test___riscv_vadd_tum(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,32); +} + + +vuint16mf4_t test___riscv_vadd_tum(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,32); +} + + +vuint16mf2_t test___riscv_vadd_tum(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,32); +} + + +vuint16m1_t test___riscv_vadd_tum(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,32); +} + + +vuint16m2_t test___riscv_vadd_tum(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,32); +} + + +vuint16m4_t test___riscv_vadd_tum(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,32); +} + + +vuint16m8_t test___riscv_vadd_tum(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,32); +} + + +vuint32mf2_t test___riscv_vadd_tum(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,32); +} + + +vuint32m1_t test___riscv_vadd_tum(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,32); +} + + +vuint32m2_t test___riscv_vadd_tum(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,32); +} + + +vuint32m4_t test___riscv_vadd_tum(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,32); +} + + +vuint32m8_t test___riscv_vadd_tum(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,32); +} + + +vuint64m1_t test___riscv_vadd_tum(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,32); +} + + +vuint64m2_t test___riscv_vadd_tum(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,32); +} + + +vuint64m4_t test___riscv_vadd_tum(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,32); +} + + +vuint64m8_t test___riscv_vadd_tum(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 8 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_tum_rv64-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_tum_rv64-1.C new file mode 100644 index 00000000000..3b3377f3458 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_tum_rv64-1.C @@ -0,0 +1,292 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vadd_tum(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,vl); +} + + +vint8mf4_t test___riscv_vadd_tum(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,vl); +} + + +vint8mf2_t test___riscv_vadd_tum(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,vl); +} + + +vint8m1_t test___riscv_vadd_tum(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,vl); +} + + +vint8m2_t test___riscv_vadd_tum(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,vl); +} + + +vint8m4_t test___riscv_vadd_tum(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,vl); +} + + +vint8m8_t test___riscv_vadd_tum(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,vl); +} + + +vint16mf4_t test___riscv_vadd_tum(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,vl); +} + + +vint16mf2_t test___riscv_vadd_tum(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,vl); +} + + +vint16m1_t test___riscv_vadd_tum(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,vl); +} + + +vint16m2_t test___riscv_vadd_tum(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,vl); +} + + +vint16m4_t test___riscv_vadd_tum(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,vl); +} + + +vint16m8_t test___riscv_vadd_tum(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,vl); +} + + +vint32mf2_t test___riscv_vadd_tum(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,vl); +} + + +vint32m1_t test___riscv_vadd_tum(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,vl); +} + + +vint32m2_t test___riscv_vadd_tum(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,vl); +} + + +vint32m4_t test___riscv_vadd_tum(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,vl); +} + + +vint32m8_t test___riscv_vadd_tum(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,vl); +} + + +vint64m1_t test___riscv_vadd_tum(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,vl); +} + + +vint64m2_t test___riscv_vadd_tum(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,vl); +} + + +vint64m4_t test___riscv_vadd_tum(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,vl); +} + + +vint64m8_t test___riscv_vadd_tum(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,vl); +} + + +vuint8mf8_t test___riscv_vadd_tum(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,vl); +} + + +vuint8mf4_t test___riscv_vadd_tum(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,vl); +} + + +vuint8mf2_t test___riscv_vadd_tum(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,vl); +} + + +vuint8m1_t test___riscv_vadd_tum(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,vl); +} + + +vuint8m2_t test___riscv_vadd_tum(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,vl); +} + + +vuint8m4_t test___riscv_vadd_tum(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,vl); +} + + +vuint8m8_t test___riscv_vadd_tum(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,vl); +} + + +vuint16mf4_t test___riscv_vadd_tum(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,vl); +} + + +vuint16mf2_t test___riscv_vadd_tum(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,vl); +} + + +vuint16m1_t test___riscv_vadd_tum(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,vl); +} + + +vuint16m2_t test___riscv_vadd_tum(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,vl); +} + + +vuint16m4_t test___riscv_vadd_tum(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,vl); +} + + +vuint16m8_t test___riscv_vadd_tum(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,vl); +} + + +vuint32mf2_t test___riscv_vadd_tum(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,vl); +} + + +vuint32m1_t test___riscv_vadd_tum(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,vl); +} + + +vuint32m2_t test___riscv_vadd_tum(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,vl); +} + + +vuint32m4_t test___riscv_vadd_tum(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,vl); +} + + +vuint32m8_t test___riscv_vadd_tum(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,vl); +} + + +vuint64m1_t test___riscv_vadd_tum(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,vl); +} + + +vuint64m2_t test___riscv_vadd_tum(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,vl); +} + + +vuint64m4_t test___riscv_vadd_tum(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,vl); +} + + +vuint64m8_t test___riscv_vadd_tum(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_tum_rv64-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_tum_rv64-2.C new file mode 100644 index 00000000000..ece9f1a14fc --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_tum_rv64-2.C @@ -0,0 +1,292 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vadd_tum(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,31); +} + + +vint8mf4_t test___riscv_vadd_tum(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,31); +} + + +vint8mf2_t test___riscv_vadd_tum(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,31); +} + + +vint8m1_t test___riscv_vadd_tum(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,31); +} + + +vint8m2_t test___riscv_vadd_tum(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,31); +} + + +vint8m4_t test___riscv_vadd_tum(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,31); +} + + +vint8m8_t test___riscv_vadd_tum(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,31); +} + + +vint16mf4_t test___riscv_vadd_tum(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,31); +} + + +vint16mf2_t test___riscv_vadd_tum(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,31); +} + + +vint16m1_t test___riscv_vadd_tum(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,31); +} + + +vint16m2_t test___riscv_vadd_tum(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,31); +} + + +vint16m4_t test___riscv_vadd_tum(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,31); +} + + +vint16m8_t test___riscv_vadd_tum(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,31); +} + + +vint32mf2_t test___riscv_vadd_tum(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,31); +} + + +vint32m1_t test___riscv_vadd_tum(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,31); +} + + +vint32m2_t test___riscv_vadd_tum(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,31); +} + + +vint32m4_t test___riscv_vadd_tum(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,31); +} + + +vint32m8_t test___riscv_vadd_tum(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,31); +} + + +vint64m1_t test___riscv_vadd_tum(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,31); +} + + +vint64m2_t test___riscv_vadd_tum(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,31); +} + + +vint64m4_t test___riscv_vadd_tum(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,31); +} + + +vint64m8_t test___riscv_vadd_tum(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,31); +} + + +vuint8mf8_t test___riscv_vadd_tum(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,31); +} + + +vuint8mf4_t test___riscv_vadd_tum(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,31); +} + + +vuint8mf2_t test___riscv_vadd_tum(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,31); +} + + +vuint8m1_t test___riscv_vadd_tum(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,31); +} + + +vuint8m2_t test___riscv_vadd_tum(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,31); +} + + +vuint8m4_t test___riscv_vadd_tum(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,31); +} + + +vuint8m8_t test___riscv_vadd_tum(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,31); +} + + +vuint16mf4_t test___riscv_vadd_tum(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,31); +} + + +vuint16mf2_t test___riscv_vadd_tum(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,31); +} + + +vuint16m1_t test___riscv_vadd_tum(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,31); +} + + +vuint16m2_t test___riscv_vadd_tum(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,31); +} + + +vuint16m4_t test___riscv_vadd_tum(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,31); +} + + +vuint16m8_t test___riscv_vadd_tum(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,31); +} + + +vuint32mf2_t test___riscv_vadd_tum(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,31); +} + + +vuint32m1_t test___riscv_vadd_tum(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,31); +} + + +vuint32m2_t test___riscv_vadd_tum(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,31); +} + + +vuint32m4_t test___riscv_vadd_tum(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,31); +} + + +vuint32m8_t test___riscv_vadd_tum(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,31); +} + + +vuint64m1_t test___riscv_vadd_tum(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,31); +} + + +vuint64m2_t test___riscv_vadd_tum(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,31); +} + + +vuint64m4_t test___riscv_vadd_tum(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,31); +} + + +vuint64m8_t test___riscv_vadd_tum(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_tum_rv64-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_tum_rv64-3.C new file mode 100644 index 00000000000..56f7c5d5612 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_tum_rv64-3.C @@ -0,0 +1,292 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vadd_tum(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,32); +} + + +vint8mf4_t test___riscv_vadd_tum(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,32); +} + + +vint8mf2_t test___riscv_vadd_tum(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,32); +} + + +vint8m1_t test___riscv_vadd_tum(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,32); +} + + +vint8m2_t test___riscv_vadd_tum(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,32); +} + + +vint8m4_t test___riscv_vadd_tum(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,32); +} + + +vint8m8_t test___riscv_vadd_tum(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,32); +} + + +vint16mf4_t test___riscv_vadd_tum(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,32); +} + + +vint16mf2_t test___riscv_vadd_tum(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,32); +} + + +vint16m1_t test___riscv_vadd_tum(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,32); +} + + +vint16m2_t test___riscv_vadd_tum(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,32); +} + + +vint16m4_t test___riscv_vadd_tum(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,32); +} + + +vint16m8_t test___riscv_vadd_tum(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,32); +} + + +vint32mf2_t test___riscv_vadd_tum(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,32); +} + + +vint32m1_t test___riscv_vadd_tum(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,32); +} + + +vint32m2_t test___riscv_vadd_tum(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,32); +} + + +vint32m4_t test___riscv_vadd_tum(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,32); +} + + +vint32m8_t test___riscv_vadd_tum(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,32); +} + + +vint64m1_t test___riscv_vadd_tum(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,32); +} + + +vint64m2_t test___riscv_vadd_tum(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,32); +} + + +vint64m4_t test___riscv_vadd_tum(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,32); +} + + +vint64m8_t test___riscv_vadd_tum(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,32); +} + + +vuint8mf8_t test___riscv_vadd_tum(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,32); +} + + +vuint8mf4_t test___riscv_vadd_tum(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,32); +} + + +vuint8mf2_t test___riscv_vadd_tum(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,32); +} + + +vuint8m1_t test___riscv_vadd_tum(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,32); +} + + +vuint8m2_t test___riscv_vadd_tum(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,32); +} + + +vuint8m4_t test___riscv_vadd_tum(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,32); +} + + +vuint8m8_t test___riscv_vadd_tum(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,32); +} + + +vuint16mf4_t test___riscv_vadd_tum(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,32); +} + + +vuint16mf2_t test___riscv_vadd_tum(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,32); +} + + +vuint16m1_t test___riscv_vadd_tum(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,32); +} + + +vuint16m2_t test___riscv_vadd_tum(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,32); +} + + +vuint16m4_t test___riscv_vadd_tum(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,32); +} + + +vuint16m8_t test___riscv_vadd_tum(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,32); +} + + +vuint32mf2_t test___riscv_vadd_tum(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,32); +} + + +vuint32m1_t test___riscv_vadd_tum(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,32); +} + + +vuint32m2_t test___riscv_vadd_tum(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,32); +} + + +vuint32m4_t test___riscv_vadd_tum(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,32); +} + + +vuint32m8_t test___riscv_vadd_tum(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,32); +} + + +vuint64m1_t test___riscv_vadd_tum(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,32); +} + + +vuint64m2_t test___riscv_vadd_tum(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,32); +} + + +vuint64m4_t test___riscv_vadd_tum(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,32); +} + + +vuint64m8_t test___riscv_vadd_tum(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_tumu_rv32-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_tumu_rv32-1.C new file mode 100644 index 00000000000..91b816f125d --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_tumu_rv32-1.C @@ -0,0 +1,289 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vadd_tumu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,vl); +} + + +vint8mf4_t test___riscv_vadd_tumu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,vl); +} + + +vint8mf2_t test___riscv_vadd_tumu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,vl); +} + + +vint8m1_t test___riscv_vadd_tumu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,vl); +} + + +vint8m2_t test___riscv_vadd_tumu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,vl); +} + + +vint8m4_t test___riscv_vadd_tumu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,vl); +} + + +vint8m8_t test___riscv_vadd_tumu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,vl); +} + + +vint16mf4_t test___riscv_vadd_tumu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,vl); +} + + +vint16mf2_t test___riscv_vadd_tumu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,vl); +} + + +vint16m1_t test___riscv_vadd_tumu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,vl); +} + + +vint16m2_t test___riscv_vadd_tumu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,vl); +} + + +vint16m4_t test___riscv_vadd_tumu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,vl); +} + + +vint16m8_t test___riscv_vadd_tumu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,vl); +} + + +vint32mf2_t test___riscv_vadd_tumu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,vl); +} + + +vint32m1_t test___riscv_vadd_tumu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,vl); +} + + +vint32m2_t test___riscv_vadd_tumu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,vl); +} + + +vint32m4_t test___riscv_vadd_tumu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,vl); +} + + +vint32m8_t test___riscv_vadd_tumu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,vl); +} + + +vint64m1_t test___riscv_vadd_tumu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,vl); +} + + +vint64m2_t test___riscv_vadd_tumu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,vl); +} + + +vint64m4_t test___riscv_vadd_tumu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,vl); +} + + +vint64m8_t test___riscv_vadd_tumu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,vl); +} + + +vuint8mf8_t test___riscv_vadd_tumu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,vl); +} + + +vuint8mf4_t test___riscv_vadd_tumu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,vl); +} + + +vuint8mf2_t test___riscv_vadd_tumu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,vl); +} + + +vuint8m1_t test___riscv_vadd_tumu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,vl); +} + + +vuint8m2_t test___riscv_vadd_tumu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,vl); +} + + +vuint8m4_t test___riscv_vadd_tumu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,vl); +} + + +vuint8m8_t test___riscv_vadd_tumu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,vl); +} + + +vuint16mf4_t test___riscv_vadd_tumu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,vl); +} + + +vuint16mf2_t test___riscv_vadd_tumu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,vl); +} + + +vuint16m1_t test___riscv_vadd_tumu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,vl); +} + + +vuint16m2_t test___riscv_vadd_tumu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,vl); +} + + +vuint16m4_t test___riscv_vadd_tumu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,vl); +} + + +vuint16m8_t test___riscv_vadd_tumu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,vl); +} + + +vuint32mf2_t test___riscv_vadd_tumu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,vl); +} + + +vuint32m1_t test___riscv_vadd_tumu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,vl); +} + + +vuint32m2_t test___riscv_vadd_tumu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,vl); +} + + +vuint32m4_t test___riscv_vadd_tumu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,vl); +} + + +vuint32m8_t test___riscv_vadd_tumu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,vl); +} + + +vuint64m1_t test___riscv_vadd_tumu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,vl); +} + + +vuint64m2_t test___riscv_vadd_tumu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,vl); +} + + +vuint64m4_t test___riscv_vadd_tumu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,vl); +} + + +vuint64m8_t test___riscv_vadd_tumu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 8 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_tumu_rv32-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_tumu_rv32-2.C new file mode 100644 index 00000000000..65655949df6 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_tumu_rv32-2.C @@ -0,0 +1,289 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vadd_tumu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,31); +} + + +vint8mf4_t test___riscv_vadd_tumu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,31); +} + + +vint8mf2_t test___riscv_vadd_tumu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,31); +} + + +vint8m1_t test___riscv_vadd_tumu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,31); +} + + +vint8m2_t test___riscv_vadd_tumu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,31); +} + + +vint8m4_t test___riscv_vadd_tumu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,31); +} + + +vint8m8_t test___riscv_vadd_tumu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,31); +} + + +vint16mf4_t test___riscv_vadd_tumu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,31); +} + + +vint16mf2_t test___riscv_vadd_tumu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,31); +} + + +vint16m1_t test___riscv_vadd_tumu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,31); +} + + +vint16m2_t test___riscv_vadd_tumu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,31); +} + + +vint16m4_t test___riscv_vadd_tumu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,31); +} + + +vint16m8_t test___riscv_vadd_tumu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,31); +} + + +vint32mf2_t test___riscv_vadd_tumu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,31); +} + + +vint32m1_t test___riscv_vadd_tumu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,31); +} + + +vint32m2_t test___riscv_vadd_tumu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,31); +} + + +vint32m4_t test___riscv_vadd_tumu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,31); +} + + +vint32m8_t test___riscv_vadd_tumu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,31); +} + + +vint64m1_t test___riscv_vadd_tumu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,31); +} + + +vint64m2_t test___riscv_vadd_tumu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,31); +} + + +vint64m4_t test___riscv_vadd_tumu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,31); +} + + +vint64m8_t test___riscv_vadd_tumu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,31); +} + + +vuint8mf8_t test___riscv_vadd_tumu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,31); +} + + +vuint8mf4_t test___riscv_vadd_tumu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,31); +} + + +vuint8mf2_t test___riscv_vadd_tumu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,31); +} + + +vuint8m1_t test___riscv_vadd_tumu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,31); +} + + +vuint8m2_t test___riscv_vadd_tumu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,31); +} + + +vuint8m4_t test___riscv_vadd_tumu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,31); +} + + +vuint8m8_t test___riscv_vadd_tumu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,31); +} + + +vuint16mf4_t test___riscv_vadd_tumu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,31); +} + + +vuint16mf2_t test___riscv_vadd_tumu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,31); +} + + +vuint16m1_t test___riscv_vadd_tumu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,31); +} + + +vuint16m2_t test___riscv_vadd_tumu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,31); +} + + +vuint16m4_t test___riscv_vadd_tumu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,31); +} + + +vuint16m8_t test___riscv_vadd_tumu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,31); +} + + +vuint32mf2_t test___riscv_vadd_tumu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,31); +} + + +vuint32m1_t test___riscv_vadd_tumu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,31); +} + + +vuint32m2_t test___riscv_vadd_tumu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,31); +} + + +vuint32m4_t test___riscv_vadd_tumu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,31); +} + + +vuint32m8_t test___riscv_vadd_tumu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,31); +} + + +vuint64m1_t test___riscv_vadd_tumu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,31); +} + + +vuint64m2_t test___riscv_vadd_tumu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,31); +} + + +vuint64m4_t test___riscv_vadd_tumu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,31); +} + + +vuint64m8_t test___riscv_vadd_tumu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 8 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_tumu_rv32-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_tumu_rv32-3.C new file mode 100644 index 00000000000..8013027670d --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_tumu_rv32-3.C @@ -0,0 +1,289 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vadd_tumu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,32); +} + + +vint8mf4_t test___riscv_vadd_tumu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,32); +} + + +vint8mf2_t test___riscv_vadd_tumu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,32); +} + + +vint8m1_t test___riscv_vadd_tumu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,32); +} + + +vint8m2_t test___riscv_vadd_tumu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,32); +} + + +vint8m4_t test___riscv_vadd_tumu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,32); +} + + +vint8m8_t test___riscv_vadd_tumu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,32); +} + + +vint16mf4_t test___riscv_vadd_tumu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,32); +} + + +vint16mf2_t test___riscv_vadd_tumu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,32); +} + + +vint16m1_t test___riscv_vadd_tumu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,32); +} + + +vint16m2_t test___riscv_vadd_tumu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,32); +} + + +vint16m4_t test___riscv_vadd_tumu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,32); +} + + +vint16m8_t test___riscv_vadd_tumu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,32); +} + + +vint32mf2_t test___riscv_vadd_tumu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,32); +} + + +vint32m1_t test___riscv_vadd_tumu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,32); +} + + +vint32m2_t test___riscv_vadd_tumu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,32); +} + + +vint32m4_t test___riscv_vadd_tumu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,32); +} + + +vint32m8_t test___riscv_vadd_tumu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,32); +} + + +vint64m1_t test___riscv_vadd_tumu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,32); +} + + +vint64m2_t test___riscv_vadd_tumu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,32); +} + + +vint64m4_t test___riscv_vadd_tumu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,32); +} + + +vint64m8_t test___riscv_vadd_tumu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,32); +} + + +vuint8mf8_t test___riscv_vadd_tumu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,32); +} + + +vuint8mf4_t test___riscv_vadd_tumu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,32); +} + + +vuint8mf2_t test___riscv_vadd_tumu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,32); +} + + +vuint8m1_t test___riscv_vadd_tumu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,32); +} + + +vuint8m2_t test___riscv_vadd_tumu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,32); +} + + +vuint8m4_t test___riscv_vadd_tumu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,32); +} + + +vuint8m8_t test___riscv_vadd_tumu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,32); +} + + +vuint16mf4_t test___riscv_vadd_tumu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,32); +} + + +vuint16mf2_t test___riscv_vadd_tumu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,32); +} + + +vuint16m1_t test___riscv_vadd_tumu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,32); +} + + +vuint16m2_t test___riscv_vadd_tumu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,32); +} + + +vuint16m4_t test___riscv_vadd_tumu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,32); +} + + +vuint16m8_t test___riscv_vadd_tumu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,32); +} + + +vuint32mf2_t test___riscv_vadd_tumu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,32); +} + + +vuint32m1_t test___riscv_vadd_tumu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,32); +} + + +vuint32m2_t test___riscv_vadd_tumu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,32); +} + + +vuint32m4_t test___riscv_vadd_tumu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,32); +} + + +vuint32m8_t test___riscv_vadd_tumu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,32); +} + + +vuint64m1_t test___riscv_vadd_tumu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,32); +} + + +vuint64m2_t test___riscv_vadd_tumu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,32); +} + + +vuint64m4_t test___riscv_vadd_tumu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,32); +} + + +vuint64m8_t test___riscv_vadd_tumu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 8 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_tumu_rv64-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_tumu_rv64-1.C new file mode 100644 index 00000000000..e33ae90a3c6 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_tumu_rv64-1.C @@ -0,0 +1,292 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vadd_tumu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,vl); +} + + +vint8mf4_t test___riscv_vadd_tumu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,vl); +} + + +vint8mf2_t test___riscv_vadd_tumu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,vl); +} + + +vint8m1_t test___riscv_vadd_tumu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,vl); +} + + +vint8m2_t test___riscv_vadd_tumu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,vl); +} + + +vint8m4_t test___riscv_vadd_tumu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,vl); +} + + +vint8m8_t test___riscv_vadd_tumu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,vl); +} + + +vint16mf4_t test___riscv_vadd_tumu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,vl); +} + + +vint16mf2_t test___riscv_vadd_tumu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,vl); +} + + +vint16m1_t test___riscv_vadd_tumu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,vl); +} + + +vint16m2_t test___riscv_vadd_tumu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,vl); +} + + +vint16m4_t test___riscv_vadd_tumu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,vl); +} + + +vint16m8_t test___riscv_vadd_tumu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,vl); +} + + +vint32mf2_t test___riscv_vadd_tumu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,vl); +} + + +vint32m1_t test___riscv_vadd_tumu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,vl); +} + + +vint32m2_t test___riscv_vadd_tumu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,vl); +} + + +vint32m4_t test___riscv_vadd_tumu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,vl); +} + + +vint32m8_t test___riscv_vadd_tumu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,vl); +} + + +vint64m1_t test___riscv_vadd_tumu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,vl); +} + + +vint64m2_t test___riscv_vadd_tumu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,vl); +} + + +vint64m4_t test___riscv_vadd_tumu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,vl); +} + + +vint64m8_t test___riscv_vadd_tumu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,vl); +} + + +vuint8mf8_t test___riscv_vadd_tumu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,vl); +} + + +vuint8mf4_t test___riscv_vadd_tumu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,vl); +} + + +vuint8mf2_t test___riscv_vadd_tumu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,vl); +} + + +vuint8m1_t test___riscv_vadd_tumu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,vl); +} + + +vuint8m2_t test___riscv_vadd_tumu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,vl); +} + + +vuint8m4_t test___riscv_vadd_tumu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,vl); +} + + +vuint8m8_t test___riscv_vadd_tumu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,vl); +} + + +vuint16mf4_t test___riscv_vadd_tumu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,vl); +} + + +vuint16mf2_t test___riscv_vadd_tumu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,vl); +} + + +vuint16m1_t test___riscv_vadd_tumu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,vl); +} + + +vuint16m2_t test___riscv_vadd_tumu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,vl); +} + + +vuint16m4_t test___riscv_vadd_tumu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,vl); +} + + +vuint16m8_t test___riscv_vadd_tumu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,vl); +} + + +vuint32mf2_t test___riscv_vadd_tumu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,vl); +} + + +vuint32m1_t test___riscv_vadd_tumu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,vl); +} + + +vuint32m2_t test___riscv_vadd_tumu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,vl); +} + + +vuint32m4_t test___riscv_vadd_tumu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,vl); +} + + +vuint32m8_t test___riscv_vadd_tumu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,vl); +} + + +vuint64m1_t test___riscv_vadd_tumu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,vl); +} + + +vuint64m2_t test___riscv_vadd_tumu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,vl); +} + + +vuint64m4_t test___riscv_vadd_tumu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,vl); +} + + +vuint64m8_t test___riscv_vadd_tumu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_tumu_rv64-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_tumu_rv64-2.C new file mode 100644 index 00000000000..560b9d355f5 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_tumu_rv64-2.C @@ -0,0 +1,292 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vadd_tumu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,31); +} + + +vint8mf4_t test___riscv_vadd_tumu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,31); +} + + +vint8mf2_t test___riscv_vadd_tumu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,31); +} + + +vint8m1_t test___riscv_vadd_tumu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,31); +} + + +vint8m2_t test___riscv_vadd_tumu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,31); +} + + +vint8m4_t test___riscv_vadd_tumu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,31); +} + + +vint8m8_t test___riscv_vadd_tumu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,31); +} + + +vint16mf4_t test___riscv_vadd_tumu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,31); +} + + +vint16mf2_t test___riscv_vadd_tumu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,31); +} + + +vint16m1_t test___riscv_vadd_tumu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,31); +} + + +vint16m2_t test___riscv_vadd_tumu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,31); +} + + +vint16m4_t test___riscv_vadd_tumu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,31); +} + + +vint16m8_t test___riscv_vadd_tumu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,31); +} + + +vint32mf2_t test___riscv_vadd_tumu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,31); +} + + +vint32m1_t test___riscv_vadd_tumu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,31); +} + + +vint32m2_t test___riscv_vadd_tumu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,31); +} + + +vint32m4_t test___riscv_vadd_tumu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,31); +} + + +vint32m8_t test___riscv_vadd_tumu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,31); +} + + +vint64m1_t test___riscv_vadd_tumu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,31); +} + + +vint64m2_t test___riscv_vadd_tumu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,31); +} + + +vint64m4_t test___riscv_vadd_tumu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,31); +} + + +vint64m8_t test___riscv_vadd_tumu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,31); +} + + +vuint8mf8_t test___riscv_vadd_tumu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,31); +} + + +vuint8mf4_t test___riscv_vadd_tumu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,31); +} + + +vuint8mf2_t test___riscv_vadd_tumu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,31); +} + + +vuint8m1_t test___riscv_vadd_tumu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,31); +} + + +vuint8m2_t test___riscv_vadd_tumu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,31); +} + + +vuint8m4_t test___riscv_vadd_tumu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,31); +} + + +vuint8m8_t test___riscv_vadd_tumu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,31); +} + + +vuint16mf4_t test___riscv_vadd_tumu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,31); +} + + +vuint16mf2_t test___riscv_vadd_tumu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,31); +} + + +vuint16m1_t test___riscv_vadd_tumu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,31); +} + + +vuint16m2_t test___riscv_vadd_tumu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,31); +} + + +vuint16m4_t test___riscv_vadd_tumu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,31); +} + + +vuint16m8_t test___riscv_vadd_tumu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,31); +} + + +vuint32mf2_t test___riscv_vadd_tumu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,31); +} + + +vuint32m1_t test___riscv_vadd_tumu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,31); +} + + +vuint32m2_t test___riscv_vadd_tumu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,31); +} + + +vuint32m4_t test___riscv_vadd_tumu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,31); +} + + +vuint32m8_t test___riscv_vadd_tumu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,31); +} + + +vuint64m1_t test___riscv_vadd_tumu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,31); +} + + +vuint64m2_t test___riscv_vadd_tumu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,31); +} + + +vuint64m4_t test___riscv_vadd_tumu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,31); +} + + +vuint64m8_t test___riscv_vadd_tumu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_tumu_rv64-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_tumu_rv64-3.C new file mode 100644 index 00000000000..2ff074ac409 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_tumu_rv64-3.C @@ -0,0 +1,292 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vadd_tumu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,32); +} + + +vint8mf4_t test___riscv_vadd_tumu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,32); +} + + +vint8mf2_t test___riscv_vadd_tumu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,32); +} + + +vint8m1_t test___riscv_vadd_tumu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,32); +} + + +vint8m2_t test___riscv_vadd_tumu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,32); +} + + +vint8m4_t test___riscv_vadd_tumu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,32); +} + + +vint8m8_t test___riscv_vadd_tumu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,32); +} + + +vint16mf4_t test___riscv_vadd_tumu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,32); +} + + +vint16mf2_t test___riscv_vadd_tumu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,32); +} + + +vint16m1_t test___riscv_vadd_tumu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,32); +} + + +vint16m2_t test___riscv_vadd_tumu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,32); +} + + +vint16m4_t test___riscv_vadd_tumu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,32); +} + + +vint16m8_t test___riscv_vadd_tumu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,32); +} + + +vint32mf2_t test___riscv_vadd_tumu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,32); +} + + +vint32m1_t test___riscv_vadd_tumu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,32); +} + + +vint32m2_t test___riscv_vadd_tumu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,32); +} + + +vint32m4_t test___riscv_vadd_tumu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,32); +} + + +vint32m8_t test___riscv_vadd_tumu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,32); +} + + +vint64m1_t test___riscv_vadd_tumu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,32); +} + + +vint64m2_t test___riscv_vadd_tumu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,32); +} + + +vint64m4_t test___riscv_vadd_tumu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,32); +} + + +vint64m8_t test___riscv_vadd_tumu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,32); +} + + +vuint8mf8_t test___riscv_vadd_tumu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,32); +} + + +vuint8mf4_t test___riscv_vadd_tumu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,32); +} + + +vuint8mf2_t test___riscv_vadd_tumu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,32); +} + + +vuint8m1_t test___riscv_vadd_tumu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,32); +} + + +vuint8m2_t test___riscv_vadd_tumu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,32); +} + + +vuint8m4_t test___riscv_vadd_tumu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,32); +} + + +vuint8m8_t test___riscv_vadd_tumu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,32); +} + + +vuint16mf4_t test___riscv_vadd_tumu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,32); +} + + +vuint16mf2_t test___riscv_vadd_tumu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,32); +} + + +vuint16m1_t test___riscv_vadd_tumu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,32); +} + + +vuint16m2_t test___riscv_vadd_tumu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,32); +} + + +vuint16m4_t test___riscv_vadd_tumu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,32); +} + + +vuint16m8_t test___riscv_vadd_tumu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,32); +} + + +vuint32mf2_t test___riscv_vadd_tumu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,32); +} + + +vuint32m1_t test___riscv_vadd_tumu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,32); +} + + +vuint32m2_t test___riscv_vadd_tumu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,32); +} + + +vuint32m4_t test___riscv_vadd_tumu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,32); +} + + +vuint32m8_t test___riscv_vadd_tumu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,32); +} + + +vuint64m1_t test___riscv_vadd_tumu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,32); +} + + +vuint64m2_t test___riscv_vadd_tumu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,32); +} + + +vuint64m4_t test___riscv_vadd_tumu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,32); +} + + +vuint64m8_t test___riscv_vadd_tumu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*mu\s+vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */