diff mbox series

RISC-V: Add vxor.vx C++ API tests

Message ID 20230203074024.196307-1-juzhe.zhong@rivai.ai
State Committed
Commit 7d8c4a59fdf1dd0bd5303eb50761b114fd7bd8b7
Headers
Series RISC-V: Add vxor.vx C++ API tests |

Commit Message

juzhe.zhong@rivai.ai Feb. 3, 2023, 7:40 a.m. UTC 
  From: Ju-Zhe Zhong <juzhe.zhong@rivai.ai>

gcc/testsuite/ChangeLog:

        * g++.target/riscv/rvv/base/vxor_vx_mu_rv32-1.C: New test.
        * g++.target/riscv/rvv/base/vxor_vx_mu_rv32-2.C: New test.
        * g++.target/riscv/rvv/base/vxor_vx_mu_rv32-3.C: New test.
        * g++.target/riscv/rvv/base/vxor_vx_mu_rv64-1.C: New test.
        * g++.target/riscv/rvv/base/vxor_vx_mu_rv64-2.C: New test.
        * g++.target/riscv/rvv/base/vxor_vx_mu_rv64-3.C: New test.
        * g++.target/riscv/rvv/base/vxor_vx_rv32-1.C: New test.
        * g++.target/riscv/rvv/base/vxor_vx_rv32-2.C: New test.
        * g++.target/riscv/rvv/base/vxor_vx_rv32-3.C: New test.
        * g++.target/riscv/rvv/base/vxor_vx_rv64-1.C: New test.
        * g++.target/riscv/rvv/base/vxor_vx_rv64-2.C: New test.
        * g++.target/riscv/rvv/base/vxor_vx_rv64-3.C: New test.
        * g++.target/riscv/rvv/base/vxor_vx_tu_rv32-1.C: New test.
        * g++.target/riscv/rvv/base/vxor_vx_tu_rv32-2.C: New test.
        * g++.target/riscv/rvv/base/vxor_vx_tu_rv32-3.C: New test.
        * g++.target/riscv/rvv/base/vxor_vx_tu_rv64-1.C: New test.
        * g++.target/riscv/rvv/base/vxor_vx_tu_rv64-2.C: New test.
        * g++.target/riscv/rvv/base/vxor_vx_tu_rv64-3.C: New test.
        * g++.target/riscv/rvv/base/vxor_vx_tum_rv32-1.C: New test.
        * g++.target/riscv/rvv/base/vxor_vx_tum_rv32-2.C: New test.
        * g++.target/riscv/rvv/base/vxor_vx_tum_rv32-3.C: New test.
        * g++.target/riscv/rvv/base/vxor_vx_tum_rv64-1.C: New test.
        * g++.target/riscv/rvv/base/vxor_vx_tum_rv64-2.C: New test.
        * g++.target/riscv/rvv/base/vxor_vx_tum_rv64-3.C: New test.
        * g++.target/riscv/rvv/base/vxor_vx_tumu_rv32-1.C: New test.
        * g++.target/riscv/rvv/base/vxor_vx_tumu_rv32-2.C: New test.
        * g++.target/riscv/rvv/base/vxor_vx_tumu_rv32-3.C: New test.
        * g++.target/riscv/rvv/base/vxor_vx_tumu_rv64-1.C: New test.
        * g++.target/riscv/rvv/base/vxor_vx_tumu_rv64-2.C: New test.
        * g++.target/riscv/rvv/base/vxor_vx_tumu_rv64-3.C: New test.

---
 .../riscv/rvv/base/vxor_vx_mu_rv32-1.C        | 289 +++++++++
 .../riscv/rvv/base/vxor_vx_mu_rv32-2.C        | 289 +++++++++
 .../riscv/rvv/base/vxor_vx_mu_rv32-3.C        | 289 +++++++++
 .../riscv/rvv/base/vxor_vx_mu_rv64-1.C        | 292 +++++++++
 .../riscv/rvv/base/vxor_vx_mu_rv64-2.C        | 292 +++++++++
 .../riscv/rvv/base/vxor_vx_mu_rv64-3.C        | 292 +++++++++
 .../riscv/rvv/base/vxor_vx_rv32-1.C           | 572 +++++++++++++++++
 .../riscv/rvv/base/vxor_vx_rv32-2.C           | 572 +++++++++++++++++
 .../riscv/rvv/base/vxor_vx_rv32-3.C           | 572 +++++++++++++++++
 .../riscv/rvv/base/vxor_vx_rv64-1.C           | 578 ++++++++++++++++++
 .../riscv/rvv/base/vxor_vx_rv64-2.C           | 578 ++++++++++++++++++
 .../riscv/rvv/base/vxor_vx_rv64-3.C           | 578 ++++++++++++++++++
 .../riscv/rvv/base/vxor_vx_tu_rv32-1.C        | 289 +++++++++
 .../riscv/rvv/base/vxor_vx_tu_rv32-2.C        | 289 +++++++++
 .../riscv/rvv/base/vxor_vx_tu_rv32-3.C        | 289 +++++++++
 .../riscv/rvv/base/vxor_vx_tu_rv64-1.C        | 292 +++++++++
 .../riscv/rvv/base/vxor_vx_tu_rv64-2.C        | 292 +++++++++
 .../riscv/rvv/base/vxor_vx_tu_rv64-3.C        | 292 +++++++++
 .../riscv/rvv/base/vxor_vx_tum_rv32-1.C       | 289 +++++++++
 .../riscv/rvv/base/vxor_vx_tum_rv32-2.C       | 289 +++++++++
 .../riscv/rvv/base/vxor_vx_tum_rv32-3.C       | 289 +++++++++
 .../riscv/rvv/base/vxor_vx_tum_rv64-1.C       | 292 +++++++++
 .../riscv/rvv/base/vxor_vx_tum_rv64-2.C       | 292 +++++++++
 .../riscv/rvv/base/vxor_vx_tum_rv64-3.C       | 292 +++++++++
 .../riscv/rvv/base/vxor_vx_tumu_rv32-1.C      | 289 +++++++++
 .../riscv/rvv/base/vxor_vx_tumu_rv32-2.C      | 289 +++++++++
 .../riscv/rvv/base/vxor_vx_tumu_rv32-3.C      | 289 +++++++++
 .../riscv/rvv/base/vxor_vx_tumu_rv64-1.C      | 292 +++++++++
 .../riscv/rvv/base/vxor_vx_tumu_rv64-2.C      | 292 +++++++++
 .../riscv/rvv/base/vxor_vx_tumu_rv64-3.C      | 292 +++++++++
 30 files changed, 10422 insertions(+)
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vxor_vx_mu_rv32-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vxor_vx_mu_rv32-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vxor_vx_mu_rv32-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vxor_vx_mu_rv64-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vxor_vx_mu_rv64-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vxor_vx_mu_rv64-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vxor_vx_rv32-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vxor_vx_rv32-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vxor_vx_rv32-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vxor_vx_rv64-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vxor_vx_rv64-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vxor_vx_rv64-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vxor_vx_tu_rv32-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vxor_vx_tu_rv32-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vxor_vx_tu_rv32-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vxor_vx_tu_rv64-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vxor_vx_tu_rv64-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vxor_vx_tu_rv64-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vxor_vx_tum_rv32-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vxor_vx_tum_rv32-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vxor_vx_tum_rv32-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vxor_vx_tum_rv64-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vxor_vx_tum_rv64-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vxor_vx_tum_rv64-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vxor_vx_tumu_rv32-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vxor_vx_tumu_rv32-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vxor_vx_tumu_rv32-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vxor_vx_tumu_rv64-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vxor_vx_tumu_rv64-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vxor_vx_tumu_rv64-3.C
diff mbox series

Patch

diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vxor_vx_mu_rv32-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vxor_vx_mu_rv32-1.C
new file mode 100644
index 00000000000..bfeac5bdcd9
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vxor_vx_mu_rv32-1.C
@@ -0,0 +1,289 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vxor_mu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint8mf4_t test___riscv_vxor_mu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint8mf2_t test___riscv_vxor_mu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint8m1_t test___riscv_vxor_mu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint8m2_t test___riscv_vxor_mu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint8m4_t test___riscv_vxor_mu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint8m8_t test___riscv_vxor_mu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint16mf4_t test___riscv_vxor_mu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint16mf2_t test___riscv_vxor_mu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint16m1_t test___riscv_vxor_mu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint16m2_t test___riscv_vxor_mu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint16m4_t test___riscv_vxor_mu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint16m8_t test___riscv_vxor_mu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint32mf2_t test___riscv_vxor_mu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint32m1_t test___riscv_vxor_mu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint32m2_t test___riscv_vxor_mu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint32m4_t test___riscv_vxor_mu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint32m8_t test___riscv_vxor_mu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint64m1_t test___riscv_vxor_mu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint64m2_t test___riscv_vxor_mu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint64m4_t test___riscv_vxor_mu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint64m8_t test___riscv_vxor_mu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint8mf8_t test___riscv_vxor_mu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint8mf4_t test___riscv_vxor_mu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint8mf2_t test___riscv_vxor_mu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint8m1_t test___riscv_vxor_mu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint8m2_t test___riscv_vxor_mu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint8m4_t test___riscv_vxor_mu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint8m8_t test___riscv_vxor_mu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint16mf4_t test___riscv_vxor_mu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint16mf2_t test___riscv_vxor_mu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m1_t test___riscv_vxor_mu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m2_t test___riscv_vxor_mu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m4_t test___riscv_vxor_mu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m8_t test___riscv_vxor_mu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint32mf2_t test___riscv_vxor_mu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m1_t test___riscv_vxor_mu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m2_t test___riscv_vxor_mu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m4_t test___riscv_vxor_mu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m8_t test___riscv_vxor_mu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m1_t test___riscv_vxor_mu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m2_t test___riscv_vxor_mu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m4_t test___riscv_vxor_mu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m8_t test___riscv_vxor_mu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 8 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vxor_vx_mu_rv32-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vxor_vx_mu_rv32-2.C
new file mode 100644
index 00000000000..fe89c832136
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vxor_vx_mu_rv32-2.C
@@ -0,0 +1,289 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vxor_mu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,31);
+}
+
+
+vint8mf4_t test___riscv_vxor_mu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,31);
+}
+
+
+vint8mf2_t test___riscv_vxor_mu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,31);
+}
+
+
+vint8m1_t test___riscv_vxor_mu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,31);
+}
+
+
+vint8m2_t test___riscv_vxor_mu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,31);
+}
+
+
+vint8m4_t test___riscv_vxor_mu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,31);
+}
+
+
+vint8m8_t test___riscv_vxor_mu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,31);
+}
+
+
+vint16mf4_t test___riscv_vxor_mu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,31);
+}
+
+
+vint16mf2_t test___riscv_vxor_mu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,31);
+}
+
+
+vint16m1_t test___riscv_vxor_mu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,31);
+}
+
+
+vint16m2_t test___riscv_vxor_mu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,31);
+}
+
+
+vint16m4_t test___riscv_vxor_mu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,31);
+}
+
+
+vint16m8_t test___riscv_vxor_mu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,31);
+}
+
+
+vint32mf2_t test___riscv_vxor_mu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,31);
+}
+
+
+vint32m1_t test___riscv_vxor_mu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,31);
+}
+
+
+vint32m2_t test___riscv_vxor_mu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,31);
+}
+
+
+vint32m4_t test___riscv_vxor_mu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,31);
+}
+
+
+vint32m8_t test___riscv_vxor_mu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,31);
+}
+
+
+vint64m1_t test___riscv_vxor_mu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,31);
+}
+
+
+vint64m2_t test___riscv_vxor_mu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,31);
+}
+
+
+vint64m4_t test___riscv_vxor_mu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,31);
+}
+
+
+vint64m8_t test___riscv_vxor_mu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint8mf8_t test___riscv_vxor_mu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint8mf4_t test___riscv_vxor_mu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint8mf2_t test___riscv_vxor_mu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint8m1_t test___riscv_vxor_mu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint8m2_t test___riscv_vxor_mu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint8m4_t test___riscv_vxor_mu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint8m8_t test___riscv_vxor_mu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint16mf4_t test___riscv_vxor_mu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint16mf2_t test___riscv_vxor_mu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint16m1_t test___riscv_vxor_mu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint16m2_t test___riscv_vxor_mu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint16m4_t test___riscv_vxor_mu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint16m8_t test___riscv_vxor_mu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint32mf2_t test___riscv_vxor_mu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint32m1_t test___riscv_vxor_mu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint32m2_t test___riscv_vxor_mu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint32m4_t test___riscv_vxor_mu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint32m8_t test___riscv_vxor_mu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint64m1_t test___riscv_vxor_mu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint64m2_t test___riscv_vxor_mu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint64m4_t test___riscv_vxor_mu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint64m8_t test___riscv_vxor_mu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 8 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vxor_vx_mu_rv32-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vxor_vx_mu_rv32-3.C
new file mode 100644
index 00000000000..3e8556a0c38
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vxor_vx_mu_rv32-3.C
@@ -0,0 +1,289 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vxor_mu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,32);
+}
+
+
+vint8mf4_t test___riscv_vxor_mu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,32);
+}
+
+
+vint8mf2_t test___riscv_vxor_mu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,32);
+}
+
+
+vint8m1_t test___riscv_vxor_mu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,32);
+}
+
+
+vint8m2_t test___riscv_vxor_mu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,32);
+}
+
+
+vint8m4_t test___riscv_vxor_mu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,32);
+}
+
+
+vint8m8_t test___riscv_vxor_mu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,32);
+}
+
+
+vint16mf4_t test___riscv_vxor_mu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,32);
+}
+
+
+vint16mf2_t test___riscv_vxor_mu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,32);
+}
+
+
+vint16m1_t test___riscv_vxor_mu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,32);
+}
+
+
+vint16m2_t test___riscv_vxor_mu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,32);
+}
+
+
+vint16m4_t test___riscv_vxor_mu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,32);
+}
+
+
+vint16m8_t test___riscv_vxor_mu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,32);
+}
+
+
+vint32mf2_t test___riscv_vxor_mu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,32);
+}
+
+
+vint32m1_t test___riscv_vxor_mu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,32);
+}
+
+
+vint32m2_t test___riscv_vxor_mu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,32);
+}
+
+
+vint32m4_t test___riscv_vxor_mu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,32);
+}
+
+
+vint32m8_t test___riscv_vxor_mu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,32);
+}
+
+
+vint64m1_t test___riscv_vxor_mu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,32);
+}
+
+
+vint64m2_t test___riscv_vxor_mu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,32);
+}
+
+
+vint64m4_t test___riscv_vxor_mu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,32);
+}
+
+
+vint64m8_t test___riscv_vxor_mu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint8mf8_t test___riscv_vxor_mu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint8mf4_t test___riscv_vxor_mu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint8mf2_t test___riscv_vxor_mu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint8m1_t test___riscv_vxor_mu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint8m2_t test___riscv_vxor_mu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint8m4_t test___riscv_vxor_mu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint8m8_t test___riscv_vxor_mu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint16mf4_t test___riscv_vxor_mu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint16mf2_t test___riscv_vxor_mu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint16m1_t test___riscv_vxor_mu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint16m2_t test___riscv_vxor_mu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint16m4_t test___riscv_vxor_mu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint16m8_t test___riscv_vxor_mu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint32mf2_t test___riscv_vxor_mu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint32m1_t test___riscv_vxor_mu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint32m2_t test___riscv_vxor_mu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint32m4_t test___riscv_vxor_mu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint32m8_t test___riscv_vxor_mu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint64m1_t test___riscv_vxor_mu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint64m2_t test___riscv_vxor_mu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint64m4_t test___riscv_vxor_mu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint64m8_t test___riscv_vxor_mu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 8 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vxor_vx_mu_rv64-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vxor_vx_mu_rv64-1.C
new file mode 100644
index 00000000000..7ea0054a01c
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vxor_vx_mu_rv64-1.C
@@ -0,0 +1,292 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vxor_mu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint8mf4_t test___riscv_vxor_mu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint8mf2_t test___riscv_vxor_mu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint8m1_t test___riscv_vxor_mu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint8m2_t test___riscv_vxor_mu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint8m4_t test___riscv_vxor_mu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint8m8_t test___riscv_vxor_mu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint16mf4_t test___riscv_vxor_mu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint16mf2_t test___riscv_vxor_mu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint16m1_t test___riscv_vxor_mu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint16m2_t test___riscv_vxor_mu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint16m4_t test___riscv_vxor_mu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint16m8_t test___riscv_vxor_mu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint32mf2_t test___riscv_vxor_mu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint32m1_t test___riscv_vxor_mu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint32m2_t test___riscv_vxor_mu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint32m4_t test___riscv_vxor_mu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint32m8_t test___riscv_vxor_mu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint64m1_t test___riscv_vxor_mu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint64m2_t test___riscv_vxor_mu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint64m4_t test___riscv_vxor_mu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint64m8_t test___riscv_vxor_mu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint8mf8_t test___riscv_vxor_mu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint8mf4_t test___riscv_vxor_mu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint8mf2_t test___riscv_vxor_mu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint8m1_t test___riscv_vxor_mu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint8m2_t test___riscv_vxor_mu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint8m4_t test___riscv_vxor_mu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint8m8_t test___riscv_vxor_mu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint16mf4_t test___riscv_vxor_mu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint16mf2_t test___riscv_vxor_mu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m1_t test___riscv_vxor_mu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m2_t test___riscv_vxor_mu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m4_t test___riscv_vxor_mu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m8_t test___riscv_vxor_mu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint32mf2_t test___riscv_vxor_mu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m1_t test___riscv_vxor_mu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m2_t test___riscv_vxor_mu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m4_t test___riscv_vxor_mu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m8_t test___riscv_vxor_mu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m1_t test___riscv_vxor_mu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m2_t test___riscv_vxor_mu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m4_t test___riscv_vxor_mu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m8_t test___riscv_vxor_mu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vxor_vx_mu_rv64-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vxor_vx_mu_rv64-2.C
new file mode 100644
index 00000000000..1f8167b1209
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vxor_vx_mu_rv64-2.C
@@ -0,0 +1,292 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vxor_mu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,31);
+}
+
+
+vint8mf4_t test___riscv_vxor_mu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,31);
+}
+
+
+vint8mf2_t test___riscv_vxor_mu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,31);
+}
+
+
+vint8m1_t test___riscv_vxor_mu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,31);
+}
+
+
+vint8m2_t test___riscv_vxor_mu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,31);
+}
+
+
+vint8m4_t test___riscv_vxor_mu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,31);
+}
+
+
+vint8m8_t test___riscv_vxor_mu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,31);
+}
+
+
+vint16mf4_t test___riscv_vxor_mu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,31);
+}
+
+
+vint16mf2_t test___riscv_vxor_mu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,31);
+}
+
+
+vint16m1_t test___riscv_vxor_mu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,31);
+}
+
+
+vint16m2_t test___riscv_vxor_mu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,31);
+}
+
+
+vint16m4_t test___riscv_vxor_mu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,31);
+}
+
+
+vint16m8_t test___riscv_vxor_mu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,31);
+}
+
+
+vint32mf2_t test___riscv_vxor_mu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,31);
+}
+
+
+vint32m1_t test___riscv_vxor_mu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,31);
+}
+
+
+vint32m2_t test___riscv_vxor_mu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,31);
+}
+
+
+vint32m4_t test___riscv_vxor_mu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,31);
+}
+
+
+vint32m8_t test___riscv_vxor_mu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,31);
+}
+
+
+vint64m1_t test___riscv_vxor_mu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,31);
+}
+
+
+vint64m2_t test___riscv_vxor_mu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,31);
+}
+
+
+vint64m4_t test___riscv_vxor_mu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,31);
+}
+
+
+vint64m8_t test___riscv_vxor_mu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint8mf8_t test___riscv_vxor_mu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint8mf4_t test___riscv_vxor_mu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint8mf2_t test___riscv_vxor_mu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint8m1_t test___riscv_vxor_mu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint8m2_t test___riscv_vxor_mu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint8m4_t test___riscv_vxor_mu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint8m8_t test___riscv_vxor_mu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint16mf4_t test___riscv_vxor_mu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint16mf2_t test___riscv_vxor_mu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint16m1_t test___riscv_vxor_mu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint16m2_t test___riscv_vxor_mu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint16m4_t test___riscv_vxor_mu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint16m8_t test___riscv_vxor_mu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint32mf2_t test___riscv_vxor_mu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint32m1_t test___riscv_vxor_mu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint32m2_t test___riscv_vxor_mu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint32m4_t test___riscv_vxor_mu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint32m8_t test___riscv_vxor_mu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint64m1_t test___riscv_vxor_mu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint64m2_t test___riscv_vxor_mu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint64m4_t test___riscv_vxor_mu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint64m8_t test___riscv_vxor_mu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vxor_vx_mu_rv64-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vxor_vx_mu_rv64-3.C
new file mode 100644
index 00000000000..67fb085c903
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vxor_vx_mu_rv64-3.C
@@ -0,0 +1,292 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vxor_mu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,32);
+}
+
+
+vint8mf4_t test___riscv_vxor_mu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,32);
+}
+
+
+vint8mf2_t test___riscv_vxor_mu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,32);
+}
+
+
+vint8m1_t test___riscv_vxor_mu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,32);
+}
+
+
+vint8m2_t test___riscv_vxor_mu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,32);
+}
+
+
+vint8m4_t test___riscv_vxor_mu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,32);
+}
+
+
+vint8m8_t test___riscv_vxor_mu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,32);
+}
+
+
+vint16mf4_t test___riscv_vxor_mu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,32);
+}
+
+
+vint16mf2_t test___riscv_vxor_mu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,32);
+}
+
+
+vint16m1_t test___riscv_vxor_mu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,32);
+}
+
+
+vint16m2_t test___riscv_vxor_mu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,32);
+}
+
+
+vint16m4_t test___riscv_vxor_mu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,32);
+}
+
+
+vint16m8_t test___riscv_vxor_mu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,32);
+}
+
+
+vint32mf2_t test___riscv_vxor_mu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,32);
+}
+
+
+vint32m1_t test___riscv_vxor_mu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,32);
+}
+
+
+vint32m2_t test___riscv_vxor_mu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,32);
+}
+
+
+vint32m4_t test___riscv_vxor_mu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,32);
+}
+
+
+vint32m8_t test___riscv_vxor_mu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,32);
+}
+
+
+vint64m1_t test___riscv_vxor_mu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,32);
+}
+
+
+vint64m2_t test___riscv_vxor_mu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,32);
+}
+
+
+vint64m4_t test___riscv_vxor_mu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,32);
+}
+
+
+vint64m8_t test___riscv_vxor_mu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint8mf8_t test___riscv_vxor_mu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint8mf4_t test___riscv_vxor_mu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint8mf2_t test___riscv_vxor_mu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint8m1_t test___riscv_vxor_mu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint8m2_t test___riscv_vxor_mu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint8m4_t test___riscv_vxor_mu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint8m8_t test___riscv_vxor_mu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint16mf4_t test___riscv_vxor_mu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint16mf2_t test___riscv_vxor_mu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint16m1_t test___riscv_vxor_mu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint16m2_t test___riscv_vxor_mu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint16m4_t test___riscv_vxor_mu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint16m8_t test___riscv_vxor_mu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint32mf2_t test___riscv_vxor_mu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint32m1_t test___riscv_vxor_mu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint32m2_t test___riscv_vxor_mu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint32m4_t test___riscv_vxor_mu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint32m8_t test___riscv_vxor_mu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint64m1_t test___riscv_vxor_mu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint64m2_t test___riscv_vxor_mu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint64m4_t test___riscv_vxor_mu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint64m8_t test___riscv_vxor_mu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vxor_mu(mask,merge,op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vxor_vx_rv32-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vxor_vx_rv32-1.C
new file mode 100644
index 00000000000..f0c3914300e
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vxor_vx_rv32-1.C
@@ -0,0 +1,572 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vxor(vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,vl);
+}
+
+
+vint8mf4_t test___riscv_vxor(vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,vl);
+}
+
+
+vint8mf2_t test___riscv_vxor(vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,vl);
+}
+
+
+vint8m1_t test___riscv_vxor(vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,vl);
+}
+
+
+vint8m2_t test___riscv_vxor(vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,vl);
+}
+
+
+vint8m4_t test___riscv_vxor(vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,vl);
+}
+
+
+vint8m8_t test___riscv_vxor(vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,vl);
+}
+
+
+vint16mf4_t test___riscv_vxor(vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,vl);
+}
+
+
+vint16mf2_t test___riscv_vxor(vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,vl);
+}
+
+
+vint16m1_t test___riscv_vxor(vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,vl);
+}
+
+
+vint16m2_t test___riscv_vxor(vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,vl);
+}
+
+
+vint16m4_t test___riscv_vxor(vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,vl);
+}
+
+
+vint16m8_t test___riscv_vxor(vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,vl);
+}
+
+
+vint32mf2_t test___riscv_vxor(vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,vl);
+}
+
+
+vint32m1_t test___riscv_vxor(vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,vl);
+}
+
+
+vint32m2_t test___riscv_vxor(vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,vl);
+}
+
+
+vint32m4_t test___riscv_vxor(vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,vl);
+}
+
+
+vint32m8_t test___riscv_vxor(vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,vl);
+}
+
+
+vint64m1_t test___riscv_vxor(vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,vl);
+}
+
+
+vint64m2_t test___riscv_vxor(vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,vl);
+}
+
+
+vint64m4_t test___riscv_vxor(vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,vl);
+}
+
+
+vint64m8_t test___riscv_vxor(vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,vl);
+}
+
+
+vuint8mf8_t test___riscv_vxor(vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,vl);
+}
+
+
+vuint8mf4_t test___riscv_vxor(vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,vl);
+}
+
+
+vuint8mf2_t test___riscv_vxor(vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,vl);
+}
+
+
+vuint8m1_t test___riscv_vxor(vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,vl);
+}
+
+
+vuint8m2_t test___riscv_vxor(vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,vl);
+}
+
+
+vuint8m4_t test___riscv_vxor(vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,vl);
+}
+
+
+vuint8m8_t test___riscv_vxor(vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,vl);
+}
+
+
+vuint16mf4_t test___riscv_vxor(vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,vl);
+}
+
+
+vuint16mf2_t test___riscv_vxor(vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,vl);
+}
+
+
+vuint16m1_t test___riscv_vxor(vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,vl);
+}
+
+
+vuint16m2_t test___riscv_vxor(vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,vl);
+}
+
+
+vuint16m4_t test___riscv_vxor(vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,vl);
+}
+
+
+vuint16m8_t test___riscv_vxor(vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,vl);
+}
+
+
+vuint32mf2_t test___riscv_vxor(vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,vl);
+}
+
+
+vuint32m1_t test___riscv_vxor(vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,vl);
+}
+
+
+vuint32m2_t test___riscv_vxor(vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,vl);
+}
+
+
+vuint32m4_t test___riscv_vxor(vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,vl);
+}
+
+
+vuint32m8_t test___riscv_vxor(vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,vl);
+}
+
+
+vuint64m1_t test___riscv_vxor(vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,vl);
+}
+
+
+vuint64m2_t test___riscv_vxor(vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,vl);
+}
+
+
+vuint64m4_t test___riscv_vxor(vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,vl);
+}
+
+
+vuint64m8_t test___riscv_vxor(vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,vl);
+}
+
+
+vint8mf8_t test___riscv_vxor(vbool64_t mask,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,vl);
+}
+
+
+vint8mf4_t test___riscv_vxor(vbool32_t mask,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,vl);
+}
+
+
+vint8mf2_t test___riscv_vxor(vbool16_t mask,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,vl);
+}
+
+
+vint8m1_t test___riscv_vxor(vbool8_t mask,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,vl);
+}
+
+
+vint8m2_t test___riscv_vxor(vbool4_t mask,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,vl);
+}
+
+
+vint8m4_t test___riscv_vxor(vbool2_t mask,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,vl);
+}
+
+
+vint8m8_t test___riscv_vxor(vbool1_t mask,vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,vl);
+}
+
+
+vint16mf4_t test___riscv_vxor(vbool64_t mask,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,vl);
+}
+
+
+vint16mf2_t test___riscv_vxor(vbool32_t mask,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,vl);
+}
+
+
+vint16m1_t test___riscv_vxor(vbool16_t mask,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,vl);
+}
+
+
+vint16m2_t test___riscv_vxor(vbool8_t mask,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,vl);
+}
+
+
+vint16m4_t test___riscv_vxor(vbool4_t mask,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,vl);
+}
+
+
+vint16m8_t test___riscv_vxor(vbool2_t mask,vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,vl);
+}
+
+
+vint32mf2_t test___riscv_vxor(vbool64_t mask,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,vl);
+}
+
+
+vint32m1_t test___riscv_vxor(vbool32_t mask,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,vl);
+}
+
+
+vint32m2_t test___riscv_vxor(vbool16_t mask,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,vl);
+}
+
+
+vint32m4_t test___riscv_vxor(vbool8_t mask,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,vl);
+}
+
+
+vint32m8_t test___riscv_vxor(vbool4_t mask,vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,vl);
+}
+
+
+vint64m1_t test___riscv_vxor(vbool64_t mask,vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,vl);
+}
+
+
+vint64m2_t test___riscv_vxor(vbool32_t mask,vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,vl);
+}
+
+
+vint64m4_t test___riscv_vxor(vbool16_t mask,vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,vl);
+}
+
+
+vint64m8_t test___riscv_vxor(vbool8_t mask,vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,vl);
+}
+
+
+vuint8mf8_t test___riscv_vxor(vbool64_t mask,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,vl);
+}
+
+
+vuint8mf4_t test___riscv_vxor(vbool32_t mask,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,vl);
+}
+
+
+vuint8mf2_t test___riscv_vxor(vbool16_t mask,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,vl);
+}
+
+
+vuint8m1_t test___riscv_vxor(vbool8_t mask,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,vl);
+}
+
+
+vuint8m2_t test___riscv_vxor(vbool4_t mask,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,vl);
+}
+
+
+vuint8m4_t test___riscv_vxor(vbool2_t mask,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,vl);
+}
+
+
+vuint8m8_t test___riscv_vxor(vbool1_t mask,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,vl);
+}
+
+
+vuint16mf4_t test___riscv_vxor(vbool64_t mask,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,vl);
+}
+
+
+vuint16mf2_t test___riscv_vxor(vbool32_t mask,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,vl);
+}
+
+
+vuint16m1_t test___riscv_vxor(vbool16_t mask,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,vl);
+}
+
+
+vuint16m2_t test___riscv_vxor(vbool8_t mask,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,vl);
+}
+
+
+vuint16m4_t test___riscv_vxor(vbool4_t mask,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,vl);
+}
+
+
+vuint16m8_t test___riscv_vxor(vbool2_t mask,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,vl);
+}
+
+
+vuint32mf2_t test___riscv_vxor(vbool64_t mask,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,vl);
+}
+
+
+vuint32m1_t test___riscv_vxor(vbool32_t mask,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,vl);
+}
+
+
+vuint32m2_t test___riscv_vxor(vbool16_t mask,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,vl);
+}
+
+
+vuint32m4_t test___riscv_vxor(vbool8_t mask,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,vl);
+}
+
+
+vuint32m8_t test___riscv_vxor(vbool4_t mask,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,vl);
+}
+
+
+vuint64m1_t test___riscv_vxor(vbool64_t mask,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,vl);
+}
+
+
+vuint64m2_t test___riscv_vxor(vbool32_t mask,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,vl);
+}
+
+
+vuint64m4_t test___riscv_vxor(vbool16_t mask,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,vl);
+}
+
+
+vuint64m8_t test___riscv_vxor(vbool8_t mask,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 8 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 8 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vxor_vx_rv32-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vxor_vx_rv32-2.C
new file mode 100644
index 00000000000..11f8c28f910
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vxor_vx_rv32-2.C
@@ -0,0 +1,572 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vxor(vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,31);
+}
+
+
+vint8mf4_t test___riscv_vxor(vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,31);
+}
+
+
+vint8mf2_t test___riscv_vxor(vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,31);
+}
+
+
+vint8m1_t test___riscv_vxor(vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,31);
+}
+
+
+vint8m2_t test___riscv_vxor(vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,31);
+}
+
+
+vint8m4_t test___riscv_vxor(vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,31);
+}
+
+
+vint8m8_t test___riscv_vxor(vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,31);
+}
+
+
+vint16mf4_t test___riscv_vxor(vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,31);
+}
+
+
+vint16mf2_t test___riscv_vxor(vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,31);
+}
+
+
+vint16m1_t test___riscv_vxor(vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,31);
+}
+
+
+vint16m2_t test___riscv_vxor(vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,31);
+}
+
+
+vint16m4_t test___riscv_vxor(vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,31);
+}
+
+
+vint16m8_t test___riscv_vxor(vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,31);
+}
+
+
+vint32mf2_t test___riscv_vxor(vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,31);
+}
+
+
+vint32m1_t test___riscv_vxor(vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,31);
+}
+
+
+vint32m2_t test___riscv_vxor(vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,31);
+}
+
+
+vint32m4_t test___riscv_vxor(vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,31);
+}
+
+
+vint32m8_t test___riscv_vxor(vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,31);
+}
+
+
+vint64m1_t test___riscv_vxor(vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,31);
+}
+
+
+vint64m2_t test___riscv_vxor(vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,31);
+}
+
+
+vint64m4_t test___riscv_vxor(vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,31);
+}
+
+
+vint64m8_t test___riscv_vxor(vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,31);
+}
+
+
+vuint8mf8_t test___riscv_vxor(vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,31);
+}
+
+
+vuint8mf4_t test___riscv_vxor(vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,31);
+}
+
+
+vuint8mf2_t test___riscv_vxor(vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,31);
+}
+
+
+vuint8m1_t test___riscv_vxor(vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,31);
+}
+
+
+vuint8m2_t test___riscv_vxor(vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,31);
+}
+
+
+vuint8m4_t test___riscv_vxor(vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,31);
+}
+
+
+vuint8m8_t test___riscv_vxor(vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,31);
+}
+
+
+vuint16mf4_t test___riscv_vxor(vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,31);
+}
+
+
+vuint16mf2_t test___riscv_vxor(vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,31);
+}
+
+
+vuint16m1_t test___riscv_vxor(vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,31);
+}
+
+
+vuint16m2_t test___riscv_vxor(vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,31);
+}
+
+
+vuint16m4_t test___riscv_vxor(vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,31);
+}
+
+
+vuint16m8_t test___riscv_vxor(vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,31);
+}
+
+
+vuint32mf2_t test___riscv_vxor(vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,31);
+}
+
+
+vuint32m1_t test___riscv_vxor(vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,31);
+}
+
+
+vuint32m2_t test___riscv_vxor(vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,31);
+}
+
+
+vuint32m4_t test___riscv_vxor(vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,31);
+}
+
+
+vuint32m8_t test___riscv_vxor(vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,31);
+}
+
+
+vuint64m1_t test___riscv_vxor(vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,31);
+}
+
+
+vuint64m2_t test___riscv_vxor(vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,31);
+}
+
+
+vuint64m4_t test___riscv_vxor(vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,31);
+}
+
+
+vuint64m8_t test___riscv_vxor(vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,31);
+}
+
+
+vint8mf8_t test___riscv_vxor(vbool64_t mask,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,31);
+}
+
+
+vint8mf4_t test___riscv_vxor(vbool32_t mask,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,31);
+}
+
+
+vint8mf2_t test___riscv_vxor(vbool16_t mask,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,31);
+}
+
+
+vint8m1_t test___riscv_vxor(vbool8_t mask,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,31);
+}
+
+
+vint8m2_t test___riscv_vxor(vbool4_t mask,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,31);
+}
+
+
+vint8m4_t test___riscv_vxor(vbool2_t mask,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,31);
+}
+
+
+vint8m8_t test___riscv_vxor(vbool1_t mask,vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,31);
+}
+
+
+vint16mf4_t test___riscv_vxor(vbool64_t mask,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,31);
+}
+
+
+vint16mf2_t test___riscv_vxor(vbool32_t mask,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,31);
+}
+
+
+vint16m1_t test___riscv_vxor(vbool16_t mask,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,31);
+}
+
+
+vint16m2_t test___riscv_vxor(vbool8_t mask,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,31);
+}
+
+
+vint16m4_t test___riscv_vxor(vbool4_t mask,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,31);
+}
+
+
+vint16m8_t test___riscv_vxor(vbool2_t mask,vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,31);
+}
+
+
+vint32mf2_t test___riscv_vxor(vbool64_t mask,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,31);
+}
+
+
+vint32m1_t test___riscv_vxor(vbool32_t mask,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,31);
+}
+
+
+vint32m2_t test___riscv_vxor(vbool16_t mask,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,31);
+}
+
+
+vint32m4_t test___riscv_vxor(vbool8_t mask,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,31);
+}
+
+
+vint32m8_t test___riscv_vxor(vbool4_t mask,vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,31);
+}
+
+
+vint64m1_t test___riscv_vxor(vbool64_t mask,vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,31);
+}
+
+
+vint64m2_t test___riscv_vxor(vbool32_t mask,vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,31);
+}
+
+
+vint64m4_t test___riscv_vxor(vbool16_t mask,vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,31);
+}
+
+
+vint64m8_t test___riscv_vxor(vbool8_t mask,vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,31);
+}
+
+
+vuint8mf8_t test___riscv_vxor(vbool64_t mask,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,31);
+}
+
+
+vuint8mf4_t test___riscv_vxor(vbool32_t mask,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,31);
+}
+
+
+vuint8mf2_t test___riscv_vxor(vbool16_t mask,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,31);
+}
+
+
+vuint8m1_t test___riscv_vxor(vbool8_t mask,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,31);
+}
+
+
+vuint8m2_t test___riscv_vxor(vbool4_t mask,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,31);
+}
+
+
+vuint8m4_t test___riscv_vxor(vbool2_t mask,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,31);
+}
+
+
+vuint8m8_t test___riscv_vxor(vbool1_t mask,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,31);
+}
+
+
+vuint16mf4_t test___riscv_vxor(vbool64_t mask,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,31);
+}
+
+
+vuint16mf2_t test___riscv_vxor(vbool32_t mask,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,31);
+}
+
+
+vuint16m1_t test___riscv_vxor(vbool16_t mask,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,31);
+}
+
+
+vuint16m2_t test___riscv_vxor(vbool8_t mask,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,31);
+}
+
+
+vuint16m4_t test___riscv_vxor(vbool4_t mask,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,31);
+}
+
+
+vuint16m8_t test___riscv_vxor(vbool2_t mask,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,31);
+}
+
+
+vuint32mf2_t test___riscv_vxor(vbool64_t mask,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,31);
+}
+
+
+vuint32m1_t test___riscv_vxor(vbool32_t mask,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,31);
+}
+
+
+vuint32m2_t test___riscv_vxor(vbool16_t mask,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,31);
+}
+
+
+vuint32m4_t test___riscv_vxor(vbool8_t mask,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,31);
+}
+
+
+vuint32m8_t test___riscv_vxor(vbool4_t mask,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,31);
+}
+
+
+vuint64m1_t test___riscv_vxor(vbool64_t mask,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,31);
+}
+
+
+vuint64m2_t test___riscv_vxor(vbool32_t mask,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,31);
+}
+
+
+vuint64m4_t test___riscv_vxor(vbool16_t mask,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,31);
+}
+
+
+vuint64m8_t test___riscv_vxor(vbool8_t mask,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 8 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 8 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vxor_vx_rv32-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vxor_vx_rv32-3.C
new file mode 100644
index 00000000000..c9911f6b1da
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vxor_vx_rv32-3.C
@@ -0,0 +1,572 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vxor(vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,32);
+}
+
+
+vint8mf4_t test___riscv_vxor(vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,32);
+}
+
+
+vint8mf2_t test___riscv_vxor(vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,32);
+}
+
+
+vint8m1_t test___riscv_vxor(vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,32);
+}
+
+
+vint8m2_t test___riscv_vxor(vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,32);
+}
+
+
+vint8m4_t test___riscv_vxor(vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,32);
+}
+
+
+vint8m8_t test___riscv_vxor(vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,32);
+}
+
+
+vint16mf4_t test___riscv_vxor(vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,32);
+}
+
+
+vint16mf2_t test___riscv_vxor(vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,32);
+}
+
+
+vint16m1_t test___riscv_vxor(vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,32);
+}
+
+
+vint16m2_t test___riscv_vxor(vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,32);
+}
+
+
+vint16m4_t test___riscv_vxor(vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,32);
+}
+
+
+vint16m8_t test___riscv_vxor(vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,32);
+}
+
+
+vint32mf2_t test___riscv_vxor(vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,32);
+}
+
+
+vint32m1_t test___riscv_vxor(vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,32);
+}
+
+
+vint32m2_t test___riscv_vxor(vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,32);
+}
+
+
+vint32m4_t test___riscv_vxor(vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,32);
+}
+
+
+vint32m8_t test___riscv_vxor(vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,32);
+}
+
+
+vint64m1_t test___riscv_vxor(vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,32);
+}
+
+
+vint64m2_t test___riscv_vxor(vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,32);
+}
+
+
+vint64m4_t test___riscv_vxor(vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,32);
+}
+
+
+vint64m8_t test___riscv_vxor(vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,32);
+}
+
+
+vuint8mf8_t test___riscv_vxor(vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,32);
+}
+
+
+vuint8mf4_t test___riscv_vxor(vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,32);
+}
+
+
+vuint8mf2_t test___riscv_vxor(vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,32);
+}
+
+
+vuint8m1_t test___riscv_vxor(vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,32);
+}
+
+
+vuint8m2_t test___riscv_vxor(vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,32);
+}
+
+
+vuint8m4_t test___riscv_vxor(vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,32);
+}
+
+
+vuint8m8_t test___riscv_vxor(vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,32);
+}
+
+
+vuint16mf4_t test___riscv_vxor(vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,32);
+}
+
+
+vuint16mf2_t test___riscv_vxor(vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,32);
+}
+
+
+vuint16m1_t test___riscv_vxor(vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,32);
+}
+
+
+vuint16m2_t test___riscv_vxor(vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,32);
+}
+
+
+vuint16m4_t test___riscv_vxor(vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,32);
+}
+
+
+vuint16m8_t test___riscv_vxor(vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,32);
+}
+
+
+vuint32mf2_t test___riscv_vxor(vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,32);
+}
+
+
+vuint32m1_t test___riscv_vxor(vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,32);
+}
+
+
+vuint32m2_t test___riscv_vxor(vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,32);
+}
+
+
+vuint32m4_t test___riscv_vxor(vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,32);
+}
+
+
+vuint32m8_t test___riscv_vxor(vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,32);
+}
+
+
+vuint64m1_t test___riscv_vxor(vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,32);
+}
+
+
+vuint64m2_t test___riscv_vxor(vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,32);
+}
+
+
+vuint64m4_t test___riscv_vxor(vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,32);
+}
+
+
+vuint64m8_t test___riscv_vxor(vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,32);
+}
+
+
+vint8mf8_t test___riscv_vxor(vbool64_t mask,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,32);
+}
+
+
+vint8mf4_t test___riscv_vxor(vbool32_t mask,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,32);
+}
+
+
+vint8mf2_t test___riscv_vxor(vbool16_t mask,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,32);
+}
+
+
+vint8m1_t test___riscv_vxor(vbool8_t mask,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,32);
+}
+
+
+vint8m2_t test___riscv_vxor(vbool4_t mask,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,32);
+}
+
+
+vint8m4_t test___riscv_vxor(vbool2_t mask,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,32);
+}
+
+
+vint8m8_t test___riscv_vxor(vbool1_t mask,vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,32);
+}
+
+
+vint16mf4_t test___riscv_vxor(vbool64_t mask,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,32);
+}
+
+
+vint16mf2_t test___riscv_vxor(vbool32_t mask,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,32);
+}
+
+
+vint16m1_t test___riscv_vxor(vbool16_t mask,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,32);
+}
+
+
+vint16m2_t test___riscv_vxor(vbool8_t mask,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,32);
+}
+
+
+vint16m4_t test___riscv_vxor(vbool4_t mask,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,32);
+}
+
+
+vint16m8_t test___riscv_vxor(vbool2_t mask,vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,32);
+}
+
+
+vint32mf2_t test___riscv_vxor(vbool64_t mask,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,32);
+}
+
+
+vint32m1_t test___riscv_vxor(vbool32_t mask,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,32);
+}
+
+
+vint32m2_t test___riscv_vxor(vbool16_t mask,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,32);
+}
+
+
+vint32m4_t test___riscv_vxor(vbool8_t mask,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,32);
+}
+
+
+vint32m8_t test___riscv_vxor(vbool4_t mask,vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,32);
+}
+
+
+vint64m1_t test___riscv_vxor(vbool64_t mask,vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,32);
+}
+
+
+vint64m2_t test___riscv_vxor(vbool32_t mask,vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,32);
+}
+
+
+vint64m4_t test___riscv_vxor(vbool16_t mask,vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,32);
+}
+
+
+vint64m8_t test___riscv_vxor(vbool8_t mask,vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,32);
+}
+
+
+vuint8mf8_t test___riscv_vxor(vbool64_t mask,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,32);
+}
+
+
+vuint8mf4_t test___riscv_vxor(vbool32_t mask,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,32);
+}
+
+
+vuint8mf2_t test___riscv_vxor(vbool16_t mask,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,32);
+}
+
+
+vuint8m1_t test___riscv_vxor(vbool8_t mask,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,32);
+}
+
+
+vuint8m2_t test___riscv_vxor(vbool4_t mask,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,32);
+}
+
+
+vuint8m4_t test___riscv_vxor(vbool2_t mask,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,32);
+}
+
+
+vuint8m8_t test___riscv_vxor(vbool1_t mask,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,32);
+}
+
+
+vuint16mf4_t test___riscv_vxor(vbool64_t mask,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,32);
+}
+
+
+vuint16mf2_t test___riscv_vxor(vbool32_t mask,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,32);
+}
+
+
+vuint16m1_t test___riscv_vxor(vbool16_t mask,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,32);
+}
+
+
+vuint16m2_t test___riscv_vxor(vbool8_t mask,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,32);
+}
+
+
+vuint16m4_t test___riscv_vxor(vbool4_t mask,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,32);
+}
+
+
+vuint16m8_t test___riscv_vxor(vbool2_t mask,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,32);
+}
+
+
+vuint32mf2_t test___riscv_vxor(vbool64_t mask,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,32);
+}
+
+
+vuint32m1_t test___riscv_vxor(vbool32_t mask,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,32);
+}
+
+
+vuint32m2_t test___riscv_vxor(vbool16_t mask,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,32);
+}
+
+
+vuint32m4_t test___riscv_vxor(vbool8_t mask,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,32);
+}
+
+
+vuint32m8_t test___riscv_vxor(vbool4_t mask,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,32);
+}
+
+
+vuint64m1_t test___riscv_vxor(vbool64_t mask,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,32);
+}
+
+
+vuint64m2_t test___riscv_vxor(vbool32_t mask,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,32);
+}
+
+
+vuint64m4_t test___riscv_vxor(vbool16_t mask,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,32);
+}
+
+
+vuint64m8_t test___riscv_vxor(vbool8_t mask,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 8 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 8 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vxor_vx_rv64-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vxor_vx_rv64-1.C
new file mode 100644
index 00000000000..e5e985d0ab5
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vxor_vx_rv64-1.C
@@ -0,0 +1,578 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vxor(vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,vl);
+}
+
+
+vint8mf4_t test___riscv_vxor(vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,vl);
+}
+
+
+vint8mf2_t test___riscv_vxor(vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,vl);
+}
+
+
+vint8m1_t test___riscv_vxor(vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,vl);
+}
+
+
+vint8m2_t test___riscv_vxor(vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,vl);
+}
+
+
+vint8m4_t test___riscv_vxor(vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,vl);
+}
+
+
+vint8m8_t test___riscv_vxor(vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,vl);
+}
+
+
+vint16mf4_t test___riscv_vxor(vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,vl);
+}
+
+
+vint16mf2_t test___riscv_vxor(vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,vl);
+}
+
+
+vint16m1_t test___riscv_vxor(vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,vl);
+}
+
+
+vint16m2_t test___riscv_vxor(vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,vl);
+}
+
+
+vint16m4_t test___riscv_vxor(vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,vl);
+}
+
+
+vint16m8_t test___riscv_vxor(vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,vl);
+}
+
+
+vint32mf2_t test___riscv_vxor(vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,vl);
+}
+
+
+vint32m1_t test___riscv_vxor(vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,vl);
+}
+
+
+vint32m2_t test___riscv_vxor(vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,vl);
+}
+
+
+vint32m4_t test___riscv_vxor(vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,vl);
+}
+
+
+vint32m8_t test___riscv_vxor(vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,vl);
+}
+
+
+vint64m1_t test___riscv_vxor(vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,vl);
+}
+
+
+vint64m2_t test___riscv_vxor(vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,vl);
+}
+
+
+vint64m4_t test___riscv_vxor(vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,vl);
+}
+
+
+vint64m8_t test___riscv_vxor(vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,vl);
+}
+
+
+vuint8mf8_t test___riscv_vxor(vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,vl);
+}
+
+
+vuint8mf4_t test___riscv_vxor(vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,vl);
+}
+
+
+vuint8mf2_t test___riscv_vxor(vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,vl);
+}
+
+
+vuint8m1_t test___riscv_vxor(vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,vl);
+}
+
+
+vuint8m2_t test___riscv_vxor(vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,vl);
+}
+
+
+vuint8m4_t test___riscv_vxor(vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,vl);
+}
+
+
+vuint8m8_t test___riscv_vxor(vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,vl);
+}
+
+
+vuint16mf4_t test___riscv_vxor(vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,vl);
+}
+
+
+vuint16mf2_t test___riscv_vxor(vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,vl);
+}
+
+
+vuint16m1_t test___riscv_vxor(vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,vl);
+}
+
+
+vuint16m2_t test___riscv_vxor(vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,vl);
+}
+
+
+vuint16m4_t test___riscv_vxor(vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,vl);
+}
+
+
+vuint16m8_t test___riscv_vxor(vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,vl);
+}
+
+
+vuint32mf2_t test___riscv_vxor(vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,vl);
+}
+
+
+vuint32m1_t test___riscv_vxor(vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,vl);
+}
+
+
+vuint32m2_t test___riscv_vxor(vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,vl);
+}
+
+
+vuint32m4_t test___riscv_vxor(vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,vl);
+}
+
+
+vuint32m8_t test___riscv_vxor(vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,vl);
+}
+
+
+vuint64m1_t test___riscv_vxor(vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,vl);
+}
+
+
+vuint64m2_t test___riscv_vxor(vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,vl);
+}
+
+
+vuint64m4_t test___riscv_vxor(vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,vl);
+}
+
+
+vuint64m8_t test___riscv_vxor(vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,vl);
+}
+
+
+vint8mf8_t test___riscv_vxor(vbool64_t mask,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,vl);
+}
+
+
+vint8mf4_t test___riscv_vxor(vbool32_t mask,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,vl);
+}
+
+
+vint8mf2_t test___riscv_vxor(vbool16_t mask,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,vl);
+}
+
+
+vint8m1_t test___riscv_vxor(vbool8_t mask,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,vl);
+}
+
+
+vint8m2_t test___riscv_vxor(vbool4_t mask,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,vl);
+}
+
+
+vint8m4_t test___riscv_vxor(vbool2_t mask,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,vl);
+}
+
+
+vint8m8_t test___riscv_vxor(vbool1_t mask,vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,vl);
+}
+
+
+vint16mf4_t test___riscv_vxor(vbool64_t mask,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,vl);
+}
+
+
+vint16mf2_t test___riscv_vxor(vbool32_t mask,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,vl);
+}
+
+
+vint16m1_t test___riscv_vxor(vbool16_t mask,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,vl);
+}
+
+
+vint16m2_t test___riscv_vxor(vbool8_t mask,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,vl);
+}
+
+
+vint16m4_t test___riscv_vxor(vbool4_t mask,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,vl);
+}
+
+
+vint16m8_t test___riscv_vxor(vbool2_t mask,vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,vl);
+}
+
+
+vint32mf2_t test___riscv_vxor(vbool64_t mask,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,vl);
+}
+
+
+vint32m1_t test___riscv_vxor(vbool32_t mask,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,vl);
+}
+
+
+vint32m2_t test___riscv_vxor(vbool16_t mask,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,vl);
+}
+
+
+vint32m4_t test___riscv_vxor(vbool8_t mask,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,vl);
+}
+
+
+vint32m8_t test___riscv_vxor(vbool4_t mask,vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,vl);
+}
+
+
+vint64m1_t test___riscv_vxor(vbool64_t mask,vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,vl);
+}
+
+
+vint64m2_t test___riscv_vxor(vbool32_t mask,vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,vl);
+}
+
+
+vint64m4_t test___riscv_vxor(vbool16_t mask,vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,vl);
+}
+
+
+vint64m8_t test___riscv_vxor(vbool8_t mask,vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,vl);
+}
+
+
+vuint8mf8_t test___riscv_vxor(vbool64_t mask,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,vl);
+}
+
+
+vuint8mf4_t test___riscv_vxor(vbool32_t mask,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,vl);
+}
+
+
+vuint8mf2_t test___riscv_vxor(vbool16_t mask,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,vl);
+}
+
+
+vuint8m1_t test___riscv_vxor(vbool8_t mask,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,vl);
+}
+
+
+vuint8m2_t test___riscv_vxor(vbool4_t mask,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,vl);
+}
+
+
+vuint8m4_t test___riscv_vxor(vbool2_t mask,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,vl);
+}
+
+
+vuint8m8_t test___riscv_vxor(vbool1_t mask,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,vl);
+}
+
+
+vuint16mf4_t test___riscv_vxor(vbool64_t mask,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,vl);
+}
+
+
+vuint16mf2_t test___riscv_vxor(vbool32_t mask,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,vl);
+}
+
+
+vuint16m1_t test___riscv_vxor(vbool16_t mask,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,vl);
+}
+
+
+vuint16m2_t test___riscv_vxor(vbool8_t mask,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,vl);
+}
+
+
+vuint16m4_t test___riscv_vxor(vbool4_t mask,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,vl);
+}
+
+
+vuint16m8_t test___riscv_vxor(vbool2_t mask,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,vl);
+}
+
+
+vuint32mf2_t test___riscv_vxor(vbool64_t mask,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,vl);
+}
+
+
+vuint32m1_t test___riscv_vxor(vbool32_t mask,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,vl);
+}
+
+
+vuint32m2_t test___riscv_vxor(vbool16_t mask,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,vl);
+}
+
+
+vuint32m4_t test___riscv_vxor(vbool8_t mask,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,vl);
+}
+
+
+vuint32m8_t test___riscv_vxor(vbool4_t mask,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,vl);
+}
+
+
+vuint64m1_t test___riscv_vxor(vbool64_t mask,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,vl);
+}
+
+
+vuint64m2_t test___riscv_vxor(vbool32_t mask,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,vl);
+}
+
+
+vuint64m4_t test___riscv_vxor(vbool16_t mask,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,vl);
+}
+
+
+vuint64m8_t test___riscv_vxor(vbool8_t mask,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vxor_vx_rv64-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vxor_vx_rv64-2.C
new file mode 100644
index 00000000000..720b3bd729e
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vxor_vx_rv64-2.C
@@ -0,0 +1,578 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vxor(vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,31);
+}
+
+
+vint8mf4_t test___riscv_vxor(vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,31);
+}
+
+
+vint8mf2_t test___riscv_vxor(vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,31);
+}
+
+
+vint8m1_t test___riscv_vxor(vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,31);
+}
+
+
+vint8m2_t test___riscv_vxor(vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,31);
+}
+
+
+vint8m4_t test___riscv_vxor(vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,31);
+}
+
+
+vint8m8_t test___riscv_vxor(vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,31);
+}
+
+
+vint16mf4_t test___riscv_vxor(vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,31);
+}
+
+
+vint16mf2_t test___riscv_vxor(vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,31);
+}
+
+
+vint16m1_t test___riscv_vxor(vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,31);
+}
+
+
+vint16m2_t test___riscv_vxor(vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,31);
+}
+
+
+vint16m4_t test___riscv_vxor(vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,31);
+}
+
+
+vint16m8_t test___riscv_vxor(vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,31);
+}
+
+
+vint32mf2_t test___riscv_vxor(vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,31);
+}
+
+
+vint32m1_t test___riscv_vxor(vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,31);
+}
+
+
+vint32m2_t test___riscv_vxor(vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,31);
+}
+
+
+vint32m4_t test___riscv_vxor(vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,31);
+}
+
+
+vint32m8_t test___riscv_vxor(vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,31);
+}
+
+
+vint64m1_t test___riscv_vxor(vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,31);
+}
+
+
+vint64m2_t test___riscv_vxor(vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,31);
+}
+
+
+vint64m4_t test___riscv_vxor(vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,31);
+}
+
+
+vint64m8_t test___riscv_vxor(vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,31);
+}
+
+
+vuint8mf8_t test___riscv_vxor(vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,31);
+}
+
+
+vuint8mf4_t test___riscv_vxor(vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,31);
+}
+
+
+vuint8mf2_t test___riscv_vxor(vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,31);
+}
+
+
+vuint8m1_t test___riscv_vxor(vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,31);
+}
+
+
+vuint8m2_t test___riscv_vxor(vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,31);
+}
+
+
+vuint8m4_t test___riscv_vxor(vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,31);
+}
+
+
+vuint8m8_t test___riscv_vxor(vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,31);
+}
+
+
+vuint16mf4_t test___riscv_vxor(vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,31);
+}
+
+
+vuint16mf2_t test___riscv_vxor(vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,31);
+}
+
+
+vuint16m1_t test___riscv_vxor(vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,31);
+}
+
+
+vuint16m2_t test___riscv_vxor(vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,31);
+}
+
+
+vuint16m4_t test___riscv_vxor(vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,31);
+}
+
+
+vuint16m8_t test___riscv_vxor(vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,31);
+}
+
+
+vuint32mf2_t test___riscv_vxor(vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,31);
+}
+
+
+vuint32m1_t test___riscv_vxor(vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,31);
+}
+
+
+vuint32m2_t test___riscv_vxor(vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,31);
+}
+
+
+vuint32m4_t test___riscv_vxor(vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,31);
+}
+
+
+vuint32m8_t test___riscv_vxor(vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,31);
+}
+
+
+vuint64m1_t test___riscv_vxor(vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,31);
+}
+
+
+vuint64m2_t test___riscv_vxor(vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,31);
+}
+
+
+vuint64m4_t test___riscv_vxor(vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,31);
+}
+
+
+vuint64m8_t test___riscv_vxor(vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,31);
+}
+
+
+vint8mf8_t test___riscv_vxor(vbool64_t mask,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,31);
+}
+
+
+vint8mf4_t test___riscv_vxor(vbool32_t mask,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,31);
+}
+
+
+vint8mf2_t test___riscv_vxor(vbool16_t mask,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,31);
+}
+
+
+vint8m1_t test___riscv_vxor(vbool8_t mask,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,31);
+}
+
+
+vint8m2_t test___riscv_vxor(vbool4_t mask,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,31);
+}
+
+
+vint8m4_t test___riscv_vxor(vbool2_t mask,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,31);
+}
+
+
+vint8m8_t test___riscv_vxor(vbool1_t mask,vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,31);
+}
+
+
+vint16mf4_t test___riscv_vxor(vbool64_t mask,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,31);
+}
+
+
+vint16mf2_t test___riscv_vxor(vbool32_t mask,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,31);
+}
+
+
+vint16m1_t test___riscv_vxor(vbool16_t mask,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,31);
+}
+
+
+vint16m2_t test___riscv_vxor(vbool8_t mask,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,31);
+}
+
+
+vint16m4_t test___riscv_vxor(vbool4_t mask,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,31);
+}
+
+
+vint16m8_t test___riscv_vxor(vbool2_t mask,vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,31);
+}
+
+
+vint32mf2_t test___riscv_vxor(vbool64_t mask,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,31);
+}
+
+
+vint32m1_t test___riscv_vxor(vbool32_t mask,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,31);
+}
+
+
+vint32m2_t test___riscv_vxor(vbool16_t mask,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,31);
+}
+
+
+vint32m4_t test___riscv_vxor(vbool8_t mask,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,31);
+}
+
+
+vint32m8_t test___riscv_vxor(vbool4_t mask,vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,31);
+}
+
+
+vint64m1_t test___riscv_vxor(vbool64_t mask,vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,31);
+}
+
+
+vint64m2_t test___riscv_vxor(vbool32_t mask,vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,31);
+}
+
+
+vint64m4_t test___riscv_vxor(vbool16_t mask,vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,31);
+}
+
+
+vint64m8_t test___riscv_vxor(vbool8_t mask,vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,31);
+}
+
+
+vuint8mf8_t test___riscv_vxor(vbool64_t mask,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,31);
+}
+
+
+vuint8mf4_t test___riscv_vxor(vbool32_t mask,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,31);
+}
+
+
+vuint8mf2_t test___riscv_vxor(vbool16_t mask,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,31);
+}
+
+
+vuint8m1_t test___riscv_vxor(vbool8_t mask,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,31);
+}
+
+
+vuint8m2_t test___riscv_vxor(vbool4_t mask,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,31);
+}
+
+
+vuint8m4_t test___riscv_vxor(vbool2_t mask,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,31);
+}
+
+
+vuint8m8_t test___riscv_vxor(vbool1_t mask,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,31);
+}
+
+
+vuint16mf4_t test___riscv_vxor(vbool64_t mask,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,31);
+}
+
+
+vuint16mf2_t test___riscv_vxor(vbool32_t mask,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,31);
+}
+
+
+vuint16m1_t test___riscv_vxor(vbool16_t mask,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,31);
+}
+
+
+vuint16m2_t test___riscv_vxor(vbool8_t mask,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,31);
+}
+
+
+vuint16m4_t test___riscv_vxor(vbool4_t mask,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,31);
+}
+
+
+vuint16m8_t test___riscv_vxor(vbool2_t mask,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,31);
+}
+
+
+vuint32mf2_t test___riscv_vxor(vbool64_t mask,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,31);
+}
+
+
+vuint32m1_t test___riscv_vxor(vbool32_t mask,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,31);
+}
+
+
+vuint32m2_t test___riscv_vxor(vbool16_t mask,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,31);
+}
+
+
+vuint32m4_t test___riscv_vxor(vbool8_t mask,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,31);
+}
+
+
+vuint32m8_t test___riscv_vxor(vbool4_t mask,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,31);
+}
+
+
+vuint64m1_t test___riscv_vxor(vbool64_t mask,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,31);
+}
+
+
+vuint64m2_t test___riscv_vxor(vbool32_t mask,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,31);
+}
+
+
+vuint64m4_t test___riscv_vxor(vbool16_t mask,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,31);
+}
+
+
+vuint64m8_t test___riscv_vxor(vbool8_t mask,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vxor_vx_rv64-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vxor_vx_rv64-3.C
new file mode 100644
index 00000000000..600654d0e64
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vxor_vx_rv64-3.C
@@ -0,0 +1,578 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vxor(vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,32);
+}
+
+
+vint8mf4_t test___riscv_vxor(vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,32);
+}
+
+
+vint8mf2_t test___riscv_vxor(vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,32);
+}
+
+
+vint8m1_t test___riscv_vxor(vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,32);
+}
+
+
+vint8m2_t test___riscv_vxor(vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,32);
+}
+
+
+vint8m4_t test___riscv_vxor(vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,32);
+}
+
+
+vint8m8_t test___riscv_vxor(vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,32);
+}
+
+
+vint16mf4_t test___riscv_vxor(vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,32);
+}
+
+
+vint16mf2_t test___riscv_vxor(vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,32);
+}
+
+
+vint16m1_t test___riscv_vxor(vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,32);
+}
+
+
+vint16m2_t test___riscv_vxor(vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,32);
+}
+
+
+vint16m4_t test___riscv_vxor(vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,32);
+}
+
+
+vint16m8_t test___riscv_vxor(vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,32);
+}
+
+
+vint32mf2_t test___riscv_vxor(vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,32);
+}
+
+
+vint32m1_t test___riscv_vxor(vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,32);
+}
+
+
+vint32m2_t test___riscv_vxor(vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,32);
+}
+
+
+vint32m4_t test___riscv_vxor(vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,32);
+}
+
+
+vint32m8_t test___riscv_vxor(vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,32);
+}
+
+
+vint64m1_t test___riscv_vxor(vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,32);
+}
+
+
+vint64m2_t test___riscv_vxor(vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,32);
+}
+
+
+vint64m4_t test___riscv_vxor(vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,32);
+}
+
+
+vint64m8_t test___riscv_vxor(vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,32);
+}
+
+
+vuint8mf8_t test___riscv_vxor(vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,32);
+}
+
+
+vuint8mf4_t test___riscv_vxor(vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,32);
+}
+
+
+vuint8mf2_t test___riscv_vxor(vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,32);
+}
+
+
+vuint8m1_t test___riscv_vxor(vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,32);
+}
+
+
+vuint8m2_t test___riscv_vxor(vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,32);
+}
+
+
+vuint8m4_t test___riscv_vxor(vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,32);
+}
+
+
+vuint8m8_t test___riscv_vxor(vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,32);
+}
+
+
+vuint16mf4_t test___riscv_vxor(vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,32);
+}
+
+
+vuint16mf2_t test___riscv_vxor(vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,32);
+}
+
+
+vuint16m1_t test___riscv_vxor(vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,32);
+}
+
+
+vuint16m2_t test___riscv_vxor(vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,32);
+}
+
+
+vuint16m4_t test___riscv_vxor(vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,32);
+}
+
+
+vuint16m8_t test___riscv_vxor(vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,32);
+}
+
+
+vuint32mf2_t test___riscv_vxor(vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,32);
+}
+
+
+vuint32m1_t test___riscv_vxor(vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,32);
+}
+
+
+vuint32m2_t test___riscv_vxor(vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,32);
+}
+
+
+vuint32m4_t test___riscv_vxor(vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,32);
+}
+
+
+vuint32m8_t test___riscv_vxor(vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,32);
+}
+
+
+vuint64m1_t test___riscv_vxor(vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,32);
+}
+
+
+vuint64m2_t test___riscv_vxor(vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,32);
+}
+
+
+vuint64m4_t test___riscv_vxor(vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,32);
+}
+
+
+vuint64m8_t test___riscv_vxor(vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vxor(op1,op2,32);
+}
+
+
+vint8mf8_t test___riscv_vxor(vbool64_t mask,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,32);
+}
+
+
+vint8mf4_t test___riscv_vxor(vbool32_t mask,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,32);
+}
+
+
+vint8mf2_t test___riscv_vxor(vbool16_t mask,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,32);
+}
+
+
+vint8m1_t test___riscv_vxor(vbool8_t mask,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,32);
+}
+
+
+vint8m2_t test___riscv_vxor(vbool4_t mask,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,32);
+}
+
+
+vint8m4_t test___riscv_vxor(vbool2_t mask,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,32);
+}
+
+
+vint8m8_t test___riscv_vxor(vbool1_t mask,vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,32);
+}
+
+
+vint16mf4_t test___riscv_vxor(vbool64_t mask,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,32);
+}
+
+
+vint16mf2_t test___riscv_vxor(vbool32_t mask,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,32);
+}
+
+
+vint16m1_t test___riscv_vxor(vbool16_t mask,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,32);
+}
+
+
+vint16m2_t test___riscv_vxor(vbool8_t mask,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,32);
+}
+
+
+vint16m4_t test___riscv_vxor(vbool4_t mask,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,32);
+}
+
+
+vint16m8_t test___riscv_vxor(vbool2_t mask,vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,32);
+}
+
+
+vint32mf2_t test___riscv_vxor(vbool64_t mask,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,32);
+}
+
+
+vint32m1_t test___riscv_vxor(vbool32_t mask,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,32);
+}
+
+
+vint32m2_t test___riscv_vxor(vbool16_t mask,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,32);
+}
+
+
+vint32m4_t test___riscv_vxor(vbool8_t mask,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,32);
+}
+
+
+vint32m8_t test___riscv_vxor(vbool4_t mask,vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,32);
+}
+
+
+vint64m1_t test___riscv_vxor(vbool64_t mask,vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,32);
+}
+
+
+vint64m2_t test___riscv_vxor(vbool32_t mask,vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,32);
+}
+
+
+vint64m4_t test___riscv_vxor(vbool16_t mask,vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,32);
+}
+
+
+vint64m8_t test___riscv_vxor(vbool8_t mask,vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,32);
+}
+
+
+vuint8mf8_t test___riscv_vxor(vbool64_t mask,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,32);
+}
+
+
+vuint8mf4_t test___riscv_vxor(vbool32_t mask,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,32);
+}
+
+
+vuint8mf2_t test___riscv_vxor(vbool16_t mask,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,32);
+}
+
+
+vuint8m1_t test___riscv_vxor(vbool8_t mask,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,32);
+}
+
+
+vuint8m2_t test___riscv_vxor(vbool4_t mask,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,32);
+}
+
+
+vuint8m4_t test___riscv_vxor(vbool2_t mask,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,32);
+}
+
+
+vuint8m8_t test___riscv_vxor(vbool1_t mask,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,32);
+}
+
+
+vuint16mf4_t test___riscv_vxor(vbool64_t mask,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,32);
+}
+
+
+vuint16mf2_t test___riscv_vxor(vbool32_t mask,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,32);
+}
+
+
+vuint16m1_t test___riscv_vxor(vbool16_t mask,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,32);
+}
+
+
+vuint16m2_t test___riscv_vxor(vbool8_t mask,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,32);
+}
+
+
+vuint16m4_t test___riscv_vxor(vbool4_t mask,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,32);
+}
+
+
+vuint16m8_t test___riscv_vxor(vbool2_t mask,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,32);
+}
+
+
+vuint32mf2_t test___riscv_vxor(vbool64_t mask,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,32);
+}
+
+
+vuint32m1_t test___riscv_vxor(vbool32_t mask,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,32);
+}
+
+
+vuint32m2_t test___riscv_vxor(vbool16_t mask,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,32);
+}
+
+
+vuint32m4_t test___riscv_vxor(vbool8_t mask,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,32);
+}
+
+
+vuint32m8_t test___riscv_vxor(vbool4_t mask,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,32);
+}
+
+
+vuint64m1_t test___riscv_vxor(vbool64_t mask,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,32);
+}
+
+
+vuint64m2_t test___riscv_vxor(vbool32_t mask,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,32);
+}
+
+
+vuint64m4_t test___riscv_vxor(vbool16_t mask,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,32);
+}
+
+
+vuint64m8_t test___riscv_vxor(vbool8_t mask,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vxor(mask,op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vxor_vx_tu_rv32-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vxor_vx_tu_rv32-1.C
new file mode 100644
index 00000000000..e8eb726443a
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vxor_vx_tu_rv32-1.C
@@ -0,0 +1,289 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vxor_tu(vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,vl);
+}
+
+
+vint8mf4_t test___riscv_vxor_tu(vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,vl);
+}
+
+
+vint8mf2_t test___riscv_vxor_tu(vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,vl);
+}
+
+
+vint8m1_t test___riscv_vxor_tu(vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,vl);
+}
+
+
+vint8m2_t test___riscv_vxor_tu(vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,vl);
+}
+
+
+vint8m4_t test___riscv_vxor_tu(vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,vl);
+}
+
+
+vint8m8_t test___riscv_vxor_tu(vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,vl);
+}
+
+
+vint16mf4_t test___riscv_vxor_tu(vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,vl);
+}
+
+
+vint16mf2_t test___riscv_vxor_tu(vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,vl);
+}
+
+
+vint16m1_t test___riscv_vxor_tu(vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,vl);
+}
+
+
+vint16m2_t test___riscv_vxor_tu(vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,vl);
+}
+
+
+vint16m4_t test___riscv_vxor_tu(vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,vl);
+}
+
+
+vint16m8_t test___riscv_vxor_tu(vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,vl);
+}
+
+
+vint32mf2_t test___riscv_vxor_tu(vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,vl);
+}
+
+
+vint32m1_t test___riscv_vxor_tu(vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,vl);
+}
+
+
+vint32m2_t test___riscv_vxor_tu(vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,vl);
+}
+
+
+vint32m4_t test___riscv_vxor_tu(vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,vl);
+}
+
+
+vint32m8_t test___riscv_vxor_tu(vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,vl);
+}
+
+
+vint64m1_t test___riscv_vxor_tu(vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,vl);
+}
+
+
+vint64m2_t test___riscv_vxor_tu(vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,vl);
+}
+
+
+vint64m4_t test___riscv_vxor_tu(vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,vl);
+}
+
+
+vint64m8_t test___riscv_vxor_tu(vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,vl);
+}
+
+
+vuint8mf8_t test___riscv_vxor_tu(vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,vl);
+}
+
+
+vuint8mf4_t test___riscv_vxor_tu(vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,vl);
+}
+
+
+vuint8mf2_t test___riscv_vxor_tu(vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,vl);
+}
+
+
+vuint8m1_t test___riscv_vxor_tu(vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,vl);
+}
+
+
+vuint8m2_t test___riscv_vxor_tu(vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,vl);
+}
+
+
+vuint8m4_t test___riscv_vxor_tu(vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,vl);
+}
+
+
+vuint8m8_t test___riscv_vxor_tu(vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,vl);
+}
+
+
+vuint16mf4_t test___riscv_vxor_tu(vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,vl);
+}
+
+
+vuint16mf2_t test___riscv_vxor_tu(vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,vl);
+}
+
+
+vuint16m1_t test___riscv_vxor_tu(vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,vl);
+}
+
+
+vuint16m2_t test___riscv_vxor_tu(vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,vl);
+}
+
+
+vuint16m4_t test___riscv_vxor_tu(vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,vl);
+}
+
+
+vuint16m8_t test___riscv_vxor_tu(vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,vl);
+}
+
+
+vuint32mf2_t test___riscv_vxor_tu(vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,vl);
+}
+
+
+vuint32m1_t test___riscv_vxor_tu(vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,vl);
+}
+
+
+vuint32m2_t test___riscv_vxor_tu(vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,vl);
+}
+
+
+vuint32m4_t test___riscv_vxor_tu(vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,vl);
+}
+
+
+vuint32m8_t test___riscv_vxor_tu(vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,vl);
+}
+
+
+vuint64m1_t test___riscv_vxor_tu(vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,vl);
+}
+
+
+vuint64m2_t test___riscv_vxor_tu(vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,vl);
+}
+
+
+vuint64m4_t test___riscv_vxor_tu(vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,vl);
+}
+
+
+vuint64m8_t test___riscv_vxor_tu(vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 8 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vxor_vx_tu_rv32-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vxor_vx_tu_rv32-2.C
new file mode 100644
index 00000000000..f11cd7d0afd
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vxor_vx_tu_rv32-2.C
@@ -0,0 +1,289 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vxor_tu(vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,31);
+}
+
+
+vint8mf4_t test___riscv_vxor_tu(vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,31);
+}
+
+
+vint8mf2_t test___riscv_vxor_tu(vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,31);
+}
+
+
+vint8m1_t test___riscv_vxor_tu(vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,31);
+}
+
+
+vint8m2_t test___riscv_vxor_tu(vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,31);
+}
+
+
+vint8m4_t test___riscv_vxor_tu(vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,31);
+}
+
+
+vint8m8_t test___riscv_vxor_tu(vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,31);
+}
+
+
+vint16mf4_t test___riscv_vxor_tu(vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,31);
+}
+
+
+vint16mf2_t test___riscv_vxor_tu(vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,31);
+}
+
+
+vint16m1_t test___riscv_vxor_tu(vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,31);
+}
+
+
+vint16m2_t test___riscv_vxor_tu(vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,31);
+}
+
+
+vint16m4_t test___riscv_vxor_tu(vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,31);
+}
+
+
+vint16m8_t test___riscv_vxor_tu(vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,31);
+}
+
+
+vint32mf2_t test___riscv_vxor_tu(vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,31);
+}
+
+
+vint32m1_t test___riscv_vxor_tu(vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,31);
+}
+
+
+vint32m2_t test___riscv_vxor_tu(vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,31);
+}
+
+
+vint32m4_t test___riscv_vxor_tu(vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,31);
+}
+
+
+vint32m8_t test___riscv_vxor_tu(vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,31);
+}
+
+
+vint64m1_t test___riscv_vxor_tu(vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,31);
+}
+
+
+vint64m2_t test___riscv_vxor_tu(vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,31);
+}
+
+
+vint64m4_t test___riscv_vxor_tu(vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,31);
+}
+
+
+vint64m8_t test___riscv_vxor_tu(vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,31);
+}
+
+
+vuint8mf8_t test___riscv_vxor_tu(vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,31);
+}
+
+
+vuint8mf4_t test___riscv_vxor_tu(vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,31);
+}
+
+
+vuint8mf2_t test___riscv_vxor_tu(vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,31);
+}
+
+
+vuint8m1_t test___riscv_vxor_tu(vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,31);
+}
+
+
+vuint8m2_t test___riscv_vxor_tu(vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,31);
+}
+
+
+vuint8m4_t test___riscv_vxor_tu(vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,31);
+}
+
+
+vuint8m8_t test___riscv_vxor_tu(vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,31);
+}
+
+
+vuint16mf4_t test___riscv_vxor_tu(vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,31);
+}
+
+
+vuint16mf2_t test___riscv_vxor_tu(vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,31);
+}
+
+
+vuint16m1_t test___riscv_vxor_tu(vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,31);
+}
+
+
+vuint16m2_t test___riscv_vxor_tu(vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,31);
+}
+
+
+vuint16m4_t test___riscv_vxor_tu(vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,31);
+}
+
+
+vuint16m8_t test___riscv_vxor_tu(vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,31);
+}
+
+
+vuint32mf2_t test___riscv_vxor_tu(vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,31);
+}
+
+
+vuint32m1_t test___riscv_vxor_tu(vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,31);
+}
+
+
+vuint32m2_t test___riscv_vxor_tu(vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,31);
+}
+
+
+vuint32m4_t test___riscv_vxor_tu(vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,31);
+}
+
+
+vuint32m8_t test___riscv_vxor_tu(vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,31);
+}
+
+
+vuint64m1_t test___riscv_vxor_tu(vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,31);
+}
+
+
+vuint64m2_t test___riscv_vxor_tu(vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,31);
+}
+
+
+vuint64m4_t test___riscv_vxor_tu(vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,31);
+}
+
+
+vuint64m8_t test___riscv_vxor_tu(vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 8 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vxor_vx_tu_rv32-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vxor_vx_tu_rv32-3.C
new file mode 100644
index 00000000000..fbaf3722162
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vxor_vx_tu_rv32-3.C
@@ -0,0 +1,289 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vxor_tu(vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,32);
+}
+
+
+vint8mf4_t test___riscv_vxor_tu(vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,32);
+}
+
+
+vint8mf2_t test___riscv_vxor_tu(vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,32);
+}
+
+
+vint8m1_t test___riscv_vxor_tu(vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,32);
+}
+
+
+vint8m2_t test___riscv_vxor_tu(vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,32);
+}
+
+
+vint8m4_t test___riscv_vxor_tu(vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,32);
+}
+
+
+vint8m8_t test___riscv_vxor_tu(vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,32);
+}
+
+
+vint16mf4_t test___riscv_vxor_tu(vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,32);
+}
+
+
+vint16mf2_t test___riscv_vxor_tu(vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,32);
+}
+
+
+vint16m1_t test___riscv_vxor_tu(vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,32);
+}
+
+
+vint16m2_t test___riscv_vxor_tu(vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,32);
+}
+
+
+vint16m4_t test___riscv_vxor_tu(vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,32);
+}
+
+
+vint16m8_t test___riscv_vxor_tu(vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,32);
+}
+
+
+vint32mf2_t test___riscv_vxor_tu(vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,32);
+}
+
+
+vint32m1_t test___riscv_vxor_tu(vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,32);
+}
+
+
+vint32m2_t test___riscv_vxor_tu(vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,32);
+}
+
+
+vint32m4_t test___riscv_vxor_tu(vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,32);
+}
+
+
+vint32m8_t test___riscv_vxor_tu(vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,32);
+}
+
+
+vint64m1_t test___riscv_vxor_tu(vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,32);
+}
+
+
+vint64m2_t test___riscv_vxor_tu(vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,32);
+}
+
+
+vint64m4_t test___riscv_vxor_tu(vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,32);
+}
+
+
+vint64m8_t test___riscv_vxor_tu(vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,32);
+}
+
+
+vuint8mf8_t test___riscv_vxor_tu(vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,32);
+}
+
+
+vuint8mf4_t test___riscv_vxor_tu(vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,32);
+}
+
+
+vuint8mf2_t test___riscv_vxor_tu(vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,32);
+}
+
+
+vuint8m1_t test___riscv_vxor_tu(vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,32);
+}
+
+
+vuint8m2_t test___riscv_vxor_tu(vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,32);
+}
+
+
+vuint8m4_t test___riscv_vxor_tu(vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,32);
+}
+
+
+vuint8m8_t test___riscv_vxor_tu(vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,32);
+}
+
+
+vuint16mf4_t test___riscv_vxor_tu(vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,32);
+}
+
+
+vuint16mf2_t test___riscv_vxor_tu(vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,32);
+}
+
+
+vuint16m1_t test___riscv_vxor_tu(vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,32);
+}
+
+
+vuint16m2_t test___riscv_vxor_tu(vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,32);
+}
+
+
+vuint16m4_t test___riscv_vxor_tu(vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,32);
+}
+
+
+vuint16m8_t test___riscv_vxor_tu(vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,32);
+}
+
+
+vuint32mf2_t test___riscv_vxor_tu(vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,32);
+}
+
+
+vuint32m1_t test___riscv_vxor_tu(vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,32);
+}
+
+
+vuint32m2_t test___riscv_vxor_tu(vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,32);
+}
+
+
+vuint32m4_t test___riscv_vxor_tu(vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,32);
+}
+
+
+vuint32m8_t test___riscv_vxor_tu(vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,32);
+}
+
+
+vuint64m1_t test___riscv_vxor_tu(vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,32);
+}
+
+
+vuint64m2_t test___riscv_vxor_tu(vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,32);
+}
+
+
+vuint64m4_t test___riscv_vxor_tu(vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,32);
+}
+
+
+vuint64m8_t test___riscv_vxor_tu(vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 8 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vxor_vx_tu_rv64-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vxor_vx_tu_rv64-1.C
new file mode 100644
index 00000000000..779f5563a76
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vxor_vx_tu_rv64-1.C
@@ -0,0 +1,292 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vxor_tu(vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,vl);
+}
+
+
+vint8mf4_t test___riscv_vxor_tu(vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,vl);
+}
+
+
+vint8mf2_t test___riscv_vxor_tu(vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,vl);
+}
+
+
+vint8m1_t test___riscv_vxor_tu(vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,vl);
+}
+
+
+vint8m2_t test___riscv_vxor_tu(vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,vl);
+}
+
+
+vint8m4_t test___riscv_vxor_tu(vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,vl);
+}
+
+
+vint8m8_t test___riscv_vxor_tu(vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,vl);
+}
+
+
+vint16mf4_t test___riscv_vxor_tu(vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,vl);
+}
+
+
+vint16mf2_t test___riscv_vxor_tu(vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,vl);
+}
+
+
+vint16m1_t test___riscv_vxor_tu(vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,vl);
+}
+
+
+vint16m2_t test___riscv_vxor_tu(vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,vl);
+}
+
+
+vint16m4_t test___riscv_vxor_tu(vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,vl);
+}
+
+
+vint16m8_t test___riscv_vxor_tu(vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,vl);
+}
+
+
+vint32mf2_t test___riscv_vxor_tu(vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,vl);
+}
+
+
+vint32m1_t test___riscv_vxor_tu(vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,vl);
+}
+
+
+vint32m2_t test___riscv_vxor_tu(vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,vl);
+}
+
+
+vint32m4_t test___riscv_vxor_tu(vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,vl);
+}
+
+
+vint32m8_t test___riscv_vxor_tu(vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,vl);
+}
+
+
+vint64m1_t test___riscv_vxor_tu(vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,vl);
+}
+
+
+vint64m2_t test___riscv_vxor_tu(vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,vl);
+}
+
+
+vint64m4_t test___riscv_vxor_tu(vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,vl);
+}
+
+
+vint64m8_t test___riscv_vxor_tu(vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,vl);
+}
+
+
+vuint8mf8_t test___riscv_vxor_tu(vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,vl);
+}
+
+
+vuint8mf4_t test___riscv_vxor_tu(vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,vl);
+}
+
+
+vuint8mf2_t test___riscv_vxor_tu(vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,vl);
+}
+
+
+vuint8m1_t test___riscv_vxor_tu(vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,vl);
+}
+
+
+vuint8m2_t test___riscv_vxor_tu(vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,vl);
+}
+
+
+vuint8m4_t test___riscv_vxor_tu(vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,vl);
+}
+
+
+vuint8m8_t test___riscv_vxor_tu(vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,vl);
+}
+
+
+vuint16mf4_t test___riscv_vxor_tu(vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,vl);
+}
+
+
+vuint16mf2_t test___riscv_vxor_tu(vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,vl);
+}
+
+
+vuint16m1_t test___riscv_vxor_tu(vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,vl);
+}
+
+
+vuint16m2_t test___riscv_vxor_tu(vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,vl);
+}
+
+
+vuint16m4_t test___riscv_vxor_tu(vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,vl);
+}
+
+
+vuint16m8_t test___riscv_vxor_tu(vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,vl);
+}
+
+
+vuint32mf2_t test___riscv_vxor_tu(vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,vl);
+}
+
+
+vuint32m1_t test___riscv_vxor_tu(vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,vl);
+}
+
+
+vuint32m2_t test___riscv_vxor_tu(vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,vl);
+}
+
+
+vuint32m4_t test___riscv_vxor_tu(vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,vl);
+}
+
+
+vuint32m8_t test___riscv_vxor_tu(vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,vl);
+}
+
+
+vuint64m1_t test___riscv_vxor_tu(vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,vl);
+}
+
+
+vuint64m2_t test___riscv_vxor_tu(vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,vl);
+}
+
+
+vuint64m4_t test___riscv_vxor_tu(vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,vl);
+}
+
+
+vuint64m8_t test___riscv_vxor_tu(vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vxor_vx_tu_rv64-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vxor_vx_tu_rv64-2.C
new file mode 100644
index 00000000000..9378d6bcbf0
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vxor_vx_tu_rv64-2.C
@@ -0,0 +1,292 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vxor_tu(vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,31);
+}
+
+
+vint8mf4_t test___riscv_vxor_tu(vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,31);
+}
+
+
+vint8mf2_t test___riscv_vxor_tu(vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,31);
+}
+
+
+vint8m1_t test___riscv_vxor_tu(vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,31);
+}
+
+
+vint8m2_t test___riscv_vxor_tu(vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,31);
+}
+
+
+vint8m4_t test___riscv_vxor_tu(vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,31);
+}
+
+
+vint8m8_t test___riscv_vxor_tu(vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,31);
+}
+
+
+vint16mf4_t test___riscv_vxor_tu(vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,31);
+}
+
+
+vint16mf2_t test___riscv_vxor_tu(vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,31);
+}
+
+
+vint16m1_t test___riscv_vxor_tu(vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,31);
+}
+
+
+vint16m2_t test___riscv_vxor_tu(vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,31);
+}
+
+
+vint16m4_t test___riscv_vxor_tu(vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,31);
+}
+
+
+vint16m8_t test___riscv_vxor_tu(vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,31);
+}
+
+
+vint32mf2_t test___riscv_vxor_tu(vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,31);
+}
+
+
+vint32m1_t test___riscv_vxor_tu(vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,31);
+}
+
+
+vint32m2_t test___riscv_vxor_tu(vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,31);
+}
+
+
+vint32m4_t test___riscv_vxor_tu(vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,31);
+}
+
+
+vint32m8_t test___riscv_vxor_tu(vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,31);
+}
+
+
+vint64m1_t test___riscv_vxor_tu(vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,31);
+}
+
+
+vint64m2_t test___riscv_vxor_tu(vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,31);
+}
+
+
+vint64m4_t test___riscv_vxor_tu(vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,31);
+}
+
+
+vint64m8_t test___riscv_vxor_tu(vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,31);
+}
+
+
+vuint8mf8_t test___riscv_vxor_tu(vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,31);
+}
+
+
+vuint8mf4_t test___riscv_vxor_tu(vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,31);
+}
+
+
+vuint8mf2_t test___riscv_vxor_tu(vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,31);
+}
+
+
+vuint8m1_t test___riscv_vxor_tu(vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,31);
+}
+
+
+vuint8m2_t test___riscv_vxor_tu(vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,31);
+}
+
+
+vuint8m4_t test___riscv_vxor_tu(vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,31);
+}
+
+
+vuint8m8_t test___riscv_vxor_tu(vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,31);
+}
+
+
+vuint16mf4_t test___riscv_vxor_tu(vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,31);
+}
+
+
+vuint16mf2_t test___riscv_vxor_tu(vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,31);
+}
+
+
+vuint16m1_t test___riscv_vxor_tu(vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,31);
+}
+
+
+vuint16m2_t test___riscv_vxor_tu(vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,31);
+}
+
+
+vuint16m4_t test___riscv_vxor_tu(vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,31);
+}
+
+
+vuint16m8_t test___riscv_vxor_tu(vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,31);
+}
+
+
+vuint32mf2_t test___riscv_vxor_tu(vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,31);
+}
+
+
+vuint32m1_t test___riscv_vxor_tu(vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,31);
+}
+
+
+vuint32m2_t test___riscv_vxor_tu(vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,31);
+}
+
+
+vuint32m4_t test___riscv_vxor_tu(vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,31);
+}
+
+
+vuint32m8_t test___riscv_vxor_tu(vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,31);
+}
+
+
+vuint64m1_t test___riscv_vxor_tu(vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,31);
+}
+
+
+vuint64m2_t test___riscv_vxor_tu(vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,31);
+}
+
+
+vuint64m4_t test___riscv_vxor_tu(vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,31);
+}
+
+
+vuint64m8_t test___riscv_vxor_tu(vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vxor_vx_tu_rv64-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vxor_vx_tu_rv64-3.C
new file mode 100644
index 00000000000..b079cfbad6a
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vxor_vx_tu_rv64-3.C
@@ -0,0 +1,292 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vxor_tu(vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,32);
+}
+
+
+vint8mf4_t test___riscv_vxor_tu(vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,32);
+}
+
+
+vint8mf2_t test___riscv_vxor_tu(vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,32);
+}
+
+
+vint8m1_t test___riscv_vxor_tu(vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,32);
+}
+
+
+vint8m2_t test___riscv_vxor_tu(vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,32);
+}
+
+
+vint8m4_t test___riscv_vxor_tu(vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,32);
+}
+
+
+vint8m8_t test___riscv_vxor_tu(vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,32);
+}
+
+
+vint16mf4_t test___riscv_vxor_tu(vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,32);
+}
+
+
+vint16mf2_t test___riscv_vxor_tu(vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,32);
+}
+
+
+vint16m1_t test___riscv_vxor_tu(vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,32);
+}
+
+
+vint16m2_t test___riscv_vxor_tu(vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,32);
+}
+
+
+vint16m4_t test___riscv_vxor_tu(vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,32);
+}
+
+
+vint16m8_t test___riscv_vxor_tu(vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,32);
+}
+
+
+vint32mf2_t test___riscv_vxor_tu(vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,32);
+}
+
+
+vint32m1_t test___riscv_vxor_tu(vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,32);
+}
+
+
+vint32m2_t test___riscv_vxor_tu(vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,32);
+}
+
+
+vint32m4_t test___riscv_vxor_tu(vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,32);
+}
+
+
+vint32m8_t test___riscv_vxor_tu(vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,32);
+}
+
+
+vint64m1_t test___riscv_vxor_tu(vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,32);
+}
+
+
+vint64m2_t test___riscv_vxor_tu(vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,32);
+}
+
+
+vint64m4_t test___riscv_vxor_tu(vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,32);
+}
+
+
+vint64m8_t test___riscv_vxor_tu(vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,32);
+}
+
+
+vuint8mf8_t test___riscv_vxor_tu(vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,32);
+}
+
+
+vuint8mf4_t test___riscv_vxor_tu(vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,32);
+}
+
+
+vuint8mf2_t test___riscv_vxor_tu(vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,32);
+}
+
+
+vuint8m1_t test___riscv_vxor_tu(vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,32);
+}
+
+
+vuint8m2_t test___riscv_vxor_tu(vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,32);
+}
+
+
+vuint8m4_t test___riscv_vxor_tu(vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,32);
+}
+
+
+vuint8m8_t test___riscv_vxor_tu(vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,32);
+}
+
+
+vuint16mf4_t test___riscv_vxor_tu(vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,32);
+}
+
+
+vuint16mf2_t test___riscv_vxor_tu(vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,32);
+}
+
+
+vuint16m1_t test___riscv_vxor_tu(vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,32);
+}
+
+
+vuint16m2_t test___riscv_vxor_tu(vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,32);
+}
+
+
+vuint16m4_t test___riscv_vxor_tu(vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,32);
+}
+
+
+vuint16m8_t test___riscv_vxor_tu(vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,32);
+}
+
+
+vuint32mf2_t test___riscv_vxor_tu(vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,32);
+}
+
+
+vuint32m1_t test___riscv_vxor_tu(vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,32);
+}
+
+
+vuint32m2_t test___riscv_vxor_tu(vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,32);
+}
+
+
+vuint32m4_t test___riscv_vxor_tu(vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,32);
+}
+
+
+vuint32m8_t test___riscv_vxor_tu(vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,32);
+}
+
+
+vuint64m1_t test___riscv_vxor_tu(vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,32);
+}
+
+
+vuint64m2_t test___riscv_vxor_tu(vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,32);
+}
+
+
+vuint64m4_t test___riscv_vxor_tu(vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,32);
+}
+
+
+vuint64m8_t test___riscv_vxor_tu(vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vxor_tu(merge,op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vxor_vx_tum_rv32-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vxor_vx_tum_rv32-1.C
new file mode 100644
index 00000000000..fe1a7b86001
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vxor_vx_tum_rv32-1.C
@@ -0,0 +1,289 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vxor_tum(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint8mf4_t test___riscv_vxor_tum(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint8mf2_t test___riscv_vxor_tum(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint8m1_t test___riscv_vxor_tum(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint8m2_t test___riscv_vxor_tum(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint8m4_t test___riscv_vxor_tum(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint8m8_t test___riscv_vxor_tum(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint16mf4_t test___riscv_vxor_tum(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint16mf2_t test___riscv_vxor_tum(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint16m1_t test___riscv_vxor_tum(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint16m2_t test___riscv_vxor_tum(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint16m4_t test___riscv_vxor_tum(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint16m8_t test___riscv_vxor_tum(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint32mf2_t test___riscv_vxor_tum(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint32m1_t test___riscv_vxor_tum(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint32m2_t test___riscv_vxor_tum(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint32m4_t test___riscv_vxor_tum(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint32m8_t test___riscv_vxor_tum(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint64m1_t test___riscv_vxor_tum(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint64m2_t test___riscv_vxor_tum(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint64m4_t test___riscv_vxor_tum(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint64m8_t test___riscv_vxor_tum(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint8mf8_t test___riscv_vxor_tum(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint8mf4_t test___riscv_vxor_tum(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint8mf2_t test___riscv_vxor_tum(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint8m1_t test___riscv_vxor_tum(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint8m2_t test___riscv_vxor_tum(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint8m4_t test___riscv_vxor_tum(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint8m8_t test___riscv_vxor_tum(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint16mf4_t test___riscv_vxor_tum(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint16mf2_t test___riscv_vxor_tum(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m1_t test___riscv_vxor_tum(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m2_t test___riscv_vxor_tum(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m4_t test___riscv_vxor_tum(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m8_t test___riscv_vxor_tum(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint32mf2_t test___riscv_vxor_tum(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m1_t test___riscv_vxor_tum(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m2_t test___riscv_vxor_tum(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m4_t test___riscv_vxor_tum(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m8_t test___riscv_vxor_tum(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m1_t test___riscv_vxor_tum(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m2_t test___riscv_vxor_tum(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m4_t test___riscv_vxor_tum(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m8_t test___riscv_vxor_tum(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 8 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vxor_vx_tum_rv32-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vxor_vx_tum_rv32-2.C
new file mode 100644
index 00000000000..cd2d88468ef
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vxor_vx_tum_rv32-2.C
@@ -0,0 +1,289 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vxor_tum(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,31);
+}
+
+
+vint8mf4_t test___riscv_vxor_tum(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,31);
+}
+
+
+vint8mf2_t test___riscv_vxor_tum(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,31);
+}
+
+
+vint8m1_t test___riscv_vxor_tum(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,31);
+}
+
+
+vint8m2_t test___riscv_vxor_tum(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,31);
+}
+
+
+vint8m4_t test___riscv_vxor_tum(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,31);
+}
+
+
+vint8m8_t test___riscv_vxor_tum(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,31);
+}
+
+
+vint16mf4_t test___riscv_vxor_tum(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,31);
+}
+
+
+vint16mf2_t test___riscv_vxor_tum(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,31);
+}
+
+
+vint16m1_t test___riscv_vxor_tum(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,31);
+}
+
+
+vint16m2_t test___riscv_vxor_tum(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,31);
+}
+
+
+vint16m4_t test___riscv_vxor_tum(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,31);
+}
+
+
+vint16m8_t test___riscv_vxor_tum(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,31);
+}
+
+
+vint32mf2_t test___riscv_vxor_tum(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,31);
+}
+
+
+vint32m1_t test___riscv_vxor_tum(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,31);
+}
+
+
+vint32m2_t test___riscv_vxor_tum(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,31);
+}
+
+
+vint32m4_t test___riscv_vxor_tum(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,31);
+}
+
+
+vint32m8_t test___riscv_vxor_tum(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,31);
+}
+
+
+vint64m1_t test___riscv_vxor_tum(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,31);
+}
+
+
+vint64m2_t test___riscv_vxor_tum(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,31);
+}
+
+
+vint64m4_t test___riscv_vxor_tum(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,31);
+}
+
+
+vint64m8_t test___riscv_vxor_tum(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint8mf8_t test___riscv_vxor_tum(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint8mf4_t test___riscv_vxor_tum(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint8mf2_t test___riscv_vxor_tum(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint8m1_t test___riscv_vxor_tum(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint8m2_t test___riscv_vxor_tum(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint8m4_t test___riscv_vxor_tum(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint8m8_t test___riscv_vxor_tum(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint16mf4_t test___riscv_vxor_tum(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint16mf2_t test___riscv_vxor_tum(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint16m1_t test___riscv_vxor_tum(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint16m2_t test___riscv_vxor_tum(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint16m4_t test___riscv_vxor_tum(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint16m8_t test___riscv_vxor_tum(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint32mf2_t test___riscv_vxor_tum(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint32m1_t test___riscv_vxor_tum(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint32m2_t test___riscv_vxor_tum(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint32m4_t test___riscv_vxor_tum(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint32m8_t test___riscv_vxor_tum(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint64m1_t test___riscv_vxor_tum(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint64m2_t test___riscv_vxor_tum(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint64m4_t test___riscv_vxor_tum(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint64m8_t test___riscv_vxor_tum(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 8 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vxor_vx_tum_rv32-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vxor_vx_tum_rv32-3.C
new file mode 100644
index 00000000000..ee880f7e4e2
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vxor_vx_tum_rv32-3.C
@@ -0,0 +1,289 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vxor_tum(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,32);
+}
+
+
+vint8mf4_t test___riscv_vxor_tum(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,32);
+}
+
+
+vint8mf2_t test___riscv_vxor_tum(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,32);
+}
+
+
+vint8m1_t test___riscv_vxor_tum(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,32);
+}
+
+
+vint8m2_t test___riscv_vxor_tum(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,32);
+}
+
+
+vint8m4_t test___riscv_vxor_tum(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,32);
+}
+
+
+vint8m8_t test___riscv_vxor_tum(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,32);
+}
+
+
+vint16mf4_t test___riscv_vxor_tum(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,32);
+}
+
+
+vint16mf2_t test___riscv_vxor_tum(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,32);
+}
+
+
+vint16m1_t test___riscv_vxor_tum(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,32);
+}
+
+
+vint16m2_t test___riscv_vxor_tum(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,32);
+}
+
+
+vint16m4_t test___riscv_vxor_tum(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,32);
+}
+
+
+vint16m8_t test___riscv_vxor_tum(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,32);
+}
+
+
+vint32mf2_t test___riscv_vxor_tum(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,32);
+}
+
+
+vint32m1_t test___riscv_vxor_tum(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,32);
+}
+
+
+vint32m2_t test___riscv_vxor_tum(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,32);
+}
+
+
+vint32m4_t test___riscv_vxor_tum(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,32);
+}
+
+
+vint32m8_t test___riscv_vxor_tum(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,32);
+}
+
+
+vint64m1_t test___riscv_vxor_tum(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,32);
+}
+
+
+vint64m2_t test___riscv_vxor_tum(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,32);
+}
+
+
+vint64m4_t test___riscv_vxor_tum(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,32);
+}
+
+
+vint64m8_t test___riscv_vxor_tum(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint8mf8_t test___riscv_vxor_tum(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint8mf4_t test___riscv_vxor_tum(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint8mf2_t test___riscv_vxor_tum(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint8m1_t test___riscv_vxor_tum(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint8m2_t test___riscv_vxor_tum(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint8m4_t test___riscv_vxor_tum(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint8m8_t test___riscv_vxor_tum(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint16mf4_t test___riscv_vxor_tum(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint16mf2_t test___riscv_vxor_tum(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint16m1_t test___riscv_vxor_tum(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint16m2_t test___riscv_vxor_tum(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint16m4_t test___riscv_vxor_tum(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint16m8_t test___riscv_vxor_tum(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint32mf2_t test___riscv_vxor_tum(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint32m1_t test___riscv_vxor_tum(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint32m2_t test___riscv_vxor_tum(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint32m4_t test___riscv_vxor_tum(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint32m8_t test___riscv_vxor_tum(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint64m1_t test___riscv_vxor_tum(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint64m2_t test___riscv_vxor_tum(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint64m4_t test___riscv_vxor_tum(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint64m8_t test___riscv_vxor_tum(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 8 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vxor_vx_tum_rv64-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vxor_vx_tum_rv64-1.C
new file mode 100644
index 00000000000..75d0adf9345
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vxor_vx_tum_rv64-1.C
@@ -0,0 +1,292 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vxor_tum(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint8mf4_t test___riscv_vxor_tum(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint8mf2_t test___riscv_vxor_tum(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint8m1_t test___riscv_vxor_tum(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint8m2_t test___riscv_vxor_tum(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint8m4_t test___riscv_vxor_tum(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint8m8_t test___riscv_vxor_tum(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint16mf4_t test___riscv_vxor_tum(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint16mf2_t test___riscv_vxor_tum(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint16m1_t test___riscv_vxor_tum(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint16m2_t test___riscv_vxor_tum(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint16m4_t test___riscv_vxor_tum(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint16m8_t test___riscv_vxor_tum(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint32mf2_t test___riscv_vxor_tum(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint32m1_t test___riscv_vxor_tum(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint32m2_t test___riscv_vxor_tum(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint32m4_t test___riscv_vxor_tum(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint32m8_t test___riscv_vxor_tum(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint64m1_t test___riscv_vxor_tum(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint64m2_t test___riscv_vxor_tum(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint64m4_t test___riscv_vxor_tum(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint64m8_t test___riscv_vxor_tum(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint8mf8_t test___riscv_vxor_tum(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint8mf4_t test___riscv_vxor_tum(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint8mf2_t test___riscv_vxor_tum(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint8m1_t test___riscv_vxor_tum(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint8m2_t test___riscv_vxor_tum(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint8m4_t test___riscv_vxor_tum(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint8m8_t test___riscv_vxor_tum(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint16mf4_t test___riscv_vxor_tum(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint16mf2_t test___riscv_vxor_tum(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m1_t test___riscv_vxor_tum(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m2_t test___riscv_vxor_tum(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m4_t test___riscv_vxor_tum(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m8_t test___riscv_vxor_tum(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint32mf2_t test___riscv_vxor_tum(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m1_t test___riscv_vxor_tum(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m2_t test___riscv_vxor_tum(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m4_t test___riscv_vxor_tum(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m8_t test___riscv_vxor_tum(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m1_t test___riscv_vxor_tum(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m2_t test___riscv_vxor_tum(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m4_t test___riscv_vxor_tum(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m8_t test___riscv_vxor_tum(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vxor_vx_tum_rv64-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vxor_vx_tum_rv64-2.C
new file mode 100644
index 00000000000..c2cec33b7d3
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vxor_vx_tum_rv64-2.C
@@ -0,0 +1,292 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vxor_tum(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,31);
+}
+
+
+vint8mf4_t test___riscv_vxor_tum(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,31);
+}
+
+
+vint8mf2_t test___riscv_vxor_tum(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,31);
+}
+
+
+vint8m1_t test___riscv_vxor_tum(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,31);
+}
+
+
+vint8m2_t test___riscv_vxor_tum(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,31);
+}
+
+
+vint8m4_t test___riscv_vxor_tum(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,31);
+}
+
+
+vint8m8_t test___riscv_vxor_tum(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,31);
+}
+
+
+vint16mf4_t test___riscv_vxor_tum(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,31);
+}
+
+
+vint16mf2_t test___riscv_vxor_tum(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,31);
+}
+
+
+vint16m1_t test___riscv_vxor_tum(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,31);
+}
+
+
+vint16m2_t test___riscv_vxor_tum(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,31);
+}
+
+
+vint16m4_t test___riscv_vxor_tum(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,31);
+}
+
+
+vint16m8_t test___riscv_vxor_tum(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,31);
+}
+
+
+vint32mf2_t test___riscv_vxor_tum(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,31);
+}
+
+
+vint32m1_t test___riscv_vxor_tum(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,31);
+}
+
+
+vint32m2_t test___riscv_vxor_tum(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,31);
+}
+
+
+vint32m4_t test___riscv_vxor_tum(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,31);
+}
+
+
+vint32m8_t test___riscv_vxor_tum(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,31);
+}
+
+
+vint64m1_t test___riscv_vxor_tum(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,31);
+}
+
+
+vint64m2_t test___riscv_vxor_tum(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,31);
+}
+
+
+vint64m4_t test___riscv_vxor_tum(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,31);
+}
+
+
+vint64m8_t test___riscv_vxor_tum(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint8mf8_t test___riscv_vxor_tum(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint8mf4_t test___riscv_vxor_tum(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint8mf2_t test___riscv_vxor_tum(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint8m1_t test___riscv_vxor_tum(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint8m2_t test___riscv_vxor_tum(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint8m4_t test___riscv_vxor_tum(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint8m8_t test___riscv_vxor_tum(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint16mf4_t test___riscv_vxor_tum(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint16mf2_t test___riscv_vxor_tum(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint16m1_t test___riscv_vxor_tum(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint16m2_t test___riscv_vxor_tum(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint16m4_t test___riscv_vxor_tum(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint16m8_t test___riscv_vxor_tum(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint32mf2_t test___riscv_vxor_tum(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint32m1_t test___riscv_vxor_tum(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint32m2_t test___riscv_vxor_tum(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint32m4_t test___riscv_vxor_tum(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint32m8_t test___riscv_vxor_tum(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint64m1_t test___riscv_vxor_tum(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint64m2_t test___riscv_vxor_tum(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint64m4_t test___riscv_vxor_tum(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint64m8_t test___riscv_vxor_tum(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vxor_vx_tum_rv64-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vxor_vx_tum_rv64-3.C
new file mode 100644
index 00000000000..011dd37c366
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vxor_vx_tum_rv64-3.C
@@ -0,0 +1,292 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vxor_tum(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,32);
+}
+
+
+vint8mf4_t test___riscv_vxor_tum(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,32);
+}
+
+
+vint8mf2_t test___riscv_vxor_tum(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,32);
+}
+
+
+vint8m1_t test___riscv_vxor_tum(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,32);
+}
+
+
+vint8m2_t test___riscv_vxor_tum(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,32);
+}
+
+
+vint8m4_t test___riscv_vxor_tum(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,32);
+}
+
+
+vint8m8_t test___riscv_vxor_tum(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,32);
+}
+
+
+vint16mf4_t test___riscv_vxor_tum(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,32);
+}
+
+
+vint16mf2_t test___riscv_vxor_tum(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,32);
+}
+
+
+vint16m1_t test___riscv_vxor_tum(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,32);
+}
+
+
+vint16m2_t test___riscv_vxor_tum(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,32);
+}
+
+
+vint16m4_t test___riscv_vxor_tum(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,32);
+}
+
+
+vint16m8_t test___riscv_vxor_tum(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,32);
+}
+
+
+vint32mf2_t test___riscv_vxor_tum(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,32);
+}
+
+
+vint32m1_t test___riscv_vxor_tum(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,32);
+}
+
+
+vint32m2_t test___riscv_vxor_tum(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,32);
+}
+
+
+vint32m4_t test___riscv_vxor_tum(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,32);
+}
+
+
+vint32m8_t test___riscv_vxor_tum(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,32);
+}
+
+
+vint64m1_t test___riscv_vxor_tum(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,32);
+}
+
+
+vint64m2_t test___riscv_vxor_tum(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,32);
+}
+
+
+vint64m4_t test___riscv_vxor_tum(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,32);
+}
+
+
+vint64m8_t test___riscv_vxor_tum(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint8mf8_t test___riscv_vxor_tum(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint8mf4_t test___riscv_vxor_tum(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint8mf2_t test___riscv_vxor_tum(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint8m1_t test___riscv_vxor_tum(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint8m2_t test___riscv_vxor_tum(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint8m4_t test___riscv_vxor_tum(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint8m8_t test___riscv_vxor_tum(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint16mf4_t test___riscv_vxor_tum(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint16mf2_t test___riscv_vxor_tum(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint16m1_t test___riscv_vxor_tum(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint16m2_t test___riscv_vxor_tum(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint16m4_t test___riscv_vxor_tum(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint16m8_t test___riscv_vxor_tum(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint32mf2_t test___riscv_vxor_tum(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint32m1_t test___riscv_vxor_tum(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint32m2_t test___riscv_vxor_tum(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint32m4_t test___riscv_vxor_tum(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint32m8_t test___riscv_vxor_tum(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint64m1_t test___riscv_vxor_tum(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint64m2_t test___riscv_vxor_tum(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint64m4_t test___riscv_vxor_tum(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint64m8_t test___riscv_vxor_tum(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vxor_tum(mask,merge,op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vxor_vx_tumu_rv32-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vxor_vx_tumu_rv32-1.C
new file mode 100644
index 00000000000..f695b485272
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vxor_vx_tumu_rv32-1.C
@@ -0,0 +1,289 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vxor_tumu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint8mf4_t test___riscv_vxor_tumu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint8mf2_t test___riscv_vxor_tumu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint8m1_t test___riscv_vxor_tumu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint8m2_t test___riscv_vxor_tumu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint8m4_t test___riscv_vxor_tumu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint8m8_t test___riscv_vxor_tumu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint16mf4_t test___riscv_vxor_tumu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint16mf2_t test___riscv_vxor_tumu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint16m1_t test___riscv_vxor_tumu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint16m2_t test___riscv_vxor_tumu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint16m4_t test___riscv_vxor_tumu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint16m8_t test___riscv_vxor_tumu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint32mf2_t test___riscv_vxor_tumu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint32m1_t test___riscv_vxor_tumu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint32m2_t test___riscv_vxor_tumu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint32m4_t test___riscv_vxor_tumu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint32m8_t test___riscv_vxor_tumu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint64m1_t test___riscv_vxor_tumu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint64m2_t test___riscv_vxor_tumu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint64m4_t test___riscv_vxor_tumu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint64m8_t test___riscv_vxor_tumu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint8mf8_t test___riscv_vxor_tumu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint8mf4_t test___riscv_vxor_tumu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint8mf2_t test___riscv_vxor_tumu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint8m1_t test___riscv_vxor_tumu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint8m2_t test___riscv_vxor_tumu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint8m4_t test___riscv_vxor_tumu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint8m8_t test___riscv_vxor_tumu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint16mf4_t test___riscv_vxor_tumu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint16mf2_t test___riscv_vxor_tumu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m1_t test___riscv_vxor_tumu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m2_t test___riscv_vxor_tumu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m4_t test___riscv_vxor_tumu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m8_t test___riscv_vxor_tumu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint32mf2_t test___riscv_vxor_tumu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m1_t test___riscv_vxor_tumu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m2_t test___riscv_vxor_tumu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m4_t test___riscv_vxor_tumu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m8_t test___riscv_vxor_tumu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m1_t test___riscv_vxor_tumu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m2_t test___riscv_vxor_tumu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m4_t test___riscv_vxor_tumu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m8_t test___riscv_vxor_tumu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 8 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vxor_vx_tumu_rv32-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vxor_vx_tumu_rv32-2.C
new file mode 100644
index 00000000000..907dd029956
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vxor_vx_tumu_rv32-2.C
@@ -0,0 +1,289 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vxor_tumu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint8mf4_t test___riscv_vxor_tumu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint8mf2_t test___riscv_vxor_tumu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint8m1_t test___riscv_vxor_tumu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint8m2_t test___riscv_vxor_tumu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint8m4_t test___riscv_vxor_tumu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint8m8_t test___riscv_vxor_tumu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint16mf4_t test___riscv_vxor_tumu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint16mf2_t test___riscv_vxor_tumu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint16m1_t test___riscv_vxor_tumu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint16m2_t test___riscv_vxor_tumu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint16m4_t test___riscv_vxor_tumu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint16m8_t test___riscv_vxor_tumu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint32mf2_t test___riscv_vxor_tumu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint32m1_t test___riscv_vxor_tumu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint32m2_t test___riscv_vxor_tumu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint32m4_t test___riscv_vxor_tumu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint32m8_t test___riscv_vxor_tumu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint64m1_t test___riscv_vxor_tumu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint64m2_t test___riscv_vxor_tumu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint64m4_t test___riscv_vxor_tumu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint64m8_t test___riscv_vxor_tumu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint8mf8_t test___riscv_vxor_tumu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint8mf4_t test___riscv_vxor_tumu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint8mf2_t test___riscv_vxor_tumu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint8m1_t test___riscv_vxor_tumu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint8m2_t test___riscv_vxor_tumu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint8m4_t test___riscv_vxor_tumu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint8m8_t test___riscv_vxor_tumu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint16mf4_t test___riscv_vxor_tumu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint16mf2_t test___riscv_vxor_tumu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint16m1_t test___riscv_vxor_tumu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint16m2_t test___riscv_vxor_tumu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint16m4_t test___riscv_vxor_tumu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint16m8_t test___riscv_vxor_tumu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint32mf2_t test___riscv_vxor_tumu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint32m1_t test___riscv_vxor_tumu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint32m2_t test___riscv_vxor_tumu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint32m4_t test___riscv_vxor_tumu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint32m8_t test___riscv_vxor_tumu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint64m1_t test___riscv_vxor_tumu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint64m2_t test___riscv_vxor_tumu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint64m4_t test___riscv_vxor_tumu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint64m8_t test___riscv_vxor_tumu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 8 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vxor_vx_tumu_rv32-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vxor_vx_tumu_rv32-3.C
new file mode 100644
index 00000000000..236f48a4fba
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vxor_vx_tumu_rv32-3.C
@@ -0,0 +1,289 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vxor_tumu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint8mf4_t test___riscv_vxor_tumu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint8mf2_t test___riscv_vxor_tumu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint8m1_t test___riscv_vxor_tumu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint8m2_t test___riscv_vxor_tumu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint8m4_t test___riscv_vxor_tumu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint8m8_t test___riscv_vxor_tumu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint16mf4_t test___riscv_vxor_tumu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint16mf2_t test___riscv_vxor_tumu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint16m1_t test___riscv_vxor_tumu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint16m2_t test___riscv_vxor_tumu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint16m4_t test___riscv_vxor_tumu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint16m8_t test___riscv_vxor_tumu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint32mf2_t test___riscv_vxor_tumu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint32m1_t test___riscv_vxor_tumu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint32m2_t test___riscv_vxor_tumu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint32m4_t test___riscv_vxor_tumu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint32m8_t test___riscv_vxor_tumu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint64m1_t test___riscv_vxor_tumu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint64m2_t test___riscv_vxor_tumu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint64m4_t test___riscv_vxor_tumu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint64m8_t test___riscv_vxor_tumu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint8mf8_t test___riscv_vxor_tumu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint8mf4_t test___riscv_vxor_tumu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint8mf2_t test___riscv_vxor_tumu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint8m1_t test___riscv_vxor_tumu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint8m2_t test___riscv_vxor_tumu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint8m4_t test___riscv_vxor_tumu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint8m8_t test___riscv_vxor_tumu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint16mf4_t test___riscv_vxor_tumu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint16mf2_t test___riscv_vxor_tumu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint16m1_t test___riscv_vxor_tumu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint16m2_t test___riscv_vxor_tumu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint16m4_t test___riscv_vxor_tumu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint16m8_t test___riscv_vxor_tumu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint32mf2_t test___riscv_vxor_tumu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint32m1_t test___riscv_vxor_tumu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint32m2_t test___riscv_vxor_tumu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint32m4_t test___riscv_vxor_tumu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint32m8_t test___riscv_vxor_tumu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint64m1_t test___riscv_vxor_tumu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint64m2_t test___riscv_vxor_tumu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint64m4_t test___riscv_vxor_tumu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint64m8_t test___riscv_vxor_tumu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 8 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vxor_vx_tumu_rv64-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vxor_vx_tumu_rv64-1.C
new file mode 100644
index 00000000000..863cd2a96ae
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vxor_vx_tumu_rv64-1.C
@@ -0,0 +1,292 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vxor_tumu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint8mf4_t test___riscv_vxor_tumu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint8mf2_t test___riscv_vxor_tumu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint8m1_t test___riscv_vxor_tumu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint8m2_t test___riscv_vxor_tumu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint8m4_t test___riscv_vxor_tumu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint8m8_t test___riscv_vxor_tumu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint16mf4_t test___riscv_vxor_tumu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint16mf2_t test___riscv_vxor_tumu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint16m1_t test___riscv_vxor_tumu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint16m2_t test___riscv_vxor_tumu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint16m4_t test___riscv_vxor_tumu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint16m8_t test___riscv_vxor_tumu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint32mf2_t test___riscv_vxor_tumu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint32m1_t test___riscv_vxor_tumu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint32m2_t test___riscv_vxor_tumu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint32m4_t test___riscv_vxor_tumu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint32m8_t test___riscv_vxor_tumu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint64m1_t test___riscv_vxor_tumu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint64m2_t test___riscv_vxor_tumu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint64m4_t test___riscv_vxor_tumu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint64m8_t test___riscv_vxor_tumu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint8mf8_t test___riscv_vxor_tumu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint8mf4_t test___riscv_vxor_tumu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint8mf2_t test___riscv_vxor_tumu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint8m1_t test___riscv_vxor_tumu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint8m2_t test___riscv_vxor_tumu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint8m4_t test___riscv_vxor_tumu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint8m8_t test___riscv_vxor_tumu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint16mf4_t test___riscv_vxor_tumu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint16mf2_t test___riscv_vxor_tumu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m1_t test___riscv_vxor_tumu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m2_t test___riscv_vxor_tumu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m4_t test___riscv_vxor_tumu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m8_t test___riscv_vxor_tumu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint32mf2_t test___riscv_vxor_tumu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m1_t test___riscv_vxor_tumu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m2_t test___riscv_vxor_tumu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m4_t test___riscv_vxor_tumu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m8_t test___riscv_vxor_tumu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m1_t test___riscv_vxor_tumu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m2_t test___riscv_vxor_tumu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m4_t test___riscv_vxor_tumu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m8_t test___riscv_vxor_tumu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vxor_vx_tumu_rv64-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vxor_vx_tumu_rv64-2.C
new file mode 100644
index 00000000000..d065cfeb2c0
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vxor_vx_tumu_rv64-2.C
@@ -0,0 +1,292 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vxor_tumu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint8mf4_t test___riscv_vxor_tumu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint8mf2_t test___riscv_vxor_tumu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint8m1_t test___riscv_vxor_tumu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint8m2_t test___riscv_vxor_tumu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint8m4_t test___riscv_vxor_tumu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint8m8_t test___riscv_vxor_tumu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint16mf4_t test___riscv_vxor_tumu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint16mf2_t test___riscv_vxor_tumu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint16m1_t test___riscv_vxor_tumu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint16m2_t test___riscv_vxor_tumu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint16m4_t test___riscv_vxor_tumu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint16m8_t test___riscv_vxor_tumu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint32mf2_t test___riscv_vxor_tumu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint32m1_t test___riscv_vxor_tumu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint32m2_t test___riscv_vxor_tumu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint32m4_t test___riscv_vxor_tumu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint32m8_t test___riscv_vxor_tumu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint64m1_t test___riscv_vxor_tumu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint64m2_t test___riscv_vxor_tumu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint64m4_t test___riscv_vxor_tumu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint64m8_t test___riscv_vxor_tumu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint8mf8_t test___riscv_vxor_tumu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint8mf4_t test___riscv_vxor_tumu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint8mf2_t test___riscv_vxor_tumu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint8m1_t test___riscv_vxor_tumu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint8m2_t test___riscv_vxor_tumu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint8m4_t test___riscv_vxor_tumu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint8m8_t test___riscv_vxor_tumu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint16mf4_t test___riscv_vxor_tumu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint16mf2_t test___riscv_vxor_tumu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint16m1_t test___riscv_vxor_tumu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint16m2_t test___riscv_vxor_tumu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint16m4_t test___riscv_vxor_tumu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint16m8_t test___riscv_vxor_tumu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint32mf2_t test___riscv_vxor_tumu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint32m1_t test___riscv_vxor_tumu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint32m2_t test___riscv_vxor_tumu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint32m4_t test___riscv_vxor_tumu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint32m8_t test___riscv_vxor_tumu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint64m1_t test___riscv_vxor_tumu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint64m2_t test___riscv_vxor_tumu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint64m4_t test___riscv_vxor_tumu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint64m8_t test___riscv_vxor_tumu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vxor_vx_tumu_rv64-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vxor_vx_tumu_rv64-3.C
new file mode 100644
index 00000000000..d37ae47e833
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vxor_vx_tumu_rv64-3.C
@@ -0,0 +1,292 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vxor_tumu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint8mf4_t test___riscv_vxor_tumu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint8mf2_t test___riscv_vxor_tumu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint8m1_t test___riscv_vxor_tumu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint8m2_t test___riscv_vxor_tumu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint8m4_t test___riscv_vxor_tumu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint8m8_t test___riscv_vxor_tumu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint16mf4_t test___riscv_vxor_tumu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint16mf2_t test___riscv_vxor_tumu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint16m1_t test___riscv_vxor_tumu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint16m2_t test___riscv_vxor_tumu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint16m4_t test___riscv_vxor_tumu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint16m8_t test___riscv_vxor_tumu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint32mf2_t test___riscv_vxor_tumu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint32m1_t test___riscv_vxor_tumu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint32m2_t test___riscv_vxor_tumu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint32m4_t test___riscv_vxor_tumu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint32m8_t test___riscv_vxor_tumu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint64m1_t test___riscv_vxor_tumu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint64m2_t test___riscv_vxor_tumu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint64m4_t test___riscv_vxor_tumu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint64m8_t test___riscv_vxor_tumu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint8mf8_t test___riscv_vxor_tumu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint8mf4_t test___riscv_vxor_tumu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint8mf2_t test___riscv_vxor_tumu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint8m1_t test___riscv_vxor_tumu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint8m2_t test___riscv_vxor_tumu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint8m4_t test___riscv_vxor_tumu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint8m8_t test___riscv_vxor_tumu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint16mf4_t test___riscv_vxor_tumu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint16mf2_t test___riscv_vxor_tumu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint16m1_t test___riscv_vxor_tumu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint16m2_t test___riscv_vxor_tumu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint16m4_t test___riscv_vxor_tumu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint16m8_t test___riscv_vxor_tumu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint32mf2_t test___riscv_vxor_tumu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint32m1_t test___riscv_vxor_tumu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint32m2_t test___riscv_vxor_tumu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint32m4_t test___riscv_vxor_tumu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint32m8_t test___riscv_vxor_tumu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint64m1_t test___riscv_vxor_tumu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint64m2_t test___riscv_vxor_tumu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint64m4_t test___riscv_vxor_tumu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint64m8_t test___riscv_vxor_tumu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vxor_tumu(mask,merge,op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */