RISC-V: Add vrem.vx C API tests

Message ID 20230203071152.170594-1-juzhe.zhong@rivai.ai
State Accepted, archived
Headers
Series RISC-V: Add vrem.vx C API tests |

Commit Message

钟居哲 Feb. 3, 2023, 7:11 a.m. UTC
  From: Ju-Zhe Zhong <juzhe.zhong@rivai.ai>

gcc/testsuite/ChangeLog:

        * gcc.target/riscv/rvv/base/vrem_vx_m_rv32-1.c: New test.
        * gcc.target/riscv/rvv/base/vrem_vx_m_rv32-2.c: New test.
        * gcc.target/riscv/rvv/base/vrem_vx_m_rv32-3.c: New test.
        * gcc.target/riscv/rvv/base/vrem_vx_m_rv64-1.c: New test.
        * gcc.target/riscv/rvv/base/vrem_vx_m_rv64-2.c: New test.
        * gcc.target/riscv/rvv/base/vrem_vx_m_rv64-3.c: New test.
        * gcc.target/riscv/rvv/base/vrem_vx_mu_rv32-1.c: New test.
        * gcc.target/riscv/rvv/base/vrem_vx_mu_rv32-2.c: New test.
        * gcc.target/riscv/rvv/base/vrem_vx_mu_rv32-3.c: New test.
        * gcc.target/riscv/rvv/base/vrem_vx_mu_rv64-1.c: New test.
        * gcc.target/riscv/rvv/base/vrem_vx_mu_rv64-2.c: New test.
        * gcc.target/riscv/rvv/base/vrem_vx_mu_rv64-3.c: New test.
        * gcc.target/riscv/rvv/base/vrem_vx_rv32-1.c: New test.
        * gcc.target/riscv/rvv/base/vrem_vx_rv32-2.c: New test.
        * gcc.target/riscv/rvv/base/vrem_vx_rv32-3.c: New test.
        * gcc.target/riscv/rvv/base/vrem_vx_rv64-1.c: New test.
        * gcc.target/riscv/rvv/base/vrem_vx_rv64-2.c: New test.
        * gcc.target/riscv/rvv/base/vrem_vx_rv64-3.c: New test.
        * gcc.target/riscv/rvv/base/vrem_vx_tu_rv32-1.c: New test.
        * gcc.target/riscv/rvv/base/vrem_vx_tu_rv32-2.c: New test.
        * gcc.target/riscv/rvv/base/vrem_vx_tu_rv32-3.c: New test.
        * gcc.target/riscv/rvv/base/vrem_vx_tu_rv64-1.c: New test.
        * gcc.target/riscv/rvv/base/vrem_vx_tu_rv64-2.c: New test.
        * gcc.target/riscv/rvv/base/vrem_vx_tu_rv64-3.c: New test.
        * gcc.target/riscv/rvv/base/vrem_vx_tum_rv32-1.c: New test.
        * gcc.target/riscv/rvv/base/vrem_vx_tum_rv32-2.c: New test.
        * gcc.target/riscv/rvv/base/vrem_vx_tum_rv32-3.c: New test.
        * gcc.target/riscv/rvv/base/vrem_vx_tum_rv64-1.c: New test.
        * gcc.target/riscv/rvv/base/vrem_vx_tum_rv64-2.c: New test.
        * gcc.target/riscv/rvv/base/vrem_vx_tum_rv64-3.c: New test.
        * gcc.target/riscv/rvv/base/vrem_vx_tumu_rv32-1.c: New test.
        * gcc.target/riscv/rvv/base/vrem_vx_tumu_rv32-2.c: New test.
        * gcc.target/riscv/rvv/base/vrem_vx_tumu_rv32-3.c: New test.
        * gcc.target/riscv/rvv/base/vrem_vx_tumu_rv64-1.c: New test.
        * gcc.target/riscv/rvv/base/vrem_vx_tumu_rv64-2.c: New test.
        * gcc.target/riscv/rvv/base/vrem_vx_tumu_rv64-3.c: New test.

---
 .../riscv/rvv/base/vrem_vx_m_rv32-1.c         | 157 +++++++++++++++++
 .../riscv/rvv/base/vrem_vx_m_rv32-2.c         | 157 +++++++++++++++++
 .../riscv/rvv/base/vrem_vx_m_rv32-3.c         | 157 +++++++++++++++++
 .../riscv/rvv/base/vrem_vx_m_rv64-1.c         | 160 ++++++++++++++++++
 .../riscv/rvv/base/vrem_vx_m_rv64-2.c         | 160 ++++++++++++++++++
 .../riscv/rvv/base/vrem_vx_m_rv64-3.c         | 160 ++++++++++++++++++
 .../riscv/rvv/base/vrem_vx_mu_rv32-1.c        | 157 +++++++++++++++++
 .../riscv/rvv/base/vrem_vx_mu_rv32-2.c        | 157 +++++++++++++++++
 .../riscv/rvv/base/vrem_vx_mu_rv32-3.c        | 157 +++++++++++++++++
 .../riscv/rvv/base/vrem_vx_mu_rv64-1.c        | 160 ++++++++++++++++++
 .../riscv/rvv/base/vrem_vx_mu_rv64-2.c        | 160 ++++++++++++++++++
 .../riscv/rvv/base/vrem_vx_mu_rv64-3.c        | 160 ++++++++++++++++++
 .../riscv/rvv/base/vrem_vx_rv32-1.c           | 157 +++++++++++++++++
 .../riscv/rvv/base/vrem_vx_rv32-2.c           | 157 +++++++++++++++++
 .../riscv/rvv/base/vrem_vx_rv32-3.c           | 157 +++++++++++++++++
 .../riscv/rvv/base/vrem_vx_rv64-1.c           | 160 ++++++++++++++++++
 .../riscv/rvv/base/vrem_vx_rv64-2.c           | 160 ++++++++++++++++++
 .../riscv/rvv/base/vrem_vx_rv64-3.c           | 160 ++++++++++++++++++
 .../riscv/rvv/base/vrem_vx_tu_rv32-1.c        | 157 +++++++++++++++++
 .../riscv/rvv/base/vrem_vx_tu_rv32-2.c        | 157 +++++++++++++++++
 .../riscv/rvv/base/vrem_vx_tu_rv32-3.c        | 157 +++++++++++++++++
 .../riscv/rvv/base/vrem_vx_tu_rv64-1.c        | 160 ++++++++++++++++++
 .../riscv/rvv/base/vrem_vx_tu_rv64-2.c        | 160 ++++++++++++++++++
 .../riscv/rvv/base/vrem_vx_tu_rv64-3.c        | 160 ++++++++++++++++++
 .../riscv/rvv/base/vrem_vx_tum_rv32-1.c       | 157 +++++++++++++++++
 .../riscv/rvv/base/vrem_vx_tum_rv32-2.c       | 157 +++++++++++++++++
 .../riscv/rvv/base/vrem_vx_tum_rv32-3.c       | 157 +++++++++++++++++
 .../riscv/rvv/base/vrem_vx_tum_rv64-1.c       | 160 ++++++++++++++++++
 .../riscv/rvv/base/vrem_vx_tum_rv64-2.c       | 160 ++++++++++++++++++
 .../riscv/rvv/base/vrem_vx_tum_rv64-3.c       | 160 ++++++++++++++++++
 .../riscv/rvv/base/vrem_vx_tumu_rv32-1.c      | 157 +++++++++++++++++
 .../riscv/rvv/base/vrem_vx_tumu_rv32-2.c      | 157 +++++++++++++++++
 .../riscv/rvv/base/vrem_vx_tumu_rv32-3.c      | 157 +++++++++++++++++
 .../riscv/rvv/base/vrem_vx_tumu_rv64-1.c      | 160 ++++++++++++++++++
 .../riscv/rvv/base/vrem_vx_tumu_rv64-2.c      | 160 ++++++++++++++++++
 .../riscv/rvv/base/vrem_vx_tumu_rv64-3.c      | 160 ++++++++++++++++++
 36 files changed, 5706 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vrem_vx_m_rv32-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vrem_vx_m_rv32-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vrem_vx_m_rv32-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vrem_vx_m_rv64-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vrem_vx_m_rv64-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vrem_vx_m_rv64-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vrem_vx_mu_rv32-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vrem_vx_mu_rv32-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vrem_vx_mu_rv32-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vrem_vx_mu_rv64-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vrem_vx_mu_rv64-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vrem_vx_mu_rv64-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vrem_vx_rv32-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vrem_vx_rv32-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vrem_vx_rv32-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vrem_vx_rv64-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vrem_vx_rv64-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vrem_vx_rv64-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vrem_vx_tu_rv32-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vrem_vx_tu_rv32-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vrem_vx_tu_rv32-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vrem_vx_tu_rv64-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vrem_vx_tu_rv64-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vrem_vx_tu_rv64-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vrem_vx_tum_rv32-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vrem_vx_tum_rv32-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vrem_vx_tum_rv32-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vrem_vx_tum_rv64-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vrem_vx_tum_rv64-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vrem_vx_tum_rv64-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vrem_vx_tumu_rv32-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vrem_vx_tumu_rv32-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vrem_vx_tumu_rv32-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vrem_vx_tumu_rv64-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vrem_vx_tumu_rv64-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vrem_vx_tumu_rv64-3.c
  

Patch

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vrem_vx_m_rv32-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vrem_vx_m_rv32-1.c
new file mode 100644
index 00000000000..f85affaf6fd
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vrem_vx_m_rv32-1.c
@@ -0,0 +1,157 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vrem_vx_i8mf8_m(vbool64_t mask,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i8mf8_m(mask,op1,op2,vl);
+}
+
+
+vint8mf4_t test___riscv_vrem_vx_i8mf4_m(vbool32_t mask,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i8mf4_m(mask,op1,op2,vl);
+}
+
+
+vint8mf2_t test___riscv_vrem_vx_i8mf2_m(vbool16_t mask,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i8mf2_m(mask,op1,op2,vl);
+}
+
+
+vint8m1_t test___riscv_vrem_vx_i8m1_m(vbool8_t mask,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i8m1_m(mask,op1,op2,vl);
+}
+
+
+vint8m2_t test___riscv_vrem_vx_i8m2_m(vbool4_t mask,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i8m2_m(mask,op1,op2,vl);
+}
+
+
+vint8m4_t test___riscv_vrem_vx_i8m4_m(vbool2_t mask,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i8m4_m(mask,op1,op2,vl);
+}
+
+
+vint8m8_t test___riscv_vrem_vx_i8m8_m(vbool1_t mask,vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i8m8_m(mask,op1,op2,vl);
+}
+
+
+vint16mf4_t test___riscv_vrem_vx_i16mf4_m(vbool64_t mask,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i16mf4_m(mask,op1,op2,vl);
+}
+
+
+vint16mf2_t test___riscv_vrem_vx_i16mf2_m(vbool32_t mask,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i16mf2_m(mask,op1,op2,vl);
+}
+
+
+vint16m1_t test___riscv_vrem_vx_i16m1_m(vbool16_t mask,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i16m1_m(mask,op1,op2,vl);
+}
+
+
+vint16m2_t test___riscv_vrem_vx_i16m2_m(vbool8_t mask,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i16m2_m(mask,op1,op2,vl);
+}
+
+
+vint16m4_t test___riscv_vrem_vx_i16m4_m(vbool4_t mask,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i16m4_m(mask,op1,op2,vl);
+}
+
+
+vint16m8_t test___riscv_vrem_vx_i16m8_m(vbool2_t mask,vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i16m8_m(mask,op1,op2,vl);
+}
+
+
+vint32mf2_t test___riscv_vrem_vx_i32mf2_m(vbool64_t mask,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i32mf2_m(mask,op1,op2,vl);
+}
+
+
+vint32m1_t test___riscv_vrem_vx_i32m1_m(vbool32_t mask,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i32m1_m(mask,op1,op2,vl);
+}
+
+
+vint32m2_t test___riscv_vrem_vx_i32m2_m(vbool16_t mask,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i32m2_m(mask,op1,op2,vl);
+}
+
+
+vint32m4_t test___riscv_vrem_vx_i32m4_m(vbool8_t mask,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i32m4_m(mask,op1,op2,vl);
+}
+
+
+vint32m8_t test___riscv_vrem_vx_i32m8_m(vbool4_t mask,vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i32m8_m(mask,op1,op2,vl);
+}
+
+
+vint64m1_t test___riscv_vrem_vx_i64m1_m(vbool64_t mask,vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i64m1_m(mask,op1,op2,vl);
+}
+
+
+vint64m2_t test___riscv_vrem_vx_i64m2_m(vbool32_t mask,vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i64m2_m(mask,op1,op2,vl);
+}
+
+
+vint64m4_t test___riscv_vrem_vx_i64m4_m(vbool16_t mask,vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i64m4_m(mask,op1,op2,vl);
+}
+
+
+vint64m8_t test___riscv_vrem_vx_i64m8_m(vbool8_t mask,vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i64m8_m(mask,op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vrem\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 4 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vrem_vx_m_rv32-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vrem_vx_m_rv32-2.c
new file mode 100644
index 00000000000..7e85d5e3195
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vrem_vx_m_rv32-2.c
@@ -0,0 +1,157 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vrem_vx_i8mf8_m(vbool64_t mask,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i8mf8_m(mask,op1,op2,31);
+}
+
+
+vint8mf4_t test___riscv_vrem_vx_i8mf4_m(vbool32_t mask,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i8mf4_m(mask,op1,op2,31);
+}
+
+
+vint8mf2_t test___riscv_vrem_vx_i8mf2_m(vbool16_t mask,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i8mf2_m(mask,op1,op2,31);
+}
+
+
+vint8m1_t test___riscv_vrem_vx_i8m1_m(vbool8_t mask,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i8m1_m(mask,op1,op2,31);
+}
+
+
+vint8m2_t test___riscv_vrem_vx_i8m2_m(vbool4_t mask,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i8m2_m(mask,op1,op2,31);
+}
+
+
+vint8m4_t test___riscv_vrem_vx_i8m4_m(vbool2_t mask,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i8m4_m(mask,op1,op2,31);
+}
+
+
+vint8m8_t test___riscv_vrem_vx_i8m8_m(vbool1_t mask,vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i8m8_m(mask,op1,op2,31);
+}
+
+
+vint16mf4_t test___riscv_vrem_vx_i16mf4_m(vbool64_t mask,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i16mf4_m(mask,op1,op2,31);
+}
+
+
+vint16mf2_t test___riscv_vrem_vx_i16mf2_m(vbool32_t mask,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i16mf2_m(mask,op1,op2,31);
+}
+
+
+vint16m1_t test___riscv_vrem_vx_i16m1_m(vbool16_t mask,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i16m1_m(mask,op1,op2,31);
+}
+
+
+vint16m2_t test___riscv_vrem_vx_i16m2_m(vbool8_t mask,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i16m2_m(mask,op1,op2,31);
+}
+
+
+vint16m4_t test___riscv_vrem_vx_i16m4_m(vbool4_t mask,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i16m4_m(mask,op1,op2,31);
+}
+
+
+vint16m8_t test___riscv_vrem_vx_i16m8_m(vbool2_t mask,vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i16m8_m(mask,op1,op2,31);
+}
+
+
+vint32mf2_t test___riscv_vrem_vx_i32mf2_m(vbool64_t mask,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i32mf2_m(mask,op1,op2,31);
+}
+
+
+vint32m1_t test___riscv_vrem_vx_i32m1_m(vbool32_t mask,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i32m1_m(mask,op1,op2,31);
+}
+
+
+vint32m2_t test___riscv_vrem_vx_i32m2_m(vbool16_t mask,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i32m2_m(mask,op1,op2,31);
+}
+
+
+vint32m4_t test___riscv_vrem_vx_i32m4_m(vbool8_t mask,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i32m4_m(mask,op1,op2,31);
+}
+
+
+vint32m8_t test___riscv_vrem_vx_i32m8_m(vbool4_t mask,vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i32m8_m(mask,op1,op2,31);
+}
+
+
+vint64m1_t test___riscv_vrem_vx_i64m1_m(vbool64_t mask,vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i64m1_m(mask,op1,op2,31);
+}
+
+
+vint64m2_t test___riscv_vrem_vx_i64m2_m(vbool32_t mask,vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i64m2_m(mask,op1,op2,31);
+}
+
+
+vint64m4_t test___riscv_vrem_vx_i64m4_m(vbool16_t mask,vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i64m4_m(mask,op1,op2,31);
+}
+
+
+vint64m8_t test___riscv_vrem_vx_i64m8_m(vbool8_t mask,vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i64m8_m(mask,op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vrem\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 4 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vrem_vx_m_rv32-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vrem_vx_m_rv32-3.c
new file mode 100644
index 00000000000..0ed013165a8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vrem_vx_m_rv32-3.c
@@ -0,0 +1,157 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vrem_vx_i8mf8_m(vbool64_t mask,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i8mf8_m(mask,op1,op2,32);
+}
+
+
+vint8mf4_t test___riscv_vrem_vx_i8mf4_m(vbool32_t mask,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i8mf4_m(mask,op1,op2,32);
+}
+
+
+vint8mf2_t test___riscv_vrem_vx_i8mf2_m(vbool16_t mask,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i8mf2_m(mask,op1,op2,32);
+}
+
+
+vint8m1_t test___riscv_vrem_vx_i8m1_m(vbool8_t mask,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i8m1_m(mask,op1,op2,32);
+}
+
+
+vint8m2_t test___riscv_vrem_vx_i8m2_m(vbool4_t mask,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i8m2_m(mask,op1,op2,32);
+}
+
+
+vint8m4_t test___riscv_vrem_vx_i8m4_m(vbool2_t mask,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i8m4_m(mask,op1,op2,32);
+}
+
+
+vint8m8_t test___riscv_vrem_vx_i8m8_m(vbool1_t mask,vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i8m8_m(mask,op1,op2,32);
+}
+
+
+vint16mf4_t test___riscv_vrem_vx_i16mf4_m(vbool64_t mask,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i16mf4_m(mask,op1,op2,32);
+}
+
+
+vint16mf2_t test___riscv_vrem_vx_i16mf2_m(vbool32_t mask,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i16mf2_m(mask,op1,op2,32);
+}
+
+
+vint16m1_t test___riscv_vrem_vx_i16m1_m(vbool16_t mask,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i16m1_m(mask,op1,op2,32);
+}
+
+
+vint16m2_t test___riscv_vrem_vx_i16m2_m(vbool8_t mask,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i16m2_m(mask,op1,op2,32);
+}
+
+
+vint16m4_t test___riscv_vrem_vx_i16m4_m(vbool4_t mask,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i16m4_m(mask,op1,op2,32);
+}
+
+
+vint16m8_t test___riscv_vrem_vx_i16m8_m(vbool2_t mask,vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i16m8_m(mask,op1,op2,32);
+}
+
+
+vint32mf2_t test___riscv_vrem_vx_i32mf2_m(vbool64_t mask,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i32mf2_m(mask,op1,op2,32);
+}
+
+
+vint32m1_t test___riscv_vrem_vx_i32m1_m(vbool32_t mask,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i32m1_m(mask,op1,op2,32);
+}
+
+
+vint32m2_t test___riscv_vrem_vx_i32m2_m(vbool16_t mask,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i32m2_m(mask,op1,op2,32);
+}
+
+
+vint32m4_t test___riscv_vrem_vx_i32m4_m(vbool8_t mask,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i32m4_m(mask,op1,op2,32);
+}
+
+
+vint32m8_t test___riscv_vrem_vx_i32m8_m(vbool4_t mask,vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i32m8_m(mask,op1,op2,32);
+}
+
+
+vint64m1_t test___riscv_vrem_vx_i64m1_m(vbool64_t mask,vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i64m1_m(mask,op1,op2,32);
+}
+
+
+vint64m2_t test___riscv_vrem_vx_i64m2_m(vbool32_t mask,vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i64m2_m(mask,op1,op2,32);
+}
+
+
+vint64m4_t test___riscv_vrem_vx_i64m4_m(vbool16_t mask,vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i64m4_m(mask,op1,op2,32);
+}
+
+
+vint64m8_t test___riscv_vrem_vx_i64m8_m(vbool8_t mask,vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i64m8_m(mask,op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vrem\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 4 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vrem_vx_m_rv64-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vrem_vx_m_rv64-1.c
new file mode 100644
index 00000000000..c28491cc0d0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vrem_vx_m_rv64-1.c
@@ -0,0 +1,160 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vrem_vx_i8mf8_m(vbool64_t mask,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i8mf8_m(mask,op1,op2,vl);
+}
+
+
+vint8mf4_t test___riscv_vrem_vx_i8mf4_m(vbool32_t mask,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i8mf4_m(mask,op1,op2,vl);
+}
+
+
+vint8mf2_t test___riscv_vrem_vx_i8mf2_m(vbool16_t mask,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i8mf2_m(mask,op1,op2,vl);
+}
+
+
+vint8m1_t test___riscv_vrem_vx_i8m1_m(vbool8_t mask,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i8m1_m(mask,op1,op2,vl);
+}
+
+
+vint8m2_t test___riscv_vrem_vx_i8m2_m(vbool4_t mask,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i8m2_m(mask,op1,op2,vl);
+}
+
+
+vint8m4_t test___riscv_vrem_vx_i8m4_m(vbool2_t mask,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i8m4_m(mask,op1,op2,vl);
+}
+
+
+vint8m8_t test___riscv_vrem_vx_i8m8_m(vbool1_t mask,vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i8m8_m(mask,op1,op2,vl);
+}
+
+
+vint16mf4_t test___riscv_vrem_vx_i16mf4_m(vbool64_t mask,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i16mf4_m(mask,op1,op2,vl);
+}
+
+
+vint16mf2_t test___riscv_vrem_vx_i16mf2_m(vbool32_t mask,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i16mf2_m(mask,op1,op2,vl);
+}
+
+
+vint16m1_t test___riscv_vrem_vx_i16m1_m(vbool16_t mask,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i16m1_m(mask,op1,op2,vl);
+}
+
+
+vint16m2_t test___riscv_vrem_vx_i16m2_m(vbool8_t mask,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i16m2_m(mask,op1,op2,vl);
+}
+
+
+vint16m4_t test___riscv_vrem_vx_i16m4_m(vbool4_t mask,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i16m4_m(mask,op1,op2,vl);
+}
+
+
+vint16m8_t test___riscv_vrem_vx_i16m8_m(vbool2_t mask,vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i16m8_m(mask,op1,op2,vl);
+}
+
+
+vint32mf2_t test___riscv_vrem_vx_i32mf2_m(vbool64_t mask,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i32mf2_m(mask,op1,op2,vl);
+}
+
+
+vint32m1_t test___riscv_vrem_vx_i32m1_m(vbool32_t mask,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i32m1_m(mask,op1,op2,vl);
+}
+
+
+vint32m2_t test___riscv_vrem_vx_i32m2_m(vbool16_t mask,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i32m2_m(mask,op1,op2,vl);
+}
+
+
+vint32m4_t test___riscv_vrem_vx_i32m4_m(vbool8_t mask,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i32m4_m(mask,op1,op2,vl);
+}
+
+
+vint32m8_t test___riscv_vrem_vx_i32m8_m(vbool4_t mask,vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i32m8_m(mask,op1,op2,vl);
+}
+
+
+vint64m1_t test___riscv_vrem_vx_i64m1_m(vbool64_t mask,vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i64m1_m(mask,op1,op2,vl);
+}
+
+
+vint64m2_t test___riscv_vrem_vx_i64m2_m(vbool32_t mask,vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i64m2_m(mask,op1,op2,vl);
+}
+
+
+vint64m4_t test___riscv_vrem_vx_i64m4_m(vbool16_t mask,vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i64m4_m(mask,op1,op2,vl);
+}
+
+
+vint64m8_t test___riscv_vrem_vx_i64m8_m(vbool8_t mask,vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i64m8_m(mask,op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vrem_vx_m_rv64-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vrem_vx_m_rv64-2.c
new file mode 100644
index 00000000000..e30ab855bc8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vrem_vx_m_rv64-2.c
@@ -0,0 +1,160 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vrem_vx_i8mf8_m(vbool64_t mask,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i8mf8_m(mask,op1,op2,31);
+}
+
+
+vint8mf4_t test___riscv_vrem_vx_i8mf4_m(vbool32_t mask,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i8mf4_m(mask,op1,op2,31);
+}
+
+
+vint8mf2_t test___riscv_vrem_vx_i8mf2_m(vbool16_t mask,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i8mf2_m(mask,op1,op2,31);
+}
+
+
+vint8m1_t test___riscv_vrem_vx_i8m1_m(vbool8_t mask,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i8m1_m(mask,op1,op2,31);
+}
+
+
+vint8m2_t test___riscv_vrem_vx_i8m2_m(vbool4_t mask,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i8m2_m(mask,op1,op2,31);
+}
+
+
+vint8m4_t test___riscv_vrem_vx_i8m4_m(vbool2_t mask,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i8m4_m(mask,op1,op2,31);
+}
+
+
+vint8m8_t test___riscv_vrem_vx_i8m8_m(vbool1_t mask,vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i8m8_m(mask,op1,op2,31);
+}
+
+
+vint16mf4_t test___riscv_vrem_vx_i16mf4_m(vbool64_t mask,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i16mf4_m(mask,op1,op2,31);
+}
+
+
+vint16mf2_t test___riscv_vrem_vx_i16mf2_m(vbool32_t mask,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i16mf2_m(mask,op1,op2,31);
+}
+
+
+vint16m1_t test___riscv_vrem_vx_i16m1_m(vbool16_t mask,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i16m1_m(mask,op1,op2,31);
+}
+
+
+vint16m2_t test___riscv_vrem_vx_i16m2_m(vbool8_t mask,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i16m2_m(mask,op1,op2,31);
+}
+
+
+vint16m4_t test___riscv_vrem_vx_i16m4_m(vbool4_t mask,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i16m4_m(mask,op1,op2,31);
+}
+
+
+vint16m8_t test___riscv_vrem_vx_i16m8_m(vbool2_t mask,vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i16m8_m(mask,op1,op2,31);
+}
+
+
+vint32mf2_t test___riscv_vrem_vx_i32mf2_m(vbool64_t mask,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i32mf2_m(mask,op1,op2,31);
+}
+
+
+vint32m1_t test___riscv_vrem_vx_i32m1_m(vbool32_t mask,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i32m1_m(mask,op1,op2,31);
+}
+
+
+vint32m2_t test___riscv_vrem_vx_i32m2_m(vbool16_t mask,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i32m2_m(mask,op1,op2,31);
+}
+
+
+vint32m4_t test___riscv_vrem_vx_i32m4_m(vbool8_t mask,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i32m4_m(mask,op1,op2,31);
+}
+
+
+vint32m8_t test___riscv_vrem_vx_i32m8_m(vbool4_t mask,vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i32m8_m(mask,op1,op2,31);
+}
+
+
+vint64m1_t test___riscv_vrem_vx_i64m1_m(vbool64_t mask,vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i64m1_m(mask,op1,op2,31);
+}
+
+
+vint64m2_t test___riscv_vrem_vx_i64m2_m(vbool32_t mask,vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i64m2_m(mask,op1,op2,31);
+}
+
+
+vint64m4_t test___riscv_vrem_vx_i64m4_m(vbool16_t mask,vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i64m4_m(mask,op1,op2,31);
+}
+
+
+vint64m8_t test___riscv_vrem_vx_i64m8_m(vbool8_t mask,vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i64m8_m(mask,op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vrem_vx_m_rv64-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vrem_vx_m_rv64-3.c
new file mode 100644
index 00000000000..3fa5b5bf775
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vrem_vx_m_rv64-3.c
@@ -0,0 +1,160 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vrem_vx_i8mf8_m(vbool64_t mask,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i8mf8_m(mask,op1,op2,32);
+}
+
+
+vint8mf4_t test___riscv_vrem_vx_i8mf4_m(vbool32_t mask,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i8mf4_m(mask,op1,op2,32);
+}
+
+
+vint8mf2_t test___riscv_vrem_vx_i8mf2_m(vbool16_t mask,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i8mf2_m(mask,op1,op2,32);
+}
+
+
+vint8m1_t test___riscv_vrem_vx_i8m1_m(vbool8_t mask,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i8m1_m(mask,op1,op2,32);
+}
+
+
+vint8m2_t test___riscv_vrem_vx_i8m2_m(vbool4_t mask,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i8m2_m(mask,op1,op2,32);
+}
+
+
+vint8m4_t test___riscv_vrem_vx_i8m4_m(vbool2_t mask,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i8m4_m(mask,op1,op2,32);
+}
+
+
+vint8m8_t test___riscv_vrem_vx_i8m8_m(vbool1_t mask,vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i8m8_m(mask,op1,op2,32);
+}
+
+
+vint16mf4_t test___riscv_vrem_vx_i16mf4_m(vbool64_t mask,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i16mf4_m(mask,op1,op2,32);
+}
+
+
+vint16mf2_t test___riscv_vrem_vx_i16mf2_m(vbool32_t mask,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i16mf2_m(mask,op1,op2,32);
+}
+
+
+vint16m1_t test___riscv_vrem_vx_i16m1_m(vbool16_t mask,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i16m1_m(mask,op1,op2,32);
+}
+
+
+vint16m2_t test___riscv_vrem_vx_i16m2_m(vbool8_t mask,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i16m2_m(mask,op1,op2,32);
+}
+
+
+vint16m4_t test___riscv_vrem_vx_i16m4_m(vbool4_t mask,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i16m4_m(mask,op1,op2,32);
+}
+
+
+vint16m8_t test___riscv_vrem_vx_i16m8_m(vbool2_t mask,vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i16m8_m(mask,op1,op2,32);
+}
+
+
+vint32mf2_t test___riscv_vrem_vx_i32mf2_m(vbool64_t mask,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i32mf2_m(mask,op1,op2,32);
+}
+
+
+vint32m1_t test___riscv_vrem_vx_i32m1_m(vbool32_t mask,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i32m1_m(mask,op1,op2,32);
+}
+
+
+vint32m2_t test___riscv_vrem_vx_i32m2_m(vbool16_t mask,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i32m2_m(mask,op1,op2,32);
+}
+
+
+vint32m4_t test___riscv_vrem_vx_i32m4_m(vbool8_t mask,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i32m4_m(mask,op1,op2,32);
+}
+
+
+vint32m8_t test___riscv_vrem_vx_i32m8_m(vbool4_t mask,vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i32m8_m(mask,op1,op2,32);
+}
+
+
+vint64m1_t test___riscv_vrem_vx_i64m1_m(vbool64_t mask,vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i64m1_m(mask,op1,op2,32);
+}
+
+
+vint64m2_t test___riscv_vrem_vx_i64m2_m(vbool32_t mask,vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i64m2_m(mask,op1,op2,32);
+}
+
+
+vint64m4_t test___riscv_vrem_vx_i64m4_m(vbool16_t mask,vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i64m4_m(mask,op1,op2,32);
+}
+
+
+vint64m8_t test___riscv_vrem_vx_i64m8_m(vbool8_t mask,vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i64m8_m(mask,op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vrem_vx_mu_rv32-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vrem_vx_mu_rv32-1.c
new file mode 100644
index 00000000000..aad06e48f7e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vrem_vx_mu_rv32-1.c
@@ -0,0 +1,157 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vrem_vx_i8mf8_mu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i8mf8_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint8mf4_t test___riscv_vrem_vx_i8mf4_mu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i8mf4_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint8mf2_t test___riscv_vrem_vx_i8mf2_mu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i8mf2_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint8m1_t test___riscv_vrem_vx_i8m1_mu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i8m1_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint8m2_t test___riscv_vrem_vx_i8m2_mu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i8m2_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint8m4_t test___riscv_vrem_vx_i8m4_mu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i8m4_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint8m8_t test___riscv_vrem_vx_i8m8_mu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i8m8_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint16mf4_t test___riscv_vrem_vx_i16mf4_mu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i16mf4_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint16mf2_t test___riscv_vrem_vx_i16mf2_mu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i16mf2_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint16m1_t test___riscv_vrem_vx_i16m1_mu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i16m1_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint16m2_t test___riscv_vrem_vx_i16m2_mu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i16m2_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint16m4_t test___riscv_vrem_vx_i16m4_mu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i16m4_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint16m8_t test___riscv_vrem_vx_i16m8_mu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i16m8_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint32mf2_t test___riscv_vrem_vx_i32mf2_mu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i32mf2_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint32m1_t test___riscv_vrem_vx_i32m1_mu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i32m1_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint32m2_t test___riscv_vrem_vx_i32m2_mu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i32m2_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint32m4_t test___riscv_vrem_vx_i32m4_mu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i32m4_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint32m8_t test___riscv_vrem_vx_i32m8_mu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i32m8_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint64m1_t test___riscv_vrem_vx_i64m1_mu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i64m1_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint64m2_t test___riscv_vrem_vx_i64m2_mu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i64m2_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint64m4_t test___riscv_vrem_vx_i64m4_mu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i64m4_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint64m8_t test___riscv_vrem_vx_i64m8_mu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i64m8_mu(mask,merge,op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*mu\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vrem\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 4 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vrem_vx_mu_rv32-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vrem_vx_mu_rv32-2.c
new file mode 100644
index 00000000000..e73b0c18e5e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vrem_vx_mu_rv32-2.c
@@ -0,0 +1,157 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vrem_vx_i8mf8_mu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i8mf8_mu(mask,merge,op1,op2,31);
+}
+
+
+vint8mf4_t test___riscv_vrem_vx_i8mf4_mu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i8mf4_mu(mask,merge,op1,op2,31);
+}
+
+
+vint8mf2_t test___riscv_vrem_vx_i8mf2_mu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i8mf2_mu(mask,merge,op1,op2,31);
+}
+
+
+vint8m1_t test___riscv_vrem_vx_i8m1_mu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i8m1_mu(mask,merge,op1,op2,31);
+}
+
+
+vint8m2_t test___riscv_vrem_vx_i8m2_mu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i8m2_mu(mask,merge,op1,op2,31);
+}
+
+
+vint8m4_t test___riscv_vrem_vx_i8m4_mu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i8m4_mu(mask,merge,op1,op2,31);
+}
+
+
+vint8m8_t test___riscv_vrem_vx_i8m8_mu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i8m8_mu(mask,merge,op1,op2,31);
+}
+
+
+vint16mf4_t test___riscv_vrem_vx_i16mf4_mu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i16mf4_mu(mask,merge,op1,op2,31);
+}
+
+
+vint16mf2_t test___riscv_vrem_vx_i16mf2_mu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i16mf2_mu(mask,merge,op1,op2,31);
+}
+
+
+vint16m1_t test___riscv_vrem_vx_i16m1_mu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i16m1_mu(mask,merge,op1,op2,31);
+}
+
+
+vint16m2_t test___riscv_vrem_vx_i16m2_mu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i16m2_mu(mask,merge,op1,op2,31);
+}
+
+
+vint16m4_t test___riscv_vrem_vx_i16m4_mu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i16m4_mu(mask,merge,op1,op2,31);
+}
+
+
+vint16m8_t test___riscv_vrem_vx_i16m8_mu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i16m8_mu(mask,merge,op1,op2,31);
+}
+
+
+vint32mf2_t test___riscv_vrem_vx_i32mf2_mu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i32mf2_mu(mask,merge,op1,op2,31);
+}
+
+
+vint32m1_t test___riscv_vrem_vx_i32m1_mu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i32m1_mu(mask,merge,op1,op2,31);
+}
+
+
+vint32m2_t test___riscv_vrem_vx_i32m2_mu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i32m2_mu(mask,merge,op1,op2,31);
+}
+
+
+vint32m4_t test___riscv_vrem_vx_i32m4_mu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i32m4_mu(mask,merge,op1,op2,31);
+}
+
+
+vint32m8_t test___riscv_vrem_vx_i32m8_mu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i32m8_mu(mask,merge,op1,op2,31);
+}
+
+
+vint64m1_t test___riscv_vrem_vx_i64m1_mu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i64m1_mu(mask,merge,op1,op2,31);
+}
+
+
+vint64m2_t test___riscv_vrem_vx_i64m2_mu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i64m2_mu(mask,merge,op1,op2,31);
+}
+
+
+vint64m4_t test___riscv_vrem_vx_i64m4_mu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i64m4_mu(mask,merge,op1,op2,31);
+}
+
+
+vint64m8_t test___riscv_vrem_vx_i64m8_mu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i64m8_mu(mask,merge,op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*mu\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*mu\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*mu\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*mu\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*mu\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*mu\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*mu\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*mu\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*mu\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*mu\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*mu\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*mu\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vrem\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 4 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vrem_vx_mu_rv32-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vrem_vx_mu_rv32-3.c
new file mode 100644
index 00000000000..14454719b19
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vrem_vx_mu_rv32-3.c
@@ -0,0 +1,157 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vrem_vx_i8mf8_mu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i8mf8_mu(mask,merge,op1,op2,32);
+}
+
+
+vint8mf4_t test___riscv_vrem_vx_i8mf4_mu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i8mf4_mu(mask,merge,op1,op2,32);
+}
+
+
+vint8mf2_t test___riscv_vrem_vx_i8mf2_mu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i8mf2_mu(mask,merge,op1,op2,32);
+}
+
+
+vint8m1_t test___riscv_vrem_vx_i8m1_mu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i8m1_mu(mask,merge,op1,op2,32);
+}
+
+
+vint8m2_t test___riscv_vrem_vx_i8m2_mu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i8m2_mu(mask,merge,op1,op2,32);
+}
+
+
+vint8m4_t test___riscv_vrem_vx_i8m4_mu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i8m4_mu(mask,merge,op1,op2,32);
+}
+
+
+vint8m8_t test___riscv_vrem_vx_i8m8_mu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i8m8_mu(mask,merge,op1,op2,32);
+}
+
+
+vint16mf4_t test___riscv_vrem_vx_i16mf4_mu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i16mf4_mu(mask,merge,op1,op2,32);
+}
+
+
+vint16mf2_t test___riscv_vrem_vx_i16mf2_mu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i16mf2_mu(mask,merge,op1,op2,32);
+}
+
+
+vint16m1_t test___riscv_vrem_vx_i16m1_mu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i16m1_mu(mask,merge,op1,op2,32);
+}
+
+
+vint16m2_t test___riscv_vrem_vx_i16m2_mu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i16m2_mu(mask,merge,op1,op2,32);
+}
+
+
+vint16m4_t test___riscv_vrem_vx_i16m4_mu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i16m4_mu(mask,merge,op1,op2,32);
+}
+
+
+vint16m8_t test___riscv_vrem_vx_i16m8_mu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i16m8_mu(mask,merge,op1,op2,32);
+}
+
+
+vint32mf2_t test___riscv_vrem_vx_i32mf2_mu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i32mf2_mu(mask,merge,op1,op2,32);
+}
+
+
+vint32m1_t test___riscv_vrem_vx_i32m1_mu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i32m1_mu(mask,merge,op1,op2,32);
+}
+
+
+vint32m2_t test___riscv_vrem_vx_i32m2_mu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i32m2_mu(mask,merge,op1,op2,32);
+}
+
+
+vint32m4_t test___riscv_vrem_vx_i32m4_mu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i32m4_mu(mask,merge,op1,op2,32);
+}
+
+
+vint32m8_t test___riscv_vrem_vx_i32m8_mu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i32m8_mu(mask,merge,op1,op2,32);
+}
+
+
+vint64m1_t test___riscv_vrem_vx_i64m1_mu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i64m1_mu(mask,merge,op1,op2,32);
+}
+
+
+vint64m2_t test___riscv_vrem_vx_i64m2_mu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i64m2_mu(mask,merge,op1,op2,32);
+}
+
+
+vint64m4_t test___riscv_vrem_vx_i64m4_mu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i64m4_mu(mask,merge,op1,op2,32);
+}
+
+
+vint64m8_t test___riscv_vrem_vx_i64m8_mu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i64m8_mu(mask,merge,op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*mu\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vrem\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 4 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vrem_vx_mu_rv64-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vrem_vx_mu_rv64-1.c
new file mode 100644
index 00000000000..60d9a23a055
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vrem_vx_mu_rv64-1.c
@@ -0,0 +1,160 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vrem_vx_i8mf8_mu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i8mf8_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint8mf4_t test___riscv_vrem_vx_i8mf4_mu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i8mf4_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint8mf2_t test___riscv_vrem_vx_i8mf2_mu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i8mf2_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint8m1_t test___riscv_vrem_vx_i8m1_mu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i8m1_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint8m2_t test___riscv_vrem_vx_i8m2_mu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i8m2_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint8m4_t test___riscv_vrem_vx_i8m4_mu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i8m4_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint8m8_t test___riscv_vrem_vx_i8m8_mu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i8m8_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint16mf4_t test___riscv_vrem_vx_i16mf4_mu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i16mf4_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint16mf2_t test___riscv_vrem_vx_i16mf2_mu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i16mf2_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint16m1_t test___riscv_vrem_vx_i16m1_mu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i16m1_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint16m2_t test___riscv_vrem_vx_i16m2_mu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i16m2_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint16m4_t test___riscv_vrem_vx_i16m4_mu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i16m4_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint16m8_t test___riscv_vrem_vx_i16m8_mu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i16m8_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint32mf2_t test___riscv_vrem_vx_i32mf2_mu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i32mf2_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint32m1_t test___riscv_vrem_vx_i32m1_mu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i32m1_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint32m2_t test___riscv_vrem_vx_i32m2_mu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i32m2_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint32m4_t test___riscv_vrem_vx_i32m4_mu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i32m4_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint32m8_t test___riscv_vrem_vx_i32m8_mu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i32m8_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint64m1_t test___riscv_vrem_vx_i64m1_mu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i64m1_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint64m2_t test___riscv_vrem_vx_i64m2_mu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i64m2_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint64m4_t test___riscv_vrem_vx_i64m4_mu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i64m4_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint64m8_t test___riscv_vrem_vx_i64m8_mu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i64m8_mu(mask,merge,op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*mu\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*mu\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*mu\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*mu\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*mu\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vrem_vx_mu_rv64-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vrem_vx_mu_rv64-2.c
new file mode 100644
index 00000000000..41eb4ee3adf
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vrem_vx_mu_rv64-2.c
@@ -0,0 +1,160 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vrem_vx_i8mf8_mu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i8mf8_mu(mask,merge,op1,op2,31);
+}
+
+
+vint8mf4_t test___riscv_vrem_vx_i8mf4_mu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i8mf4_mu(mask,merge,op1,op2,31);
+}
+
+
+vint8mf2_t test___riscv_vrem_vx_i8mf2_mu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i8mf2_mu(mask,merge,op1,op2,31);
+}
+
+
+vint8m1_t test___riscv_vrem_vx_i8m1_mu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i8m1_mu(mask,merge,op1,op2,31);
+}
+
+
+vint8m2_t test___riscv_vrem_vx_i8m2_mu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i8m2_mu(mask,merge,op1,op2,31);
+}
+
+
+vint8m4_t test___riscv_vrem_vx_i8m4_mu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i8m4_mu(mask,merge,op1,op2,31);
+}
+
+
+vint8m8_t test___riscv_vrem_vx_i8m8_mu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i8m8_mu(mask,merge,op1,op2,31);
+}
+
+
+vint16mf4_t test___riscv_vrem_vx_i16mf4_mu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i16mf4_mu(mask,merge,op1,op2,31);
+}
+
+
+vint16mf2_t test___riscv_vrem_vx_i16mf2_mu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i16mf2_mu(mask,merge,op1,op2,31);
+}
+
+
+vint16m1_t test___riscv_vrem_vx_i16m1_mu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i16m1_mu(mask,merge,op1,op2,31);
+}
+
+
+vint16m2_t test___riscv_vrem_vx_i16m2_mu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i16m2_mu(mask,merge,op1,op2,31);
+}
+
+
+vint16m4_t test___riscv_vrem_vx_i16m4_mu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i16m4_mu(mask,merge,op1,op2,31);
+}
+
+
+vint16m8_t test___riscv_vrem_vx_i16m8_mu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i16m8_mu(mask,merge,op1,op2,31);
+}
+
+
+vint32mf2_t test___riscv_vrem_vx_i32mf2_mu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i32mf2_mu(mask,merge,op1,op2,31);
+}
+
+
+vint32m1_t test___riscv_vrem_vx_i32m1_mu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i32m1_mu(mask,merge,op1,op2,31);
+}
+
+
+vint32m2_t test___riscv_vrem_vx_i32m2_mu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i32m2_mu(mask,merge,op1,op2,31);
+}
+
+
+vint32m4_t test___riscv_vrem_vx_i32m4_mu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i32m4_mu(mask,merge,op1,op2,31);
+}
+
+
+vint32m8_t test___riscv_vrem_vx_i32m8_mu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i32m8_mu(mask,merge,op1,op2,31);
+}
+
+
+vint64m1_t test___riscv_vrem_vx_i64m1_mu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i64m1_mu(mask,merge,op1,op2,31);
+}
+
+
+vint64m2_t test___riscv_vrem_vx_i64m2_mu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i64m2_mu(mask,merge,op1,op2,31);
+}
+
+
+vint64m4_t test___riscv_vrem_vx_i64m4_mu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i64m4_mu(mask,merge,op1,op2,31);
+}
+
+
+vint64m8_t test___riscv_vrem_vx_i64m8_mu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i64m8_mu(mask,merge,op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*mu\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*mu\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*mu\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*mu\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*mu\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*mu\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*mu\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*mu\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*mu\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*mu\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*mu\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*mu\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*mu\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*mu\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*mu\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*mu\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vrem_vx_mu_rv64-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vrem_vx_mu_rv64-3.c
new file mode 100644
index 00000000000..676f09a4f9f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vrem_vx_mu_rv64-3.c
@@ -0,0 +1,160 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vrem_vx_i8mf8_mu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i8mf8_mu(mask,merge,op1,op2,32);
+}
+
+
+vint8mf4_t test___riscv_vrem_vx_i8mf4_mu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i8mf4_mu(mask,merge,op1,op2,32);
+}
+
+
+vint8mf2_t test___riscv_vrem_vx_i8mf2_mu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i8mf2_mu(mask,merge,op1,op2,32);
+}
+
+
+vint8m1_t test___riscv_vrem_vx_i8m1_mu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i8m1_mu(mask,merge,op1,op2,32);
+}
+
+
+vint8m2_t test___riscv_vrem_vx_i8m2_mu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i8m2_mu(mask,merge,op1,op2,32);
+}
+
+
+vint8m4_t test___riscv_vrem_vx_i8m4_mu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i8m4_mu(mask,merge,op1,op2,32);
+}
+
+
+vint8m8_t test___riscv_vrem_vx_i8m8_mu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i8m8_mu(mask,merge,op1,op2,32);
+}
+
+
+vint16mf4_t test___riscv_vrem_vx_i16mf4_mu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i16mf4_mu(mask,merge,op1,op2,32);
+}
+
+
+vint16mf2_t test___riscv_vrem_vx_i16mf2_mu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i16mf2_mu(mask,merge,op1,op2,32);
+}
+
+
+vint16m1_t test___riscv_vrem_vx_i16m1_mu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i16m1_mu(mask,merge,op1,op2,32);
+}
+
+
+vint16m2_t test___riscv_vrem_vx_i16m2_mu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i16m2_mu(mask,merge,op1,op2,32);
+}
+
+
+vint16m4_t test___riscv_vrem_vx_i16m4_mu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i16m4_mu(mask,merge,op1,op2,32);
+}
+
+
+vint16m8_t test___riscv_vrem_vx_i16m8_mu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i16m8_mu(mask,merge,op1,op2,32);
+}
+
+
+vint32mf2_t test___riscv_vrem_vx_i32mf2_mu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i32mf2_mu(mask,merge,op1,op2,32);
+}
+
+
+vint32m1_t test___riscv_vrem_vx_i32m1_mu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i32m1_mu(mask,merge,op1,op2,32);
+}
+
+
+vint32m2_t test___riscv_vrem_vx_i32m2_mu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i32m2_mu(mask,merge,op1,op2,32);
+}
+
+
+vint32m4_t test___riscv_vrem_vx_i32m4_mu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i32m4_mu(mask,merge,op1,op2,32);
+}
+
+
+vint32m8_t test___riscv_vrem_vx_i32m8_mu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i32m8_mu(mask,merge,op1,op2,32);
+}
+
+
+vint64m1_t test___riscv_vrem_vx_i64m1_mu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i64m1_mu(mask,merge,op1,op2,32);
+}
+
+
+vint64m2_t test___riscv_vrem_vx_i64m2_mu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i64m2_mu(mask,merge,op1,op2,32);
+}
+
+
+vint64m4_t test___riscv_vrem_vx_i64m4_mu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i64m4_mu(mask,merge,op1,op2,32);
+}
+
+
+vint64m8_t test___riscv_vrem_vx_i64m8_mu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i64m8_mu(mask,merge,op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*mu\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*mu\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*mu\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*mu\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*mu\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vrem_vx_rv32-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vrem_vx_rv32-1.c
new file mode 100644
index 00000000000..10b31418d80
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vrem_vx_rv32-1.c
@@ -0,0 +1,157 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vrem_vx_i8mf8(vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i8mf8(op1,op2,vl);
+}
+
+
+vint8mf4_t test___riscv_vrem_vx_i8mf4(vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i8mf4(op1,op2,vl);
+}
+
+
+vint8mf2_t test___riscv_vrem_vx_i8mf2(vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i8mf2(op1,op2,vl);
+}
+
+
+vint8m1_t test___riscv_vrem_vx_i8m1(vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i8m1(op1,op2,vl);
+}
+
+
+vint8m2_t test___riscv_vrem_vx_i8m2(vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i8m2(op1,op2,vl);
+}
+
+
+vint8m4_t test___riscv_vrem_vx_i8m4(vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i8m4(op1,op2,vl);
+}
+
+
+vint8m8_t test___riscv_vrem_vx_i8m8(vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i8m8(op1,op2,vl);
+}
+
+
+vint16mf4_t test___riscv_vrem_vx_i16mf4(vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i16mf4(op1,op2,vl);
+}
+
+
+vint16mf2_t test___riscv_vrem_vx_i16mf2(vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i16mf2(op1,op2,vl);
+}
+
+
+vint16m1_t test___riscv_vrem_vx_i16m1(vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i16m1(op1,op2,vl);
+}
+
+
+vint16m2_t test___riscv_vrem_vx_i16m2(vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i16m2(op1,op2,vl);
+}
+
+
+vint16m4_t test___riscv_vrem_vx_i16m4(vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i16m4(op1,op2,vl);
+}
+
+
+vint16m8_t test___riscv_vrem_vx_i16m8(vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i16m8(op1,op2,vl);
+}
+
+
+vint32mf2_t test___riscv_vrem_vx_i32mf2(vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i32mf2(op1,op2,vl);
+}
+
+
+vint32m1_t test___riscv_vrem_vx_i32m1(vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i32m1(op1,op2,vl);
+}
+
+
+vint32m2_t test___riscv_vrem_vx_i32m2(vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i32m2(op1,op2,vl);
+}
+
+
+vint32m4_t test___riscv_vrem_vx_i32m4(vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i32m4(op1,op2,vl);
+}
+
+
+vint32m8_t test___riscv_vrem_vx_i32m8(vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i32m8(op1,op2,vl);
+}
+
+
+vint64m1_t test___riscv_vrem_vx_i64m1(vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i64m1(op1,op2,vl);
+}
+
+
+vint64m2_t test___riscv_vrem_vx_i64m2(vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i64m2(op1,op2,vl);
+}
+
+
+vint64m4_t test___riscv_vrem_vx_i64m4(vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i64m4(op1,op2,vl);
+}
+
+
+vint64m8_t test___riscv_vrem_vx_i64m8(vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i64m8(op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vrem\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 4 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vrem_vx_rv32-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vrem_vx_rv32-2.c
new file mode 100644
index 00000000000..9e14d2d9fcf
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vrem_vx_rv32-2.c
@@ -0,0 +1,157 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vrem_vx_i8mf8(vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i8mf8(op1,op2,31);
+}
+
+
+vint8mf4_t test___riscv_vrem_vx_i8mf4(vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i8mf4(op1,op2,31);
+}
+
+
+vint8mf2_t test___riscv_vrem_vx_i8mf2(vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i8mf2(op1,op2,31);
+}
+
+
+vint8m1_t test___riscv_vrem_vx_i8m1(vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i8m1(op1,op2,31);
+}
+
+
+vint8m2_t test___riscv_vrem_vx_i8m2(vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i8m2(op1,op2,31);
+}
+
+
+vint8m4_t test___riscv_vrem_vx_i8m4(vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i8m4(op1,op2,31);
+}
+
+
+vint8m8_t test___riscv_vrem_vx_i8m8(vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i8m8(op1,op2,31);
+}
+
+
+vint16mf4_t test___riscv_vrem_vx_i16mf4(vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i16mf4(op1,op2,31);
+}
+
+
+vint16mf2_t test___riscv_vrem_vx_i16mf2(vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i16mf2(op1,op2,31);
+}
+
+
+vint16m1_t test___riscv_vrem_vx_i16m1(vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i16m1(op1,op2,31);
+}
+
+
+vint16m2_t test___riscv_vrem_vx_i16m2(vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i16m2(op1,op2,31);
+}
+
+
+vint16m4_t test___riscv_vrem_vx_i16m4(vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i16m4(op1,op2,31);
+}
+
+
+vint16m8_t test___riscv_vrem_vx_i16m8(vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i16m8(op1,op2,31);
+}
+
+
+vint32mf2_t test___riscv_vrem_vx_i32mf2(vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i32mf2(op1,op2,31);
+}
+
+
+vint32m1_t test___riscv_vrem_vx_i32m1(vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i32m1(op1,op2,31);
+}
+
+
+vint32m2_t test___riscv_vrem_vx_i32m2(vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i32m2(op1,op2,31);
+}
+
+
+vint32m4_t test___riscv_vrem_vx_i32m4(vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i32m4(op1,op2,31);
+}
+
+
+vint32m8_t test___riscv_vrem_vx_i32m8(vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i32m8(op1,op2,31);
+}
+
+
+vint64m1_t test___riscv_vrem_vx_i64m1(vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i64m1(op1,op2,31);
+}
+
+
+vint64m2_t test___riscv_vrem_vx_i64m2(vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i64m2(op1,op2,31);
+}
+
+
+vint64m4_t test___riscv_vrem_vx_i64m4(vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i64m4(op1,op2,31);
+}
+
+
+vint64m8_t test___riscv_vrem_vx_i64m8(vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i64m8(op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vrem\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 4 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vrem_vx_rv32-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vrem_vx_rv32-3.c
new file mode 100644
index 00000000000..b786513ae2d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vrem_vx_rv32-3.c
@@ -0,0 +1,157 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vrem_vx_i8mf8(vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i8mf8(op1,op2,32);
+}
+
+
+vint8mf4_t test___riscv_vrem_vx_i8mf4(vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i8mf4(op1,op2,32);
+}
+
+
+vint8mf2_t test___riscv_vrem_vx_i8mf2(vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i8mf2(op1,op2,32);
+}
+
+
+vint8m1_t test___riscv_vrem_vx_i8m1(vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i8m1(op1,op2,32);
+}
+
+
+vint8m2_t test___riscv_vrem_vx_i8m2(vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i8m2(op1,op2,32);
+}
+
+
+vint8m4_t test___riscv_vrem_vx_i8m4(vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i8m4(op1,op2,32);
+}
+
+
+vint8m8_t test___riscv_vrem_vx_i8m8(vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i8m8(op1,op2,32);
+}
+
+
+vint16mf4_t test___riscv_vrem_vx_i16mf4(vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i16mf4(op1,op2,32);
+}
+
+
+vint16mf2_t test___riscv_vrem_vx_i16mf2(vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i16mf2(op1,op2,32);
+}
+
+
+vint16m1_t test___riscv_vrem_vx_i16m1(vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i16m1(op1,op2,32);
+}
+
+
+vint16m2_t test___riscv_vrem_vx_i16m2(vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i16m2(op1,op2,32);
+}
+
+
+vint16m4_t test___riscv_vrem_vx_i16m4(vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i16m4(op1,op2,32);
+}
+
+
+vint16m8_t test___riscv_vrem_vx_i16m8(vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i16m8(op1,op2,32);
+}
+
+
+vint32mf2_t test___riscv_vrem_vx_i32mf2(vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i32mf2(op1,op2,32);
+}
+
+
+vint32m1_t test___riscv_vrem_vx_i32m1(vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i32m1(op1,op2,32);
+}
+
+
+vint32m2_t test___riscv_vrem_vx_i32m2(vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i32m2(op1,op2,32);
+}
+
+
+vint32m4_t test___riscv_vrem_vx_i32m4(vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i32m4(op1,op2,32);
+}
+
+
+vint32m8_t test___riscv_vrem_vx_i32m8(vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i32m8(op1,op2,32);
+}
+
+
+vint64m1_t test___riscv_vrem_vx_i64m1(vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i64m1(op1,op2,32);
+}
+
+
+vint64m2_t test___riscv_vrem_vx_i64m2(vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i64m2(op1,op2,32);
+}
+
+
+vint64m4_t test___riscv_vrem_vx_i64m4(vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i64m4(op1,op2,32);
+}
+
+
+vint64m8_t test___riscv_vrem_vx_i64m8(vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i64m8(op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vrem\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 4 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vrem_vx_rv64-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vrem_vx_rv64-1.c
new file mode 100644
index 00000000000..a1bcef3edf1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vrem_vx_rv64-1.c
@@ -0,0 +1,160 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vrem_vx_i8mf8(vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i8mf8(op1,op2,vl);
+}
+
+
+vint8mf4_t test___riscv_vrem_vx_i8mf4(vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i8mf4(op1,op2,vl);
+}
+
+
+vint8mf2_t test___riscv_vrem_vx_i8mf2(vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i8mf2(op1,op2,vl);
+}
+
+
+vint8m1_t test___riscv_vrem_vx_i8m1(vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i8m1(op1,op2,vl);
+}
+
+
+vint8m2_t test___riscv_vrem_vx_i8m2(vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i8m2(op1,op2,vl);
+}
+
+
+vint8m4_t test___riscv_vrem_vx_i8m4(vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i8m4(op1,op2,vl);
+}
+
+
+vint8m8_t test___riscv_vrem_vx_i8m8(vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i8m8(op1,op2,vl);
+}
+
+
+vint16mf4_t test___riscv_vrem_vx_i16mf4(vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i16mf4(op1,op2,vl);
+}
+
+
+vint16mf2_t test___riscv_vrem_vx_i16mf2(vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i16mf2(op1,op2,vl);
+}
+
+
+vint16m1_t test___riscv_vrem_vx_i16m1(vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i16m1(op1,op2,vl);
+}
+
+
+vint16m2_t test___riscv_vrem_vx_i16m2(vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i16m2(op1,op2,vl);
+}
+
+
+vint16m4_t test___riscv_vrem_vx_i16m4(vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i16m4(op1,op2,vl);
+}
+
+
+vint16m8_t test___riscv_vrem_vx_i16m8(vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i16m8(op1,op2,vl);
+}
+
+
+vint32mf2_t test___riscv_vrem_vx_i32mf2(vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i32mf2(op1,op2,vl);
+}
+
+
+vint32m1_t test___riscv_vrem_vx_i32m1(vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i32m1(op1,op2,vl);
+}
+
+
+vint32m2_t test___riscv_vrem_vx_i32m2(vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i32m2(op1,op2,vl);
+}
+
+
+vint32m4_t test___riscv_vrem_vx_i32m4(vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i32m4(op1,op2,vl);
+}
+
+
+vint32m8_t test___riscv_vrem_vx_i32m8(vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i32m8(op1,op2,vl);
+}
+
+
+vint64m1_t test___riscv_vrem_vx_i64m1(vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i64m1(op1,op2,vl);
+}
+
+
+vint64m2_t test___riscv_vrem_vx_i64m2(vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i64m2(op1,op2,vl);
+}
+
+
+vint64m4_t test___riscv_vrem_vx_i64m4(vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i64m4(op1,op2,vl);
+}
+
+
+vint64m8_t test___riscv_vrem_vx_i64m8(vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i64m8(op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vrem_vx_rv64-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vrem_vx_rv64-2.c
new file mode 100644
index 00000000000..94258829a38
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vrem_vx_rv64-2.c
@@ -0,0 +1,160 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vrem_vx_i8mf8(vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i8mf8(op1,op2,31);
+}
+
+
+vint8mf4_t test___riscv_vrem_vx_i8mf4(vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i8mf4(op1,op2,31);
+}
+
+
+vint8mf2_t test___riscv_vrem_vx_i8mf2(vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i8mf2(op1,op2,31);
+}
+
+
+vint8m1_t test___riscv_vrem_vx_i8m1(vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i8m1(op1,op2,31);
+}
+
+
+vint8m2_t test___riscv_vrem_vx_i8m2(vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i8m2(op1,op2,31);
+}
+
+
+vint8m4_t test___riscv_vrem_vx_i8m4(vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i8m4(op1,op2,31);
+}
+
+
+vint8m8_t test___riscv_vrem_vx_i8m8(vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i8m8(op1,op2,31);
+}
+
+
+vint16mf4_t test___riscv_vrem_vx_i16mf4(vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i16mf4(op1,op2,31);
+}
+
+
+vint16mf2_t test___riscv_vrem_vx_i16mf2(vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i16mf2(op1,op2,31);
+}
+
+
+vint16m1_t test___riscv_vrem_vx_i16m1(vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i16m1(op1,op2,31);
+}
+
+
+vint16m2_t test___riscv_vrem_vx_i16m2(vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i16m2(op1,op2,31);
+}
+
+
+vint16m4_t test___riscv_vrem_vx_i16m4(vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i16m4(op1,op2,31);
+}
+
+
+vint16m8_t test___riscv_vrem_vx_i16m8(vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i16m8(op1,op2,31);
+}
+
+
+vint32mf2_t test___riscv_vrem_vx_i32mf2(vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i32mf2(op1,op2,31);
+}
+
+
+vint32m1_t test___riscv_vrem_vx_i32m1(vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i32m1(op1,op2,31);
+}
+
+
+vint32m2_t test___riscv_vrem_vx_i32m2(vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i32m2(op1,op2,31);
+}
+
+
+vint32m4_t test___riscv_vrem_vx_i32m4(vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i32m4(op1,op2,31);
+}
+
+
+vint32m8_t test___riscv_vrem_vx_i32m8(vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i32m8(op1,op2,31);
+}
+
+
+vint64m1_t test___riscv_vrem_vx_i64m1(vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i64m1(op1,op2,31);
+}
+
+
+vint64m2_t test___riscv_vrem_vx_i64m2(vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i64m2(op1,op2,31);
+}
+
+
+vint64m4_t test___riscv_vrem_vx_i64m4(vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i64m4(op1,op2,31);
+}
+
+
+vint64m8_t test___riscv_vrem_vx_i64m8(vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i64m8(op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vrem_vx_rv64-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vrem_vx_rv64-3.c
new file mode 100644
index 00000000000..cb49337a312
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vrem_vx_rv64-3.c
@@ -0,0 +1,160 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vrem_vx_i8mf8(vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i8mf8(op1,op2,32);
+}
+
+
+vint8mf4_t test___riscv_vrem_vx_i8mf4(vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i8mf4(op1,op2,32);
+}
+
+
+vint8mf2_t test___riscv_vrem_vx_i8mf2(vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i8mf2(op1,op2,32);
+}
+
+
+vint8m1_t test___riscv_vrem_vx_i8m1(vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i8m1(op1,op2,32);
+}
+
+
+vint8m2_t test___riscv_vrem_vx_i8m2(vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i8m2(op1,op2,32);
+}
+
+
+vint8m4_t test___riscv_vrem_vx_i8m4(vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i8m4(op1,op2,32);
+}
+
+
+vint8m8_t test___riscv_vrem_vx_i8m8(vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i8m8(op1,op2,32);
+}
+
+
+vint16mf4_t test___riscv_vrem_vx_i16mf4(vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i16mf4(op1,op2,32);
+}
+
+
+vint16mf2_t test___riscv_vrem_vx_i16mf2(vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i16mf2(op1,op2,32);
+}
+
+
+vint16m1_t test___riscv_vrem_vx_i16m1(vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i16m1(op1,op2,32);
+}
+
+
+vint16m2_t test___riscv_vrem_vx_i16m2(vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i16m2(op1,op2,32);
+}
+
+
+vint16m4_t test___riscv_vrem_vx_i16m4(vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i16m4(op1,op2,32);
+}
+
+
+vint16m8_t test___riscv_vrem_vx_i16m8(vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i16m8(op1,op2,32);
+}
+
+
+vint32mf2_t test___riscv_vrem_vx_i32mf2(vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i32mf2(op1,op2,32);
+}
+
+
+vint32m1_t test___riscv_vrem_vx_i32m1(vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i32m1(op1,op2,32);
+}
+
+
+vint32m2_t test___riscv_vrem_vx_i32m2(vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i32m2(op1,op2,32);
+}
+
+
+vint32m4_t test___riscv_vrem_vx_i32m4(vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i32m4(op1,op2,32);
+}
+
+
+vint32m8_t test___riscv_vrem_vx_i32m8(vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i32m8(op1,op2,32);
+}
+
+
+vint64m1_t test___riscv_vrem_vx_i64m1(vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i64m1(op1,op2,32);
+}
+
+
+vint64m2_t test___riscv_vrem_vx_i64m2(vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i64m2(op1,op2,32);
+}
+
+
+vint64m4_t test___riscv_vrem_vx_i64m4(vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i64m4(op1,op2,32);
+}
+
+
+vint64m8_t test___riscv_vrem_vx_i64m8(vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i64m8(op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vrem_vx_tu_rv32-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vrem_vx_tu_rv32-1.c
new file mode 100644
index 00000000000..b38d5f5f18f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vrem_vx_tu_rv32-1.c
@@ -0,0 +1,157 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vrem_vx_i8mf8_tu(vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i8mf8_tu(merge,op1,op2,vl);
+}
+
+
+vint8mf4_t test___riscv_vrem_vx_i8mf4_tu(vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i8mf4_tu(merge,op1,op2,vl);
+}
+
+
+vint8mf2_t test___riscv_vrem_vx_i8mf2_tu(vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i8mf2_tu(merge,op1,op2,vl);
+}
+
+
+vint8m1_t test___riscv_vrem_vx_i8m1_tu(vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i8m1_tu(merge,op1,op2,vl);
+}
+
+
+vint8m2_t test___riscv_vrem_vx_i8m2_tu(vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i8m2_tu(merge,op1,op2,vl);
+}
+
+
+vint8m4_t test___riscv_vrem_vx_i8m4_tu(vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i8m4_tu(merge,op1,op2,vl);
+}
+
+
+vint8m8_t test___riscv_vrem_vx_i8m8_tu(vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i8m8_tu(merge,op1,op2,vl);
+}
+
+
+vint16mf4_t test___riscv_vrem_vx_i16mf4_tu(vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i16mf4_tu(merge,op1,op2,vl);
+}
+
+
+vint16mf2_t test___riscv_vrem_vx_i16mf2_tu(vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i16mf2_tu(merge,op1,op2,vl);
+}
+
+
+vint16m1_t test___riscv_vrem_vx_i16m1_tu(vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i16m1_tu(merge,op1,op2,vl);
+}
+
+
+vint16m2_t test___riscv_vrem_vx_i16m2_tu(vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i16m2_tu(merge,op1,op2,vl);
+}
+
+
+vint16m4_t test___riscv_vrem_vx_i16m4_tu(vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i16m4_tu(merge,op1,op2,vl);
+}
+
+
+vint16m8_t test___riscv_vrem_vx_i16m8_tu(vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i16m8_tu(merge,op1,op2,vl);
+}
+
+
+vint32mf2_t test___riscv_vrem_vx_i32mf2_tu(vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i32mf2_tu(merge,op1,op2,vl);
+}
+
+
+vint32m1_t test___riscv_vrem_vx_i32m1_tu(vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i32m1_tu(merge,op1,op2,vl);
+}
+
+
+vint32m2_t test___riscv_vrem_vx_i32m2_tu(vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i32m2_tu(merge,op1,op2,vl);
+}
+
+
+vint32m4_t test___riscv_vrem_vx_i32m4_tu(vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i32m4_tu(merge,op1,op2,vl);
+}
+
+
+vint32m8_t test___riscv_vrem_vx_i32m8_tu(vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i32m8_tu(merge,op1,op2,vl);
+}
+
+
+vint64m1_t test___riscv_vrem_vx_i64m1_tu(vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i64m1_tu(merge,op1,op2,vl);
+}
+
+
+vint64m2_t test___riscv_vrem_vx_i64m2_tu(vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i64m2_tu(merge,op1,op2,vl);
+}
+
+
+vint64m4_t test___riscv_vrem_vx_i64m4_tu(vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i64m4_tu(merge,op1,op2,vl);
+}
+
+
+vint64m8_t test___riscv_vrem_vx_i64m8_tu(vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i64m8_tu(merge,op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vrem\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 4 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vrem_vx_tu_rv32-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vrem_vx_tu_rv32-2.c
new file mode 100644
index 00000000000..5e11fe2a4dd
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vrem_vx_tu_rv32-2.c
@@ -0,0 +1,157 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vrem_vx_i8mf8_tu(vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i8mf8_tu(merge,op1,op2,31);
+}
+
+
+vint8mf4_t test___riscv_vrem_vx_i8mf4_tu(vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i8mf4_tu(merge,op1,op2,31);
+}
+
+
+vint8mf2_t test___riscv_vrem_vx_i8mf2_tu(vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i8mf2_tu(merge,op1,op2,31);
+}
+
+
+vint8m1_t test___riscv_vrem_vx_i8m1_tu(vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i8m1_tu(merge,op1,op2,31);
+}
+
+
+vint8m2_t test___riscv_vrem_vx_i8m2_tu(vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i8m2_tu(merge,op1,op2,31);
+}
+
+
+vint8m4_t test___riscv_vrem_vx_i8m4_tu(vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i8m4_tu(merge,op1,op2,31);
+}
+
+
+vint8m8_t test___riscv_vrem_vx_i8m8_tu(vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i8m8_tu(merge,op1,op2,31);
+}
+
+
+vint16mf4_t test___riscv_vrem_vx_i16mf4_tu(vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i16mf4_tu(merge,op1,op2,31);
+}
+
+
+vint16mf2_t test___riscv_vrem_vx_i16mf2_tu(vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i16mf2_tu(merge,op1,op2,31);
+}
+
+
+vint16m1_t test___riscv_vrem_vx_i16m1_tu(vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i16m1_tu(merge,op1,op2,31);
+}
+
+
+vint16m2_t test___riscv_vrem_vx_i16m2_tu(vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i16m2_tu(merge,op1,op2,31);
+}
+
+
+vint16m4_t test___riscv_vrem_vx_i16m4_tu(vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i16m4_tu(merge,op1,op2,31);
+}
+
+
+vint16m8_t test___riscv_vrem_vx_i16m8_tu(vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i16m8_tu(merge,op1,op2,31);
+}
+
+
+vint32mf2_t test___riscv_vrem_vx_i32mf2_tu(vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i32mf2_tu(merge,op1,op2,31);
+}
+
+
+vint32m1_t test___riscv_vrem_vx_i32m1_tu(vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i32m1_tu(merge,op1,op2,31);
+}
+
+
+vint32m2_t test___riscv_vrem_vx_i32m2_tu(vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i32m2_tu(merge,op1,op2,31);
+}
+
+
+vint32m4_t test___riscv_vrem_vx_i32m4_tu(vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i32m4_tu(merge,op1,op2,31);
+}
+
+
+vint32m8_t test___riscv_vrem_vx_i32m8_tu(vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i32m8_tu(merge,op1,op2,31);
+}
+
+
+vint64m1_t test___riscv_vrem_vx_i64m1_tu(vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i64m1_tu(merge,op1,op2,31);
+}
+
+
+vint64m2_t test___riscv_vrem_vx_i64m2_tu(vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i64m2_tu(merge,op1,op2,31);
+}
+
+
+vint64m4_t test___riscv_vrem_vx_i64m4_tu(vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i64m4_tu(merge,op1,op2,31);
+}
+
+
+vint64m8_t test___riscv_vrem_vx_i64m8_tu(vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i64m8_tu(merge,op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vrem\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 4 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vrem_vx_tu_rv32-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vrem_vx_tu_rv32-3.c
new file mode 100644
index 00000000000..c4c7f43d3fb
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vrem_vx_tu_rv32-3.c
@@ -0,0 +1,157 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vrem_vx_i8mf8_tu(vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i8mf8_tu(merge,op1,op2,32);
+}
+
+
+vint8mf4_t test___riscv_vrem_vx_i8mf4_tu(vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i8mf4_tu(merge,op1,op2,32);
+}
+
+
+vint8mf2_t test___riscv_vrem_vx_i8mf2_tu(vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i8mf2_tu(merge,op1,op2,32);
+}
+
+
+vint8m1_t test___riscv_vrem_vx_i8m1_tu(vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i8m1_tu(merge,op1,op2,32);
+}
+
+
+vint8m2_t test___riscv_vrem_vx_i8m2_tu(vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i8m2_tu(merge,op1,op2,32);
+}
+
+
+vint8m4_t test___riscv_vrem_vx_i8m4_tu(vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i8m4_tu(merge,op1,op2,32);
+}
+
+
+vint8m8_t test___riscv_vrem_vx_i8m8_tu(vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i8m8_tu(merge,op1,op2,32);
+}
+
+
+vint16mf4_t test___riscv_vrem_vx_i16mf4_tu(vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i16mf4_tu(merge,op1,op2,32);
+}
+
+
+vint16mf2_t test___riscv_vrem_vx_i16mf2_tu(vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i16mf2_tu(merge,op1,op2,32);
+}
+
+
+vint16m1_t test___riscv_vrem_vx_i16m1_tu(vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i16m1_tu(merge,op1,op2,32);
+}
+
+
+vint16m2_t test___riscv_vrem_vx_i16m2_tu(vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i16m2_tu(merge,op1,op2,32);
+}
+
+
+vint16m4_t test___riscv_vrem_vx_i16m4_tu(vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i16m4_tu(merge,op1,op2,32);
+}
+
+
+vint16m8_t test___riscv_vrem_vx_i16m8_tu(vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i16m8_tu(merge,op1,op2,32);
+}
+
+
+vint32mf2_t test___riscv_vrem_vx_i32mf2_tu(vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i32mf2_tu(merge,op1,op2,32);
+}
+
+
+vint32m1_t test___riscv_vrem_vx_i32m1_tu(vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i32m1_tu(merge,op1,op2,32);
+}
+
+
+vint32m2_t test___riscv_vrem_vx_i32m2_tu(vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i32m2_tu(merge,op1,op2,32);
+}
+
+
+vint32m4_t test___riscv_vrem_vx_i32m4_tu(vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i32m4_tu(merge,op1,op2,32);
+}
+
+
+vint32m8_t test___riscv_vrem_vx_i32m8_tu(vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i32m8_tu(merge,op1,op2,32);
+}
+
+
+vint64m1_t test___riscv_vrem_vx_i64m1_tu(vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i64m1_tu(merge,op1,op2,32);
+}
+
+
+vint64m2_t test___riscv_vrem_vx_i64m2_tu(vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i64m2_tu(merge,op1,op2,32);
+}
+
+
+vint64m4_t test___riscv_vrem_vx_i64m4_tu(vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i64m4_tu(merge,op1,op2,32);
+}
+
+
+vint64m8_t test___riscv_vrem_vx_i64m8_tu(vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i64m8_tu(merge,op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vrem\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 4 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vrem_vx_tu_rv64-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vrem_vx_tu_rv64-1.c
new file mode 100644
index 00000000000..8374807e968
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vrem_vx_tu_rv64-1.c
@@ -0,0 +1,160 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vrem_vx_i8mf8_tu(vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i8mf8_tu(merge,op1,op2,vl);
+}
+
+
+vint8mf4_t test___riscv_vrem_vx_i8mf4_tu(vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i8mf4_tu(merge,op1,op2,vl);
+}
+
+
+vint8mf2_t test___riscv_vrem_vx_i8mf2_tu(vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i8mf2_tu(merge,op1,op2,vl);
+}
+
+
+vint8m1_t test___riscv_vrem_vx_i8m1_tu(vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i8m1_tu(merge,op1,op2,vl);
+}
+
+
+vint8m2_t test___riscv_vrem_vx_i8m2_tu(vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i8m2_tu(merge,op1,op2,vl);
+}
+
+
+vint8m4_t test___riscv_vrem_vx_i8m4_tu(vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i8m4_tu(merge,op1,op2,vl);
+}
+
+
+vint8m8_t test___riscv_vrem_vx_i8m8_tu(vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i8m8_tu(merge,op1,op2,vl);
+}
+
+
+vint16mf4_t test___riscv_vrem_vx_i16mf4_tu(vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i16mf4_tu(merge,op1,op2,vl);
+}
+
+
+vint16mf2_t test___riscv_vrem_vx_i16mf2_tu(vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i16mf2_tu(merge,op1,op2,vl);
+}
+
+
+vint16m1_t test___riscv_vrem_vx_i16m1_tu(vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i16m1_tu(merge,op1,op2,vl);
+}
+
+
+vint16m2_t test___riscv_vrem_vx_i16m2_tu(vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i16m2_tu(merge,op1,op2,vl);
+}
+
+
+vint16m4_t test___riscv_vrem_vx_i16m4_tu(vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i16m4_tu(merge,op1,op2,vl);
+}
+
+
+vint16m8_t test___riscv_vrem_vx_i16m8_tu(vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i16m8_tu(merge,op1,op2,vl);
+}
+
+
+vint32mf2_t test___riscv_vrem_vx_i32mf2_tu(vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i32mf2_tu(merge,op1,op2,vl);
+}
+
+
+vint32m1_t test___riscv_vrem_vx_i32m1_tu(vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i32m1_tu(merge,op1,op2,vl);
+}
+
+
+vint32m2_t test___riscv_vrem_vx_i32m2_tu(vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i32m2_tu(merge,op1,op2,vl);
+}
+
+
+vint32m4_t test___riscv_vrem_vx_i32m4_tu(vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i32m4_tu(merge,op1,op2,vl);
+}
+
+
+vint32m8_t test___riscv_vrem_vx_i32m8_tu(vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i32m8_tu(merge,op1,op2,vl);
+}
+
+
+vint64m1_t test___riscv_vrem_vx_i64m1_tu(vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i64m1_tu(merge,op1,op2,vl);
+}
+
+
+vint64m2_t test___riscv_vrem_vx_i64m2_tu(vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i64m2_tu(merge,op1,op2,vl);
+}
+
+
+vint64m4_t test___riscv_vrem_vx_i64m4_tu(vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i64m4_tu(merge,op1,op2,vl);
+}
+
+
+vint64m8_t test___riscv_vrem_vx_i64m8_tu(vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i64m8_tu(merge,op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vrem_vx_tu_rv64-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vrem_vx_tu_rv64-2.c
new file mode 100644
index 00000000000..5e9fac55df1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vrem_vx_tu_rv64-2.c
@@ -0,0 +1,160 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vrem_vx_i8mf8_tu(vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i8mf8_tu(merge,op1,op2,31);
+}
+
+
+vint8mf4_t test___riscv_vrem_vx_i8mf4_tu(vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i8mf4_tu(merge,op1,op2,31);
+}
+
+
+vint8mf2_t test___riscv_vrem_vx_i8mf2_tu(vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i8mf2_tu(merge,op1,op2,31);
+}
+
+
+vint8m1_t test___riscv_vrem_vx_i8m1_tu(vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i8m1_tu(merge,op1,op2,31);
+}
+
+
+vint8m2_t test___riscv_vrem_vx_i8m2_tu(vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i8m2_tu(merge,op1,op2,31);
+}
+
+
+vint8m4_t test___riscv_vrem_vx_i8m4_tu(vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i8m4_tu(merge,op1,op2,31);
+}
+
+
+vint8m8_t test___riscv_vrem_vx_i8m8_tu(vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i8m8_tu(merge,op1,op2,31);
+}
+
+
+vint16mf4_t test___riscv_vrem_vx_i16mf4_tu(vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i16mf4_tu(merge,op1,op2,31);
+}
+
+
+vint16mf2_t test___riscv_vrem_vx_i16mf2_tu(vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i16mf2_tu(merge,op1,op2,31);
+}
+
+
+vint16m1_t test___riscv_vrem_vx_i16m1_tu(vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i16m1_tu(merge,op1,op2,31);
+}
+
+
+vint16m2_t test___riscv_vrem_vx_i16m2_tu(vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i16m2_tu(merge,op1,op2,31);
+}
+
+
+vint16m4_t test___riscv_vrem_vx_i16m4_tu(vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i16m4_tu(merge,op1,op2,31);
+}
+
+
+vint16m8_t test___riscv_vrem_vx_i16m8_tu(vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i16m8_tu(merge,op1,op2,31);
+}
+
+
+vint32mf2_t test___riscv_vrem_vx_i32mf2_tu(vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i32mf2_tu(merge,op1,op2,31);
+}
+
+
+vint32m1_t test___riscv_vrem_vx_i32m1_tu(vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i32m1_tu(merge,op1,op2,31);
+}
+
+
+vint32m2_t test___riscv_vrem_vx_i32m2_tu(vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i32m2_tu(merge,op1,op2,31);
+}
+
+
+vint32m4_t test___riscv_vrem_vx_i32m4_tu(vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i32m4_tu(merge,op1,op2,31);
+}
+
+
+vint32m8_t test___riscv_vrem_vx_i32m8_tu(vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i32m8_tu(merge,op1,op2,31);
+}
+
+
+vint64m1_t test___riscv_vrem_vx_i64m1_tu(vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i64m1_tu(merge,op1,op2,31);
+}
+
+
+vint64m2_t test___riscv_vrem_vx_i64m2_tu(vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i64m2_tu(merge,op1,op2,31);
+}
+
+
+vint64m4_t test___riscv_vrem_vx_i64m4_tu(vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i64m4_tu(merge,op1,op2,31);
+}
+
+
+vint64m8_t test___riscv_vrem_vx_i64m8_tu(vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i64m8_tu(merge,op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vrem_vx_tu_rv64-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vrem_vx_tu_rv64-3.c
new file mode 100644
index 00000000000..7c18ee6e4d4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vrem_vx_tu_rv64-3.c
@@ -0,0 +1,160 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vrem_vx_i8mf8_tu(vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i8mf8_tu(merge,op1,op2,32);
+}
+
+
+vint8mf4_t test___riscv_vrem_vx_i8mf4_tu(vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i8mf4_tu(merge,op1,op2,32);
+}
+
+
+vint8mf2_t test___riscv_vrem_vx_i8mf2_tu(vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i8mf2_tu(merge,op1,op2,32);
+}
+
+
+vint8m1_t test___riscv_vrem_vx_i8m1_tu(vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i8m1_tu(merge,op1,op2,32);
+}
+
+
+vint8m2_t test___riscv_vrem_vx_i8m2_tu(vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i8m2_tu(merge,op1,op2,32);
+}
+
+
+vint8m4_t test___riscv_vrem_vx_i8m4_tu(vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i8m4_tu(merge,op1,op2,32);
+}
+
+
+vint8m8_t test___riscv_vrem_vx_i8m8_tu(vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i8m8_tu(merge,op1,op2,32);
+}
+
+
+vint16mf4_t test___riscv_vrem_vx_i16mf4_tu(vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i16mf4_tu(merge,op1,op2,32);
+}
+
+
+vint16mf2_t test___riscv_vrem_vx_i16mf2_tu(vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i16mf2_tu(merge,op1,op2,32);
+}
+
+
+vint16m1_t test___riscv_vrem_vx_i16m1_tu(vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i16m1_tu(merge,op1,op2,32);
+}
+
+
+vint16m2_t test___riscv_vrem_vx_i16m2_tu(vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i16m2_tu(merge,op1,op2,32);
+}
+
+
+vint16m4_t test___riscv_vrem_vx_i16m4_tu(vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i16m4_tu(merge,op1,op2,32);
+}
+
+
+vint16m8_t test___riscv_vrem_vx_i16m8_tu(vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i16m8_tu(merge,op1,op2,32);
+}
+
+
+vint32mf2_t test___riscv_vrem_vx_i32mf2_tu(vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i32mf2_tu(merge,op1,op2,32);
+}
+
+
+vint32m1_t test___riscv_vrem_vx_i32m1_tu(vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i32m1_tu(merge,op1,op2,32);
+}
+
+
+vint32m2_t test___riscv_vrem_vx_i32m2_tu(vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i32m2_tu(merge,op1,op2,32);
+}
+
+
+vint32m4_t test___riscv_vrem_vx_i32m4_tu(vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i32m4_tu(merge,op1,op2,32);
+}
+
+
+vint32m8_t test___riscv_vrem_vx_i32m8_tu(vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i32m8_tu(merge,op1,op2,32);
+}
+
+
+vint64m1_t test___riscv_vrem_vx_i64m1_tu(vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i64m1_tu(merge,op1,op2,32);
+}
+
+
+vint64m2_t test___riscv_vrem_vx_i64m2_tu(vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i64m2_tu(merge,op1,op2,32);
+}
+
+
+vint64m4_t test___riscv_vrem_vx_i64m4_tu(vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i64m4_tu(merge,op1,op2,32);
+}
+
+
+vint64m8_t test___riscv_vrem_vx_i64m8_tu(vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i64m8_tu(merge,op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vrem_vx_tum_rv32-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vrem_vx_tum_rv32-1.c
new file mode 100644
index 00000000000..6ebdf11b07b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vrem_vx_tum_rv32-1.c
@@ -0,0 +1,157 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vrem_vx_i8mf8_tum(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i8mf8_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint8mf4_t test___riscv_vrem_vx_i8mf4_tum(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i8mf4_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint8mf2_t test___riscv_vrem_vx_i8mf2_tum(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i8mf2_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint8m1_t test___riscv_vrem_vx_i8m1_tum(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i8m1_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint8m2_t test___riscv_vrem_vx_i8m2_tum(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i8m2_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint8m4_t test___riscv_vrem_vx_i8m4_tum(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i8m4_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint8m8_t test___riscv_vrem_vx_i8m8_tum(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i8m8_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint16mf4_t test___riscv_vrem_vx_i16mf4_tum(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i16mf4_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint16mf2_t test___riscv_vrem_vx_i16mf2_tum(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i16mf2_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint16m1_t test___riscv_vrem_vx_i16m1_tum(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i16m1_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint16m2_t test___riscv_vrem_vx_i16m2_tum(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i16m2_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint16m4_t test___riscv_vrem_vx_i16m4_tum(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i16m4_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint16m8_t test___riscv_vrem_vx_i16m8_tum(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i16m8_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint32mf2_t test___riscv_vrem_vx_i32mf2_tum(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i32mf2_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint32m1_t test___riscv_vrem_vx_i32m1_tum(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i32m1_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint32m2_t test___riscv_vrem_vx_i32m2_tum(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i32m2_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint32m4_t test___riscv_vrem_vx_i32m4_tum(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i32m4_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint32m8_t test___riscv_vrem_vx_i32m8_tum(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i32m8_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint64m1_t test___riscv_vrem_vx_i64m1_tum(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i64m1_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint64m2_t test___riscv_vrem_vx_i64m2_tum(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i64m2_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint64m4_t test___riscv_vrem_vx_i64m4_tum(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i64m4_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint64m8_t test___riscv_vrem_vx_i64m8_tum(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i64m8_tum(mask,merge,op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vrem\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 4 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vrem_vx_tum_rv32-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vrem_vx_tum_rv32-2.c
new file mode 100644
index 00000000000..e9ac52c1a9f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vrem_vx_tum_rv32-2.c
@@ -0,0 +1,157 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vrem_vx_i8mf8_tum(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i8mf8_tum(mask,merge,op1,op2,31);
+}
+
+
+vint8mf4_t test___riscv_vrem_vx_i8mf4_tum(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i8mf4_tum(mask,merge,op1,op2,31);
+}
+
+
+vint8mf2_t test___riscv_vrem_vx_i8mf2_tum(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i8mf2_tum(mask,merge,op1,op2,31);
+}
+
+
+vint8m1_t test___riscv_vrem_vx_i8m1_tum(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i8m1_tum(mask,merge,op1,op2,31);
+}
+
+
+vint8m2_t test___riscv_vrem_vx_i8m2_tum(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i8m2_tum(mask,merge,op1,op2,31);
+}
+
+
+vint8m4_t test___riscv_vrem_vx_i8m4_tum(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i8m4_tum(mask,merge,op1,op2,31);
+}
+
+
+vint8m8_t test___riscv_vrem_vx_i8m8_tum(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i8m8_tum(mask,merge,op1,op2,31);
+}
+
+
+vint16mf4_t test___riscv_vrem_vx_i16mf4_tum(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i16mf4_tum(mask,merge,op1,op2,31);
+}
+
+
+vint16mf2_t test___riscv_vrem_vx_i16mf2_tum(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i16mf2_tum(mask,merge,op1,op2,31);
+}
+
+
+vint16m1_t test___riscv_vrem_vx_i16m1_tum(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i16m1_tum(mask,merge,op1,op2,31);
+}
+
+
+vint16m2_t test___riscv_vrem_vx_i16m2_tum(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i16m2_tum(mask,merge,op1,op2,31);
+}
+
+
+vint16m4_t test___riscv_vrem_vx_i16m4_tum(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i16m4_tum(mask,merge,op1,op2,31);
+}
+
+
+vint16m8_t test___riscv_vrem_vx_i16m8_tum(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i16m8_tum(mask,merge,op1,op2,31);
+}
+
+
+vint32mf2_t test___riscv_vrem_vx_i32mf2_tum(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i32mf2_tum(mask,merge,op1,op2,31);
+}
+
+
+vint32m1_t test___riscv_vrem_vx_i32m1_tum(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i32m1_tum(mask,merge,op1,op2,31);
+}
+
+
+vint32m2_t test___riscv_vrem_vx_i32m2_tum(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i32m2_tum(mask,merge,op1,op2,31);
+}
+
+
+vint32m4_t test___riscv_vrem_vx_i32m4_tum(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i32m4_tum(mask,merge,op1,op2,31);
+}
+
+
+vint32m8_t test___riscv_vrem_vx_i32m8_tum(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i32m8_tum(mask,merge,op1,op2,31);
+}
+
+
+vint64m1_t test___riscv_vrem_vx_i64m1_tum(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i64m1_tum(mask,merge,op1,op2,31);
+}
+
+
+vint64m2_t test___riscv_vrem_vx_i64m2_tum(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i64m2_tum(mask,merge,op1,op2,31);
+}
+
+
+vint64m4_t test___riscv_vrem_vx_i64m4_tum(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i64m4_tum(mask,merge,op1,op2,31);
+}
+
+
+vint64m8_t test___riscv_vrem_vx_i64m8_tum(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i64m8_tum(mask,merge,op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vrem\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 4 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vrem_vx_tum_rv32-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vrem_vx_tum_rv32-3.c
new file mode 100644
index 00000000000..6e600503dcc
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vrem_vx_tum_rv32-3.c
@@ -0,0 +1,157 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vrem_vx_i8mf8_tum(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i8mf8_tum(mask,merge,op1,op2,32);
+}
+
+
+vint8mf4_t test___riscv_vrem_vx_i8mf4_tum(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i8mf4_tum(mask,merge,op1,op2,32);
+}
+
+
+vint8mf2_t test___riscv_vrem_vx_i8mf2_tum(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i8mf2_tum(mask,merge,op1,op2,32);
+}
+
+
+vint8m1_t test___riscv_vrem_vx_i8m1_tum(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i8m1_tum(mask,merge,op1,op2,32);
+}
+
+
+vint8m2_t test___riscv_vrem_vx_i8m2_tum(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i8m2_tum(mask,merge,op1,op2,32);
+}
+
+
+vint8m4_t test___riscv_vrem_vx_i8m4_tum(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i8m4_tum(mask,merge,op1,op2,32);
+}
+
+
+vint8m8_t test___riscv_vrem_vx_i8m8_tum(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i8m8_tum(mask,merge,op1,op2,32);
+}
+
+
+vint16mf4_t test___riscv_vrem_vx_i16mf4_tum(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i16mf4_tum(mask,merge,op1,op2,32);
+}
+
+
+vint16mf2_t test___riscv_vrem_vx_i16mf2_tum(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i16mf2_tum(mask,merge,op1,op2,32);
+}
+
+
+vint16m1_t test___riscv_vrem_vx_i16m1_tum(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i16m1_tum(mask,merge,op1,op2,32);
+}
+
+
+vint16m2_t test___riscv_vrem_vx_i16m2_tum(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i16m2_tum(mask,merge,op1,op2,32);
+}
+
+
+vint16m4_t test___riscv_vrem_vx_i16m4_tum(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i16m4_tum(mask,merge,op1,op2,32);
+}
+
+
+vint16m8_t test___riscv_vrem_vx_i16m8_tum(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i16m8_tum(mask,merge,op1,op2,32);
+}
+
+
+vint32mf2_t test___riscv_vrem_vx_i32mf2_tum(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i32mf2_tum(mask,merge,op1,op2,32);
+}
+
+
+vint32m1_t test___riscv_vrem_vx_i32m1_tum(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i32m1_tum(mask,merge,op1,op2,32);
+}
+
+
+vint32m2_t test___riscv_vrem_vx_i32m2_tum(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i32m2_tum(mask,merge,op1,op2,32);
+}
+
+
+vint32m4_t test___riscv_vrem_vx_i32m4_tum(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i32m4_tum(mask,merge,op1,op2,32);
+}
+
+
+vint32m8_t test___riscv_vrem_vx_i32m8_tum(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i32m8_tum(mask,merge,op1,op2,32);
+}
+
+
+vint64m1_t test___riscv_vrem_vx_i64m1_tum(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i64m1_tum(mask,merge,op1,op2,32);
+}
+
+
+vint64m2_t test___riscv_vrem_vx_i64m2_tum(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i64m2_tum(mask,merge,op1,op2,32);
+}
+
+
+vint64m4_t test___riscv_vrem_vx_i64m4_tum(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i64m4_tum(mask,merge,op1,op2,32);
+}
+
+
+vint64m8_t test___riscv_vrem_vx_i64m8_tum(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i64m8_tum(mask,merge,op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vrem\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 4 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vrem_vx_tum_rv64-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vrem_vx_tum_rv64-1.c
new file mode 100644
index 00000000000..c406d57dcd6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vrem_vx_tum_rv64-1.c
@@ -0,0 +1,160 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vrem_vx_i8mf8_tum(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i8mf8_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint8mf4_t test___riscv_vrem_vx_i8mf4_tum(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i8mf4_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint8mf2_t test___riscv_vrem_vx_i8mf2_tum(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i8mf2_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint8m1_t test___riscv_vrem_vx_i8m1_tum(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i8m1_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint8m2_t test___riscv_vrem_vx_i8m2_tum(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i8m2_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint8m4_t test___riscv_vrem_vx_i8m4_tum(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i8m4_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint8m8_t test___riscv_vrem_vx_i8m8_tum(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i8m8_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint16mf4_t test___riscv_vrem_vx_i16mf4_tum(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i16mf4_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint16mf2_t test___riscv_vrem_vx_i16mf2_tum(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i16mf2_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint16m1_t test___riscv_vrem_vx_i16m1_tum(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i16m1_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint16m2_t test___riscv_vrem_vx_i16m2_tum(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i16m2_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint16m4_t test___riscv_vrem_vx_i16m4_tum(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i16m4_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint16m8_t test___riscv_vrem_vx_i16m8_tum(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i16m8_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint32mf2_t test___riscv_vrem_vx_i32mf2_tum(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i32mf2_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint32m1_t test___riscv_vrem_vx_i32m1_tum(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i32m1_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint32m2_t test___riscv_vrem_vx_i32m2_tum(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i32m2_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint32m4_t test___riscv_vrem_vx_i32m4_tum(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i32m4_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint32m8_t test___riscv_vrem_vx_i32m8_tum(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i32m8_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint64m1_t test___riscv_vrem_vx_i64m1_tum(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i64m1_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint64m2_t test___riscv_vrem_vx_i64m2_tum(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i64m2_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint64m4_t test___riscv_vrem_vx_i64m4_tum(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i64m4_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint64m8_t test___riscv_vrem_vx_i64m8_tum(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i64m8_tum(mask,merge,op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vrem_vx_tum_rv64-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vrem_vx_tum_rv64-2.c
new file mode 100644
index 00000000000..495e17b3fe5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vrem_vx_tum_rv64-2.c
@@ -0,0 +1,160 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vrem_vx_i8mf8_tum(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i8mf8_tum(mask,merge,op1,op2,31);
+}
+
+
+vint8mf4_t test___riscv_vrem_vx_i8mf4_tum(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i8mf4_tum(mask,merge,op1,op2,31);
+}
+
+
+vint8mf2_t test___riscv_vrem_vx_i8mf2_tum(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i8mf2_tum(mask,merge,op1,op2,31);
+}
+
+
+vint8m1_t test___riscv_vrem_vx_i8m1_tum(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i8m1_tum(mask,merge,op1,op2,31);
+}
+
+
+vint8m2_t test___riscv_vrem_vx_i8m2_tum(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i8m2_tum(mask,merge,op1,op2,31);
+}
+
+
+vint8m4_t test___riscv_vrem_vx_i8m4_tum(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i8m4_tum(mask,merge,op1,op2,31);
+}
+
+
+vint8m8_t test___riscv_vrem_vx_i8m8_tum(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i8m8_tum(mask,merge,op1,op2,31);
+}
+
+
+vint16mf4_t test___riscv_vrem_vx_i16mf4_tum(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i16mf4_tum(mask,merge,op1,op2,31);
+}
+
+
+vint16mf2_t test___riscv_vrem_vx_i16mf2_tum(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i16mf2_tum(mask,merge,op1,op2,31);
+}
+
+
+vint16m1_t test___riscv_vrem_vx_i16m1_tum(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i16m1_tum(mask,merge,op1,op2,31);
+}
+
+
+vint16m2_t test___riscv_vrem_vx_i16m2_tum(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i16m2_tum(mask,merge,op1,op2,31);
+}
+
+
+vint16m4_t test___riscv_vrem_vx_i16m4_tum(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i16m4_tum(mask,merge,op1,op2,31);
+}
+
+
+vint16m8_t test___riscv_vrem_vx_i16m8_tum(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i16m8_tum(mask,merge,op1,op2,31);
+}
+
+
+vint32mf2_t test___riscv_vrem_vx_i32mf2_tum(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i32mf2_tum(mask,merge,op1,op2,31);
+}
+
+
+vint32m1_t test___riscv_vrem_vx_i32m1_tum(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i32m1_tum(mask,merge,op1,op2,31);
+}
+
+
+vint32m2_t test___riscv_vrem_vx_i32m2_tum(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i32m2_tum(mask,merge,op1,op2,31);
+}
+
+
+vint32m4_t test___riscv_vrem_vx_i32m4_tum(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i32m4_tum(mask,merge,op1,op2,31);
+}
+
+
+vint32m8_t test___riscv_vrem_vx_i32m8_tum(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i32m8_tum(mask,merge,op1,op2,31);
+}
+
+
+vint64m1_t test___riscv_vrem_vx_i64m1_tum(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i64m1_tum(mask,merge,op1,op2,31);
+}
+
+
+vint64m2_t test___riscv_vrem_vx_i64m2_tum(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i64m2_tum(mask,merge,op1,op2,31);
+}
+
+
+vint64m4_t test___riscv_vrem_vx_i64m4_tum(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i64m4_tum(mask,merge,op1,op2,31);
+}
+
+
+vint64m8_t test___riscv_vrem_vx_i64m8_tum(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i64m8_tum(mask,merge,op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vrem_vx_tum_rv64-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vrem_vx_tum_rv64-3.c
new file mode 100644
index 00000000000..a70bd24dbff
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vrem_vx_tum_rv64-3.c
@@ -0,0 +1,160 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vrem_vx_i8mf8_tum(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i8mf8_tum(mask,merge,op1,op2,32);
+}
+
+
+vint8mf4_t test___riscv_vrem_vx_i8mf4_tum(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i8mf4_tum(mask,merge,op1,op2,32);
+}
+
+
+vint8mf2_t test___riscv_vrem_vx_i8mf2_tum(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i8mf2_tum(mask,merge,op1,op2,32);
+}
+
+
+vint8m1_t test___riscv_vrem_vx_i8m1_tum(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i8m1_tum(mask,merge,op1,op2,32);
+}
+
+
+vint8m2_t test___riscv_vrem_vx_i8m2_tum(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i8m2_tum(mask,merge,op1,op2,32);
+}
+
+
+vint8m4_t test___riscv_vrem_vx_i8m4_tum(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i8m4_tum(mask,merge,op1,op2,32);
+}
+
+
+vint8m8_t test___riscv_vrem_vx_i8m8_tum(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i8m8_tum(mask,merge,op1,op2,32);
+}
+
+
+vint16mf4_t test___riscv_vrem_vx_i16mf4_tum(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i16mf4_tum(mask,merge,op1,op2,32);
+}
+
+
+vint16mf2_t test___riscv_vrem_vx_i16mf2_tum(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i16mf2_tum(mask,merge,op1,op2,32);
+}
+
+
+vint16m1_t test___riscv_vrem_vx_i16m1_tum(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i16m1_tum(mask,merge,op1,op2,32);
+}
+
+
+vint16m2_t test___riscv_vrem_vx_i16m2_tum(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i16m2_tum(mask,merge,op1,op2,32);
+}
+
+
+vint16m4_t test___riscv_vrem_vx_i16m4_tum(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i16m4_tum(mask,merge,op1,op2,32);
+}
+
+
+vint16m8_t test___riscv_vrem_vx_i16m8_tum(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i16m8_tum(mask,merge,op1,op2,32);
+}
+
+
+vint32mf2_t test___riscv_vrem_vx_i32mf2_tum(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i32mf2_tum(mask,merge,op1,op2,32);
+}
+
+
+vint32m1_t test___riscv_vrem_vx_i32m1_tum(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i32m1_tum(mask,merge,op1,op2,32);
+}
+
+
+vint32m2_t test___riscv_vrem_vx_i32m2_tum(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i32m2_tum(mask,merge,op1,op2,32);
+}
+
+
+vint32m4_t test___riscv_vrem_vx_i32m4_tum(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i32m4_tum(mask,merge,op1,op2,32);
+}
+
+
+vint32m8_t test___riscv_vrem_vx_i32m8_tum(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i32m8_tum(mask,merge,op1,op2,32);
+}
+
+
+vint64m1_t test___riscv_vrem_vx_i64m1_tum(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i64m1_tum(mask,merge,op1,op2,32);
+}
+
+
+vint64m2_t test___riscv_vrem_vx_i64m2_tum(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i64m2_tum(mask,merge,op1,op2,32);
+}
+
+
+vint64m4_t test___riscv_vrem_vx_i64m4_tum(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i64m4_tum(mask,merge,op1,op2,32);
+}
+
+
+vint64m8_t test___riscv_vrem_vx_i64m8_tum(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i64m8_tum(mask,merge,op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vrem_vx_tumu_rv32-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vrem_vx_tumu_rv32-1.c
new file mode 100644
index 00000000000..54fffba7832
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vrem_vx_tumu_rv32-1.c
@@ -0,0 +1,157 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vrem_vx_i8mf8_tumu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i8mf8_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint8mf4_t test___riscv_vrem_vx_i8mf4_tumu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i8mf4_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint8mf2_t test___riscv_vrem_vx_i8mf2_tumu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i8mf2_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint8m1_t test___riscv_vrem_vx_i8m1_tumu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i8m1_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint8m2_t test___riscv_vrem_vx_i8m2_tumu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i8m2_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint8m4_t test___riscv_vrem_vx_i8m4_tumu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i8m4_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint8m8_t test___riscv_vrem_vx_i8m8_tumu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i8m8_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint16mf4_t test___riscv_vrem_vx_i16mf4_tumu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i16mf4_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint16mf2_t test___riscv_vrem_vx_i16mf2_tumu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i16mf2_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint16m1_t test___riscv_vrem_vx_i16m1_tumu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i16m1_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint16m2_t test___riscv_vrem_vx_i16m2_tumu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i16m2_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint16m4_t test___riscv_vrem_vx_i16m4_tumu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i16m4_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint16m8_t test___riscv_vrem_vx_i16m8_tumu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i16m8_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint32mf2_t test___riscv_vrem_vx_i32mf2_tumu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i32mf2_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint32m1_t test___riscv_vrem_vx_i32m1_tumu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i32m1_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint32m2_t test___riscv_vrem_vx_i32m2_tumu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i32m2_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint32m4_t test___riscv_vrem_vx_i32m4_tumu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i32m4_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint32m8_t test___riscv_vrem_vx_i32m8_tumu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i32m8_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint64m1_t test___riscv_vrem_vx_i64m1_tumu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i64m1_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint64m2_t test___riscv_vrem_vx_i64m2_tumu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i64m2_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint64m4_t test___riscv_vrem_vx_i64m4_tumu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i64m4_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint64m8_t test___riscv_vrem_vx_i64m8_tumu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i64m8_tumu(mask,merge,op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*mu\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*mu\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*mu\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vrem\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 4 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vrem_vx_tumu_rv32-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vrem_vx_tumu_rv32-2.c
new file mode 100644
index 00000000000..d66a8812119
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vrem_vx_tumu_rv32-2.c
@@ -0,0 +1,157 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vrem_vx_i8mf8_tumu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i8mf8_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint8mf4_t test___riscv_vrem_vx_i8mf4_tumu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i8mf4_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint8mf2_t test___riscv_vrem_vx_i8mf2_tumu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i8mf2_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint8m1_t test___riscv_vrem_vx_i8m1_tumu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i8m1_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint8m2_t test___riscv_vrem_vx_i8m2_tumu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i8m2_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint8m4_t test___riscv_vrem_vx_i8m4_tumu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i8m4_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint8m8_t test___riscv_vrem_vx_i8m8_tumu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i8m8_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint16mf4_t test___riscv_vrem_vx_i16mf4_tumu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i16mf4_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint16mf2_t test___riscv_vrem_vx_i16mf2_tumu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i16mf2_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint16m1_t test___riscv_vrem_vx_i16m1_tumu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i16m1_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint16m2_t test___riscv_vrem_vx_i16m2_tumu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i16m2_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint16m4_t test___riscv_vrem_vx_i16m4_tumu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i16m4_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint16m8_t test___riscv_vrem_vx_i16m8_tumu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i16m8_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint32mf2_t test___riscv_vrem_vx_i32mf2_tumu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i32mf2_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint32m1_t test___riscv_vrem_vx_i32m1_tumu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i32m1_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint32m2_t test___riscv_vrem_vx_i32m2_tumu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i32m2_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint32m4_t test___riscv_vrem_vx_i32m4_tumu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i32m4_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint32m8_t test___riscv_vrem_vx_i32m8_tumu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i32m8_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint64m1_t test___riscv_vrem_vx_i64m1_tumu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i64m1_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint64m2_t test___riscv_vrem_vx_i64m2_tumu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i64m2_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint64m4_t test___riscv_vrem_vx_i64m4_tumu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i64m4_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint64m8_t test___riscv_vrem_vx_i64m8_tumu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i64m8_tumu(mask,merge,op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*mu\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*mu\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*mu\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*mu\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*mu\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*mu\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*mu\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*mu\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*mu\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*mu\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*mu\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*mu\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*mu\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*mu\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*mu\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*mu\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*mu\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*mu\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vrem\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 4 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vrem_vx_tumu_rv32-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vrem_vx_tumu_rv32-3.c
new file mode 100644
index 00000000000..705e31a89d7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vrem_vx_tumu_rv32-3.c
@@ -0,0 +1,157 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vrem_vx_i8mf8_tumu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i8mf8_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint8mf4_t test___riscv_vrem_vx_i8mf4_tumu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i8mf4_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint8mf2_t test___riscv_vrem_vx_i8mf2_tumu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i8mf2_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint8m1_t test___riscv_vrem_vx_i8m1_tumu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i8m1_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint8m2_t test___riscv_vrem_vx_i8m2_tumu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i8m2_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint8m4_t test___riscv_vrem_vx_i8m4_tumu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i8m4_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint8m8_t test___riscv_vrem_vx_i8m8_tumu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i8m8_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint16mf4_t test___riscv_vrem_vx_i16mf4_tumu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i16mf4_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint16mf2_t test___riscv_vrem_vx_i16mf2_tumu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i16mf2_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint16m1_t test___riscv_vrem_vx_i16m1_tumu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i16m1_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint16m2_t test___riscv_vrem_vx_i16m2_tumu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i16m2_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint16m4_t test___riscv_vrem_vx_i16m4_tumu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i16m4_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint16m8_t test___riscv_vrem_vx_i16m8_tumu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i16m8_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint32mf2_t test___riscv_vrem_vx_i32mf2_tumu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i32mf2_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint32m1_t test___riscv_vrem_vx_i32m1_tumu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i32m1_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint32m2_t test___riscv_vrem_vx_i32m2_tumu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i32m2_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint32m4_t test___riscv_vrem_vx_i32m4_tumu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i32m4_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint32m8_t test___riscv_vrem_vx_i32m8_tumu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i32m8_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint64m1_t test___riscv_vrem_vx_i64m1_tumu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i64m1_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint64m2_t test___riscv_vrem_vx_i64m2_tumu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i64m2_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint64m4_t test___riscv_vrem_vx_i64m4_tumu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i64m4_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint64m8_t test___riscv_vrem_vx_i64m8_tumu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i64m8_tumu(mask,merge,op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*mu\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*mu\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*mu\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vrem\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 4 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vrem_vx_tumu_rv64-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vrem_vx_tumu_rv64-1.c
new file mode 100644
index 00000000000..024089b4dfc
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vrem_vx_tumu_rv64-1.c
@@ -0,0 +1,160 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vrem_vx_i8mf8_tumu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i8mf8_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint8mf4_t test___riscv_vrem_vx_i8mf4_tumu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i8mf4_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint8mf2_t test___riscv_vrem_vx_i8mf2_tumu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i8mf2_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint8m1_t test___riscv_vrem_vx_i8m1_tumu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i8m1_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint8m2_t test___riscv_vrem_vx_i8m2_tumu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i8m2_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint8m4_t test___riscv_vrem_vx_i8m4_tumu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i8m4_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint8m8_t test___riscv_vrem_vx_i8m8_tumu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i8m8_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint16mf4_t test___riscv_vrem_vx_i16mf4_tumu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i16mf4_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint16mf2_t test___riscv_vrem_vx_i16mf2_tumu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i16mf2_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint16m1_t test___riscv_vrem_vx_i16m1_tumu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i16m1_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint16m2_t test___riscv_vrem_vx_i16m2_tumu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i16m2_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint16m4_t test___riscv_vrem_vx_i16m4_tumu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i16m4_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint16m8_t test___riscv_vrem_vx_i16m8_tumu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i16m8_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint32mf2_t test___riscv_vrem_vx_i32mf2_tumu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i32mf2_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint32m1_t test___riscv_vrem_vx_i32m1_tumu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i32m1_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint32m2_t test___riscv_vrem_vx_i32m2_tumu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i32m2_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint32m4_t test___riscv_vrem_vx_i32m4_tumu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i32m4_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint32m8_t test___riscv_vrem_vx_i32m8_tumu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i32m8_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint64m1_t test___riscv_vrem_vx_i64m1_tumu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i64m1_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint64m2_t test___riscv_vrem_vx_i64m2_tumu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i64m2_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint64m4_t test___riscv_vrem_vx_i64m4_tumu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i64m4_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint64m8_t test___riscv_vrem_vx_i64m8_tumu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i64m8_tumu(mask,merge,op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*mu\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*mu\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*mu\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*mu\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*mu\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*mu\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*mu\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vrem_vx_tumu_rv64-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vrem_vx_tumu_rv64-2.c
new file mode 100644
index 00000000000..f53b4e44820
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vrem_vx_tumu_rv64-2.c
@@ -0,0 +1,160 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vrem_vx_i8mf8_tumu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i8mf8_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint8mf4_t test___riscv_vrem_vx_i8mf4_tumu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i8mf4_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint8mf2_t test___riscv_vrem_vx_i8mf2_tumu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i8mf2_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint8m1_t test___riscv_vrem_vx_i8m1_tumu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i8m1_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint8m2_t test___riscv_vrem_vx_i8m2_tumu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i8m2_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint8m4_t test___riscv_vrem_vx_i8m4_tumu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i8m4_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint8m8_t test___riscv_vrem_vx_i8m8_tumu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i8m8_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint16mf4_t test___riscv_vrem_vx_i16mf4_tumu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i16mf4_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint16mf2_t test___riscv_vrem_vx_i16mf2_tumu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i16mf2_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint16m1_t test___riscv_vrem_vx_i16m1_tumu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i16m1_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint16m2_t test___riscv_vrem_vx_i16m2_tumu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i16m2_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint16m4_t test___riscv_vrem_vx_i16m4_tumu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i16m4_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint16m8_t test___riscv_vrem_vx_i16m8_tumu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i16m8_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint32mf2_t test___riscv_vrem_vx_i32mf2_tumu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i32mf2_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint32m1_t test___riscv_vrem_vx_i32m1_tumu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i32m1_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint32m2_t test___riscv_vrem_vx_i32m2_tumu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i32m2_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint32m4_t test___riscv_vrem_vx_i32m4_tumu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i32m4_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint32m8_t test___riscv_vrem_vx_i32m8_tumu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i32m8_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint64m1_t test___riscv_vrem_vx_i64m1_tumu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i64m1_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint64m2_t test___riscv_vrem_vx_i64m2_tumu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i64m2_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint64m4_t test___riscv_vrem_vx_i64m4_tumu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i64m4_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint64m8_t test___riscv_vrem_vx_i64m8_tumu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i64m8_tumu(mask,merge,op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*mu\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*mu\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*mu\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*mu\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*mu\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*mu\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*mu\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*mu\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*mu\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*mu\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*mu\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*mu\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*mu\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*mu\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*mu\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*mu\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*mu\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*mu\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*mu\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*mu\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*mu\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*mu\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vrem_vx_tumu_rv64-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vrem_vx_tumu_rv64-3.c
new file mode 100644
index 00000000000..97c2285f5bb
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vrem_vx_tumu_rv64-3.c
@@ -0,0 +1,160 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vrem_vx_i8mf8_tumu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i8mf8_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint8mf4_t test___riscv_vrem_vx_i8mf4_tumu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i8mf4_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint8mf2_t test___riscv_vrem_vx_i8mf2_tumu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i8mf2_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint8m1_t test___riscv_vrem_vx_i8m1_tumu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i8m1_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint8m2_t test___riscv_vrem_vx_i8m2_tumu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i8m2_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint8m4_t test___riscv_vrem_vx_i8m4_tumu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i8m4_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint8m8_t test___riscv_vrem_vx_i8m8_tumu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i8m8_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint16mf4_t test___riscv_vrem_vx_i16mf4_tumu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i16mf4_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint16mf2_t test___riscv_vrem_vx_i16mf2_tumu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i16mf2_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint16m1_t test___riscv_vrem_vx_i16m1_tumu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i16m1_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint16m2_t test___riscv_vrem_vx_i16m2_tumu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i16m2_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint16m4_t test___riscv_vrem_vx_i16m4_tumu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i16m4_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint16m8_t test___riscv_vrem_vx_i16m8_tumu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i16m8_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint32mf2_t test___riscv_vrem_vx_i32mf2_tumu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i32mf2_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint32m1_t test___riscv_vrem_vx_i32m1_tumu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i32m1_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint32m2_t test___riscv_vrem_vx_i32m2_tumu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i32m2_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint32m4_t test___riscv_vrem_vx_i32m4_tumu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i32m4_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint32m8_t test___riscv_vrem_vx_i32m8_tumu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i32m8_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint64m1_t test___riscv_vrem_vx_i64m1_tumu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i64m1_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint64m2_t test___riscv_vrem_vx_i64m2_tumu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i64m2_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint64m4_t test___riscv_vrem_vx_i64m4_tumu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i64m4_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint64m8_t test___riscv_vrem_vx_i64m8_tumu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrem_vx_i64m8_tumu(mask,merge,op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*mu\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*mu\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*mu\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*mu\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*mu\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*mu\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*mu\s+vrem\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */