From patchwork Fri Feb 3 04:58:51 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Monk Chiang X-Patchwork-Id: 64197 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id CCCE43858C60 for ; Fri, 3 Feb 2023 04:59:23 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mail-pf1-x429.google.com (mail-pf1-x429.google.com [IPv6:2607:f8b0:4864:20::429]) by sourceware.org (Postfix) with ESMTPS id D01B43858C5F for ; Fri, 3 Feb 2023 04:59:04 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org D01B43858C5F Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=sifive.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=sifive.com Received: by mail-pf1-x429.google.com with SMTP id bd15so2760665pfb.8 for ; Thu, 02 Feb 2023 20:59:04 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:from:to:cc:subject:date:message-id:reply-to; bh=w5de7LSkPtzQvV+hYYEz2Bx8+TNoqX/I+aDqKcvY4yQ=; b=gC+EeXKTlEL13jW+mY0IynXXgSiTTQc5c8VG2CzGoAtKa/cjVNCOawG5Lb2OfREqFJ RVf5TPiz2yqOnJ2X/PBZDig7wiufwtb3OGkjGYed1ZYTPAm2oBdRSN0wiejrnEGHvhDi WODySMSaVxmZRENo4Ms0t1e/o3rOHA9o0kbU3UB3u6w1z1Ili6ACQXAHLfwxPidQy5ym tZa/oa6Srj92fwt5XE26RYSx7N5IlLiPDqpG7kJM3TlbASSgVaJQgYv5fUdUpqNjITz2 iV8qgRtijfr9eUlPnVGIfld/emMWXrU3pv3Kx+YNoIXLn5Vy+n+MXZvK7eIXzEE/jAjX 6rEw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=w5de7LSkPtzQvV+hYYEz2Bx8+TNoqX/I+aDqKcvY4yQ=; b=mGShLNz5ATE9wVzysI2AU3SPk4kW+fncsK6FgFuMrxvRsKxQ5PerEhEFKbQE7dLPe3 OEB+8fI0Veg/z1ooF2OVdfsb+fVctrc3/03zmBQtK4Q9WwUSvAUxOlyeUD1udJbYeHha 8zanqsDF0H+7n0TgPBFgYOYmW/xLXjVq7DcFd/BGeUu2PcO1b7bpueUoDyqti4Qx4Pu8 lP3VOqeq6ZZ5ZvVj/KlWfxNZk8cDf3ckmgq0/Vl9ILTsGzdIHnG9LbGxHjv9xAI8xHvi EKFdJOxMUUoLF64ZmQZlY/kXVVmTkXDPxlSxjgZGLN+wXsQfuFNhUssIclP+wiWsYynI YyYQ== X-Gm-Message-State: AO0yUKXodrxUXtRCLs9JM1rK9Pq0ZC6Q8Z0LSe5U0r6hiYdtVhs7ox/b dSoYbD+km/od/q2DBvGeWO7ZsTOsosMc8+MTMYSCzxqN1ziIxRXVcbFYiGzLK+Qrz14YSq/YFDb z4+k/j9N7/GhIkL3AGV4kvqhBm6TNsB5i5xGk7undKxOA0VOOwBDfNd7C42OkbR0em17Y82BpLy nEqA== X-Google-Smtp-Source: AK7set/lNQfuhzEbEmzoNuaiJi8/E/leHVTHcSRGnbD7r/wxUC3tAQfKnHpcNkXe4UI4aRKgJXFEpg== X-Received: by 2002:a05:6a00:1384:b0:592:52a0:6824 with SMTP id t4-20020a056a00138400b0059252a06824mr10175032pfg.0.1675400342355; Thu, 02 Feb 2023 20:59:02 -0800 (PST) Received: from hsinchu02.internal.sifive.com (59-124-168-89.hinet-ip.hinet.net. [59.124.168.89]) by smtp.gmail.com with ESMTPSA id v2-20020a622f02000000b0059261bd5bacsm566087pfv.202.2023.02.02.20.59.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 02 Feb 2023 20:59:02 -0800 (PST) From: Monk Chiang To: gcc-patches@gcc.gnu.org, kito.cheng@gmail.com Cc: Monk Chiang Subject: [PATCH] RISC-V: Remove unnecessary register class. Date: Fri, 3 Feb 2023 12:58:51 +0800 Message-Id: <20230203045851.43100-1-monk.chiang@sifive.com> X-Mailer: git-send-email 2.37.2 MIME-Version: 1.0 X-Spam-Status: No, score=-13.7 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" Avoid VL_REGS, VTYPE_REGS join register allocation. gcc/ChangeLog: * config/riscv/riscv.h: Remove VL_REGS, VTYPE_REGS class. * config/riscv/riscv.cc: Ditto. --- gcc/config/riscv/riscv.cc | 8 +------- gcc/config/riscv/riscv.h | 6 ------ 2 files changed, 1 insertion(+), 13 deletions(-) diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index 209d9a53e7b..3b7804b7501 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -293,7 +293,7 @@ const enum reg_class riscv_regno_to_class[FIRST_PSEUDO_REGISTER] = { FP_REGS, FP_REGS, FP_REGS, FP_REGS, FP_REGS, FP_REGS, FP_REGS, FP_REGS, FP_REGS, FP_REGS, FP_REGS, FP_REGS, - FRAME_REGS, FRAME_REGS, VL_REGS, VTYPE_REGS, + FRAME_REGS, FRAME_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, @@ -5831,12 +5831,6 @@ riscv_class_max_nregs (reg_class_t rclass, machine_mode mode) if (reg_class_subset_p (rclass, V_REGS)) return riscv_hard_regno_nregs (V_REG_FIRST, mode); - if (reg_class_subset_p (rclass, VL_REGS)) - return 1; - - if (reg_class_subset_p (rclass, VTYPE_REGS)) - return 1; - return 0; } diff --git a/gcc/config/riscv/riscv.h b/gcc/config/riscv/riscv.h index 0ab739bd6eb..02e1224c3cd 100644 --- a/gcc/config/riscv/riscv.h +++ b/gcc/config/riscv/riscv.h @@ -462,8 +462,6 @@ enum reg_class GR_REGS, /* integer registers */ FP_REGS, /* floating-point registers */ FRAME_REGS, /* arg pointer and frame pointer */ - VL_REGS, /* vl register */ - VTYPE_REGS, /* vtype register */ VM_REGS, /* v0.t registers */ VD_REGS, /* vector registers except v0.t */ V_REGS, /* vector registers */ @@ -487,8 +485,6 @@ enum reg_class "GR_REGS", \ "FP_REGS", \ "FRAME_REGS", \ - "VL_REGS", \ - "VTYPE_REGS", \ "VM_REGS", \ "VD_REGS", \ "V_REGS", \ @@ -514,8 +510,6 @@ enum reg_class { 0xffffffff, 0x00000000, 0x00000000, 0x00000000 }, /* GR_REGS */ \ { 0x00000000, 0xffffffff, 0x00000000, 0x00000000 }, /* FP_REGS */ \ { 0x00000000, 0x00000000, 0x00000003, 0x00000000 }, /* FRAME_REGS */ \ - { 0x00000000, 0x00000000, 0x00000004, 0x00000000 }, /* VL_REGS */ \ - { 0x00000000, 0x00000000, 0x00000008, 0x00000000 }, /* VTYPE_REGS */ \ { 0x00000000, 0x00000000, 0x00000000, 0x00000001 }, /* V0_REGS */ \ { 0x00000000, 0x00000000, 0x00000000, 0xfffffffe }, /* VNoV0_REGS */ \ { 0x00000000, 0x00000000, 0x00000000, 0xffffffff }, /* V_REGS */ \