diff mbox series

rs6000: mark tieable between INT and FLOAT

Message ID	20230106122552.145679-1-guojiufu@linux.ibm.com
State	New
Headers	DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org EDAF73858D28 To: gcc-patches@gcc.gnu.org Cc: segher@kernel.crashing.org, dje.gcc@gmail.com, linkw@gcc.gnu.org, guojiufu@linux.ibm.com Subject: [PATCH] rs6000: mark tieable between INT and FLOAT Date: Fri, 6 Jan 2023 20:25:52 +0800 Message-Id: <20230106122552.145679-1-guojiufu@linux.ibm.com> Precedence: list From: Jiufu Guo via Gcc-patches <gcc-patches@gcc.gnu.org> Reply-To: Jiufu Guo <guojiufu@linux.ibm.com> Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" <gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org>
Series	rs6000: mark tieable between INT and FLOAT \| rs6000: mark tieable between INT and FLOAT

Commit Message

Jiufu Guo Jan. 6, 2023, 12:25 p.m. UTC

  Hi,

During discussing/review patches in maillist, we find more modes are
tieable, e.g. DI<->DF.  With some discussion, I drafted this patch
to mark more tieable modes.

Bootstrap and regtest pass on ppc64{,le}.
Is this ok for trunk?

BR,
Jeff (Jiufu)

gcc/ChangeLog:

	* config/rs6000/rs6000.cc (rs6000_modes_tieable_p): Mark more tieable
	modes.

gcc/testsuite/ChangeLog:

	* g++.target/powerpc/pr102024.C: Updated.

---
 gcc/config/rs6000/rs6000.cc                 | 9 +++++++++
 gcc/testsuite/g++.target/powerpc/pr102024.C | 3 ++-
 2 files changed, 11 insertions(+), 1 deletion(-)

Comments

Jiufu Guo Feb. 21, 2023, 1:32 a.m. UTC | #1

Hi,

Gently Ping:
https://gcc.gnu.org/pipermail/gcc-patches/2023-January/609504.html

BR,
Jeff (Jiufu)


Jiufu Guo <guojiufu@linux.ibm.com> writes:

> Hi,
>
> During discussing/review patches in maillist, we find more modes are
> tieable, e.g. DI<->DF.  With some discussion, I drafted this patch
> to mark more tieable modes.
>
> Bootstrap and regtest pass on ppc64{,le}.
> Is this ok for trunk?
>
> BR,
> Jeff (Jiufu)
>
> gcc/ChangeLog:
>
> 	* config/rs6000/rs6000.cc (rs6000_modes_tieable_p): Mark more tieable
> 	modes.
>
> gcc/testsuite/ChangeLog:
>
> 	* g++.target/powerpc/pr102024.C: Updated.
>
> ---
>  gcc/config/rs6000/rs6000.cc                 | 9 +++++++++
>  gcc/testsuite/g++.target/powerpc/pr102024.C | 3 ++-
>  2 files changed, 11 insertions(+), 1 deletion(-)
>
> diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
> index 6ac3adcec6b..3cb0186089e 100644
> --- a/gcc/config/rs6000/rs6000.cc
> +++ b/gcc/config/rs6000/rs6000.cc
> @@ -1968,6 +1968,15 @@ rs6000_modes_tieable_p (machine_mode mode1, machine_mode mode2)
>    if (ALTIVEC_OR_VSX_VECTOR_MODE (mode2))
>      return false;
>  
> +  /* SFmode format (IEEE DP) in register would not as required,
> +     So SFmode is restrict here.  */
> +  if (GET_MODE_CLASS (mode1) == MODE_FLOAT
> +      && GET_MODE_CLASS (mode2) == MODE_INT)
> +    return GET_MODE_SIZE (mode2) == UNITS_PER_FP_WORD && mode1 != SFmode;
> +  if (GET_MODE_CLASS (mode1) == MODE_INT
> +      && GET_MODE_CLASS (mode2) == MODE_FLOAT)
> +    return GET_MODE_SIZE (mode1) == UNITS_PER_FP_WORD && mode2 != SFmode;
> +
>    if (SCALAR_FLOAT_MODE_P (mode1))
>      return SCALAR_FLOAT_MODE_P (mode2);
>    if (SCALAR_FLOAT_MODE_P (mode2))
> diff --git a/gcc/testsuite/g++.target/powerpc/pr102024.C b/gcc/testsuite/g++.target/powerpc/pr102024.C
> index 769585052b5..27d2dc5e80b 100644
> --- a/gcc/testsuite/g++.target/powerpc/pr102024.C
> +++ b/gcc/testsuite/g++.target/powerpc/pr102024.C
> @@ -5,7 +5,8 @@
>  // Test that a zero-width bit field in an otherwise homogeneous aggregate
>  // generates a psabi warning and passes arguments in GPRs.
>  
> -// { dg-final { scan-assembler-times {\mstd\M} 4 } }
> +// { dg-final { scan-assembler-times {\mmtvsrd\M} 4 { target has_arch_pwr8 } } }
> +// { dg-final { scan-assembler-times {\mstd\M} 4 { target { ! has_arch_pwr8 } } } }
>  
>  struct a_thing
>  {

Jiufu Guo April 26, 2023, 2:54 a.m. UTC | #2

Hi,

I would ping this patch for stage1:
https://gcc.gnu.org/pipermail/gcc-patches/2023-January/609504.html

BR,
Jeff (Jiufu)

Jiufu Guo via Gcc-patches <gcc-patches@gcc.gnu.org> writes:

> Hi,
>
> Gently Ping:
> https://gcc.gnu.org/pipermail/gcc-patches/2023-January/609504.html
>
> BR,
> Jeff (Jiufu)
>
>
> Jiufu Guo <guojiufu@linux.ibm.com> writes:
>
>> Hi,
>>
>> During discussing/review patches in maillist, we find more modes are
>> tieable, e.g. DI<->DF.  With some discussion, I drafted this patch
>> to mark more tieable modes.
>>
>> Bootstrap and regtest pass on ppc64{,le}.
>> Is this ok for trunk?
>>
>> BR,
>> Jeff (Jiufu)
>>
>> gcc/ChangeLog:
>>
>> 	* config/rs6000/rs6000.cc (rs6000_modes_tieable_p): Mark more tieable
>> 	modes.
>>
>> gcc/testsuite/ChangeLog:
>>
>> 	* g++.target/powerpc/pr102024.C: Updated.
>>
>> ---
>>  gcc/config/rs6000/rs6000.cc                 | 9 +++++++++
>>  gcc/testsuite/g++.target/powerpc/pr102024.C | 3 ++-
>>  2 files changed, 11 insertions(+), 1 deletion(-)
>>
>> diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
>> index 6ac3adcec6b..3cb0186089e 100644
>> --- a/gcc/config/rs6000/rs6000.cc
>> +++ b/gcc/config/rs6000/rs6000.cc
>> @@ -1968,6 +1968,15 @@ rs6000_modes_tieable_p (machine_mode mode1, machine_mode mode2)
>>    if (ALTIVEC_OR_VSX_VECTOR_MODE (mode2))
>>      return false;
>>  
>> +  /* SFmode format (IEEE DP) in register would not as required,
>> +     So SFmode is restrict here.  */
>> +  if (GET_MODE_CLASS (mode1) == MODE_FLOAT
>> +      && GET_MODE_CLASS (mode2) == MODE_INT)
>> +    return GET_MODE_SIZE (mode2) == UNITS_PER_FP_WORD && mode1 != SFmode;
>> +  if (GET_MODE_CLASS (mode1) == MODE_INT
>> +      && GET_MODE_CLASS (mode2) == MODE_FLOAT)
>> +    return GET_MODE_SIZE (mode1) == UNITS_PER_FP_WORD && mode2 != SFmode;
>> +
>>    if (SCALAR_FLOAT_MODE_P (mode1))
>>      return SCALAR_FLOAT_MODE_P (mode2);
>>    if (SCALAR_FLOAT_MODE_P (mode2))
>> diff --git a/gcc/testsuite/g++.target/powerpc/pr102024.C b/gcc/testsuite/g++.target/powerpc/pr102024.C
>> index 769585052b5..27d2dc5e80b 100644
>> --- a/gcc/testsuite/g++.target/powerpc/pr102024.C
>> +++ b/gcc/testsuite/g++.target/powerpc/pr102024.C
>> @@ -5,7 +5,8 @@
>>  // Test that a zero-width bit field in an otherwise homogeneous aggregate
>>  // generates a psabi warning and passes arguments in GPRs.
>>  
>> -// { dg-final { scan-assembler-times {\mstd\M} 4 } }
>> +// { dg-final { scan-assembler-times {\mmtvsrd\M} 4 { target has_arch_pwr8 } } }
>> +// { dg-final { scan-assembler-times {\mstd\M} 4 { target { ! has_arch_pwr8 } } } }
>>  
>>  struct a_thing
>>  {

Jiufu Guo May 17, 2023, 6:46 a.m. UTC | #3

Gentle ping...

Jiufu Guo via Gcc-patches <gcc-patches@gcc.gnu.org> writes:

> Hi,
>
> I would ping this patch for stage1:
> https://gcc.gnu.org/pipermail/gcc-patches/2023-January/609504.html
>
> BR,
> Jeff (Jiufu)
>
> Jiufu Guo via Gcc-patches <gcc-patches@gcc.gnu.org> writes:
>
>> Hi,
>>
>> Gently Ping:
>> https://gcc.gnu.org/pipermail/gcc-patches/2023-January/609504.html
>>
>> BR,
>> Jeff (Jiufu)
>>
>>
>> Jiufu Guo <guojiufu@linux.ibm.com> writes:
>>
>>> Hi,
>>>
>>> During discussing/review patches in maillist, we find more modes are
>>> tieable, e.g. DI<->DF.  With some discussion, I drafted this patch
>>> to mark more tieable modes.
>>>
>>> Bootstrap and regtest pass on ppc64{,le}.
>>> Is this ok for trunk?
>>>
>>> BR,
>>> Jeff (Jiufu)
>>>
>>> gcc/ChangeLog:
>>>
>>> 	* config/rs6000/rs6000.cc (rs6000_modes_tieable_p): Mark more tieable
>>> 	modes.
>>>
>>> gcc/testsuite/ChangeLog:
>>>
>>> 	* g++.target/powerpc/pr102024.C: Updated.
>>>
>>> ---
>>>  gcc/config/rs6000/rs6000.cc                 | 9 +++++++++
>>>  gcc/testsuite/g++.target/powerpc/pr102024.C | 3 ++-
>>>  2 files changed, 11 insertions(+), 1 deletion(-)
>>>
>>> diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
>>> index 6ac3adcec6b..3cb0186089e 100644
>>> --- a/gcc/config/rs6000/rs6000.cc
>>> +++ b/gcc/config/rs6000/rs6000.cc
>>> @@ -1968,6 +1968,15 @@ rs6000_modes_tieable_p (machine_mode mode1, machine_mode mode2)
>>>    if (ALTIVEC_OR_VSX_VECTOR_MODE (mode2))
>>>      return false;
>>>  
>>> +  /* SFmode format (IEEE DP) in register would not as required,
>>> +     So SFmode is restrict here.  */
>>> +  if (GET_MODE_CLASS (mode1) == MODE_FLOAT
>>> +      && GET_MODE_CLASS (mode2) == MODE_INT)
>>> +    return GET_MODE_SIZE (mode2) == UNITS_PER_FP_WORD && mode1 != SFmode;
>>> +  if (GET_MODE_CLASS (mode1) == MODE_INT
>>> +      && GET_MODE_CLASS (mode2) == MODE_FLOAT)
>>> +    return GET_MODE_SIZE (mode1) == UNITS_PER_FP_WORD && mode2 != SFmode;
>>> +
>>>    if (SCALAR_FLOAT_MODE_P (mode1))
>>>      return SCALAR_FLOAT_MODE_P (mode2);
>>>    if (SCALAR_FLOAT_MODE_P (mode2))
>>> diff --git a/gcc/testsuite/g++.target/powerpc/pr102024.C b/gcc/testsuite/g++.target/powerpc/pr102024.C
>>> index 769585052b5..27d2dc5e80b 100644
>>> --- a/gcc/testsuite/g++.target/powerpc/pr102024.C
>>> +++ b/gcc/testsuite/g++.target/powerpc/pr102024.C
>>> @@ -5,7 +5,8 @@
>>>  // Test that a zero-width bit field in an otherwise homogeneous aggregate
>>>  // generates a psabi warning and passes arguments in GPRs.
>>>  
>>> -// { dg-final { scan-assembler-times {\mstd\M} 4 } }
>>> +// { dg-final { scan-assembler-times {\mmtvsrd\M} 4 { target has_arch_pwr8 } } }
>>> +// { dg-final { scan-assembler-times {\mstd\M} 4 { target { ! has_arch_pwr8 } } } }
>>>  
>>>  struct a_thing
>>>  {

diff mbox series

Patch

diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index 6ac3adcec6b..3cb0186089e 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -1968,6 +1968,15 @@  rs6000_modes_tieable_p (machine_mode mode1, machine_mode mode2)
   if (ALTIVEC_OR_VSX_VECTOR_MODE (mode2))
     return false;
 
+  /* SFmode format (IEEE DP) in register would not as required,
+     So SFmode is restrict here.  */
+  if (GET_MODE_CLASS (mode1) == MODE_FLOAT
+      && GET_MODE_CLASS (mode2) == MODE_INT)
+    return GET_MODE_SIZE (mode2) == UNITS_PER_FP_WORD && mode1 != SFmode;
+  if (GET_MODE_CLASS (mode1) == MODE_INT
+      && GET_MODE_CLASS (mode2) == MODE_FLOAT)
+    return GET_MODE_SIZE (mode1) == UNITS_PER_FP_WORD && mode2 != SFmode;
+
   if (SCALAR_FLOAT_MODE_P (mode1))
     return SCALAR_FLOAT_MODE_P (mode2);
   if (SCALAR_FLOAT_MODE_P (mode2))
diff --git a/gcc/testsuite/g++.target/powerpc/pr102024.C b/gcc/testsuite/g++.target/powerpc/pr102024.C
index 769585052b5..27d2dc5e80b 100644
--- a/gcc/testsuite/g++.target/powerpc/pr102024.C
+++ b/gcc/testsuite/g++.target/powerpc/pr102024.C
@@ -5,7 +5,8 @@ 
 // Test that a zero-width bit field in an otherwise homogeneous aggregate
 // generates a psabi warning and passes arguments in GPRs.
 
-// { dg-final { scan-assembler-times {\mstd\M} 4 } }
+// { dg-final { scan-assembler-times {\mmtvsrd\M} 4 { target has_arch_pwr8 } } }
+// { dg-final { scan-assembler-times {\mstd\M} 4 { target { ! has_arch_pwr8 } } } }
 
 struct a_thing
 {