From patchwork Wed Dec 28 18:18:17 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Raphael Moreira Zinsly X-Patchwork-Id: 62469 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 9103F3858410 for ; Wed, 28 Dec 2022 18:18:52 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mail-oa1-x2b.google.com (mail-oa1-x2b.google.com [IPv6:2001:4860:4864:20::2b]) by sourceware.org (Postfix) with ESMTPS id 81F983858D35 for ; Wed, 28 Dec 2022 18:18:33 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 81F983858D35 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=ventanamicro.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=ventanamicro.com Received: by mail-oa1-x2b.google.com with SMTP id 586e51a60fabf-14fb3809eaeso13368189fac.1 for ; Wed, 28 Dec 2022 10:18:33 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:from:to:cc:subject:date:message-id:reply-to; bh=OATrbedgnWuHl4XAbcKkJKdbj2f1VYlzm3/+97zV2LA=; b=ETPo8fZPRh9eK5bgz96Prkuz6ppwDvF/kOdnbIV4ExwaS8tq5MF6f6dY4qfnl1EODY AjMZ7+kFQ1blS8HNcdRynYhNmTS0HjFcbXFoiShdzLEzatrJf38sHpxEP9j1x6pHrA1K t34SNv474yFqtO019zQI8Hsp4p/AYj21FhcyGoqm9HJi6fUlYN0+oPLpZxgYGeGNzhIP iBbIV0+K3Asn0cLCf1bmMq9rniEL4FLOkrZOwI4Z6/mOqEdmNZuOTv7pae5rBqo8JzYz DMVupF8lvnmDgynzcVVFQvcp2EDD0X65ssg1eGRgYizq55rVcgFxVHmctfDkq6wCHzEo NwYw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=OATrbedgnWuHl4XAbcKkJKdbj2f1VYlzm3/+97zV2LA=; b=iqqJ8WRyA17hEOFY6XWLFUUaU+b2ywXNcESfHmAZeHYr2NOaLkyI3qTvd/lfBT76RO GbwTBr8KUI09qbLHhKcmN5nBlI0jb0EksITHrx8AeKTVvn0X6UkrQ9Bat4xvpOXzlB++ G46uCED9izOoYkrLg0v77woX1UHI4iuI1ium99xmwrQGB5hJ+dIfMEs2YrlS8bbquV7f ZKwzmtRsBDOfJH410sXHMAs0qAUU5lzY8k6pfv5KdgArqbZKW6d/aT2PB8+Jg+JUp6nj +etEntXCZeaig5CHYLfDRnfQ5fpIND8Y6X6KtMAZVNlHwtJ/Uy8ARvbAUkvPSrxaqhtZ h76w== X-Gm-Message-State: AFqh2koWzp62rT7xirSDoVSgV1eharjaPT4R0SBMBY/R032LbJfhFPfq oBgOhtiPbZ3wmciQUTIj1gwLYQcAZ+FyFY0J X-Google-Smtp-Source: AMrXdXv9M/HHW6oLtVy3VuGqp/P+VwUm1WvdoF/4SZic3dvV/rouBxYX59JLVCMbNqg2H8UBPjxiUQ== X-Received: by 2002:a05:6871:414:b0:144:57b1:c8cf with SMTP id d20-20020a056871041400b0014457b1c8cfmr17503640oag.47.1672251512404; Wed, 28 Dec 2022 10:18:32 -0800 (PST) Received: from marvin.dc1.ventanamicro.com ([2804:14d:baa4:50a9::1000]) by smtp.gmail.com with ESMTPSA id s24-20020a056870ea9800b0014c7958c55bsm7731479oap.42.2022.12.28.10.18.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 Dec 2022 10:18:31 -0800 (PST) From: Raphael Moreira Zinsly To: gcc-patches@gcc.gnu.org Cc: jeffreyalaw@gmail.com, philipp.tomsich@vrull.eu, Raphael Moreira Zinsly Subject: [PATCH] RISC-V: Optimize min/max with SImode sources on 64-bit Date: Wed, 28 Dec 2022 15:18:17 -0300 Message-Id: <20221228181817.193462-1-rzinsly@ventanamicro.com> X-Mailer: git-send-email 2.38.1 MIME-Version: 1.0 X-Spam-Status: No, score=-13.9 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" The Zbb min/max pattern was not matching 32-bit sources when compiling for 64-bit. This patch separates the pattern into SImode and DImode, and use a define_expand to handle SImode on 64-bit. zbb-min-max-02.c generates different code as a result of the new expander.  The resulting code is as efficient as the old code. Furthermore, the special sh1add pattern that appeared in zbb-min-max-02.c is tested by the zba-shNadd-* tests. gcc/ChangeLog: * config/riscv/bitmanip.md (3): Divide pattern into si3_insn and di3. (si3): Handle SImode sources on TARGET_64BIT. gcc/testsuite: * gcc.target/riscv/zbb-abs.c: New test. * gcc.target/riscv/zbb-min-max-02.c: Addapt the expected output. --- gcc/config/riscv/bitmanip.md | 38 ++++++++++++++++--- gcc/testsuite/gcc.target/riscv/zbb-abs.c | 18 +++++++++ .../gcc.target/riscv/zbb-min-max-02.c | 2 +- 3 files changed, 52 insertions(+), 6 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/zbb-abs.c diff --git a/gcc/config/riscv/bitmanip.md b/gcc/config/riscv/bitmanip.md index d17133d58c1..abf08a29e89 100644 --- a/gcc/config/riscv/bitmanip.md +++ b/gcc/config/riscv/bitmanip.md @@ -360,14 +360,42 @@ DONE; }) -(define_insn "3" - [(set (match_operand:X 0 "register_operand" "=r") - (bitmanip_minmax:X (match_operand:X 1 "register_operand" "r") - (match_operand:X 2 "register_operand" "r")))] - "TARGET_ZBB" +(define_insn "si3_insn" + [(set (match_operand:SI 0 "register_operand" "=r") + (bitmanip_minmax:SI (match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r")))] + "!TARGET_64BIT && TARGET_ZBB" "\t%0,%1,%2" [(set_attr "type" "bitmanip")]) +(define_insn "di3" + [(set (match_operand:DI 0 "register_operand" "=r") + (bitmanip_minmax:DI (match_operand:DI 1 "register_operand" "r") + (match_operand:DI 2 "register_operand" "r")))] + "TARGET_64BIT && TARGET_ZBB" + "\t%0,%1,%2" + [(set_attr "type" "bitmanip")]) + +(define_expand "si3" + [(set (match_operand:SI 0 "register_operand" "=r") + (bitmanip_minmax:SI (match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r")))] + "TARGET_ZBB" + " +{ + if (TARGET_64BIT) + { + rtx op1_x = gen_reg_rtx (DImode); + emit_move_insn (op1_x, gen_rtx_SIGN_EXTEND (DImode, operands[1])); + rtx op2_x = gen_reg_rtx (DImode); + emit_move_insn (op2_x, gen_rtx_SIGN_EXTEND (DImode, operands[2])); + rtx dst_x = gen_reg_rtx (DImode); + emit_insn (gen_di3 (dst_x, op1_x, op2_x)); + emit_move_insn (operands[0], gen_lowpart (SImode, dst_x)); + DONE; + } +}") + ;; Optimize the common case of a SImode min/max against a constant ;; that is safe both for sign- and zero-extension. (define_insn_and_split "*minmax" diff --git a/gcc/testsuite/gcc.target/riscv/zbb-abs.c b/gcc/testsuite/gcc.target/riscv/zbb-abs.c new file mode 100644 index 00000000000..6ef7efdbd49 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/zbb-abs.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zbb" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABS(x) (((x) >= 0) ? (x) : -(x)) + +int +foo (int x) +{ + return ABS(x); +} + +/* { dg-final { scan-assembler-times "neg" 1 } } */ +/* { dg-final { scan-assembler-times "max" 1 } } */ +/* { dg-final { scan-assembler-not "sraiw" } } */ +/* { dg-final { scan-assembler-not "xor" } } */ +/* { dg-final { scan-assembler-not "subw" } } */ + diff --git a/gcc/testsuite/gcc.target/riscv/zbb-min-max-02.c b/gcc/testsuite/gcc.target/riscv/zbb-min-max-02.c index b462859f10f..b9db655d55d 100644 --- a/gcc/testsuite/gcc.target/riscv/zbb-min-max-02.c +++ b/gcc/testsuite/gcc.target/riscv/zbb-min-max-02.c @@ -9,6 +9,6 @@ int f(unsigned int* a) } /* { dg-final { scan-assembler-times "minu" 1 } } */ -/* { dg-final { scan-assembler-times "sext.w" 1 } } */ +/* { dg-final { scan-assembler-times "sext.w|addw" 1 } } */ /* { dg-final { scan-assembler-not "zext.w" } } */