From patchwork Tue Dec 20 12:23:23 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manolis Tsamis X-Patchwork-Id: 62188 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 32A0C3858298 for ; Tue, 20 Dec 2022 12:24:02 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mail-lf1-x12c.google.com (mail-lf1-x12c.google.com [IPv6:2a00:1450:4864:20::12c]) by sourceware.org (Postfix) with ESMTPS id 243F13858421 for ; Tue, 20 Dec 2022 12:23:42 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 243F13858421 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=vrull.eu Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=vrull.eu Received: by mail-lf1-x12c.google.com with SMTP id p36so18295092lfa.12 for ; Tue, 20 Dec 2022 04:23:42 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vrull.eu; s=google; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:from:to:cc:subject:date:message-id:reply-to; bh=HPOp6n+Smx3PXKHA/HxonpXqBP2WGhczMC7mTq1gg/U=; b=pQDFGLXoNrvFypYLApYioCmsXu7M33/4bYmhD6gtmWSfZPyPrJOd2hJioW6zuB/1GD JaKb49CT+tfYab2SRnWR1xVRT+sXMkRxIBNK+YcPamd4uH2S+BHRiiRrbHB1Jv09id9y C8j+FItbEDqtFQIlsnIHuimo0HWXtuJeW+k6AH+vEtZVs+VSwHxcwKiMdM/LC+konpNH S1C2Urumf4bsesk55Fai9qSYeHhAE1G1/7lDYCEMe6BZkX2s2Pq+Fbnk3XiHLpbpKa5Z GG5mZnIAX30jYG6Qgn6SIcZOzujf8uR6Mey7FqJY5wJtitFo+Mf5inVC49RkFUCjdHJy IGJQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=HPOp6n+Smx3PXKHA/HxonpXqBP2WGhczMC7mTq1gg/U=; b=laXEMnik1blD+bsi8+RI2mbHVbhqXwyIgoTRH+sHsKuUedDCsZrleX7GptR1uvWMoL LoZKnRe9YlCUJzd0XfPPmpAgdlGKwni9lASxqVjFGuTlhQRqMkXK03hNIJ4QU2W19Hqu aBSu62E0Mv4ZDVm0dJ9PJ0bW359HAISyIGbgH/o/kqLBXvxe6FsdTdpziQ4SH3zqR875 Pw8IpGaRhmNe82iRn4D0ImLr47DZnvynz4OrWuiJFSF8P2Ho4ll6sLb1hGrJkATPe9O/ 2jqcyebVTzmyAhVv7TYWXFVYtuaF4FlK3R/XeU5eVAmR0eFlyWSODAuLCioTEcngoiDZ +l0Q== X-Gm-Message-State: ANoB5pnRzFgEUxE2GKtzAuUUNL4bj/C0VunoAD8PACsZt42Ws6ylh19f CY3Im568otd0/OXc7rtYJK1mWV5G5NVZsouB X-Google-Smtp-Source: AA0mqf7EdpFAQbNBkxTB+o5F/4kTZs6Xc9ukBtJf+AIu438SzBVZRqmIKOkL5a3hz/kTX5fBwgbD+w== X-Received: by 2002:a05:6512:128e:b0:4a4:68b8:f4e5 with SMTP id u14-20020a056512128e00b004a468b8f4e5mr17183048lfs.43.1671539020144; Tue, 20 Dec 2022 04:23:40 -0800 (PST) Received: from helsinki-03.engr ([2a01:4f9:6b:2a47::2]) by smtp.gmail.com with ESMTPSA id a24-20020a056512201800b004b57a810e09sm1443877lfb.288.2022.12.20.04.23.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 20 Dec 2022 04:23:39 -0800 (PST) From: Manolis Tsamis To: gcc-patches@gcc.gnu.org Cc: Tamar Christina , Philipp Tomsich , Richard Biener , Christoph Muellner , jiangning.liu@amperecomputing.com, Manolis Tsamis Subject: [PATCH v3] Add pattern to convert vector shift + bitwise and + multiply to vector compare in some cases. Date: Tue, 20 Dec 2022 13:23:23 +0100 Message-Id: <20221220122323.3863293-1-manolis.tsamis@vrull.eu> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 X-Spam-Status: No, score=-12.0 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, JMQ_SPF_NEUTRAL, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" When using SWAR (SIMD in a register) techniques a comparison operation within such a register can be made by using a combination of shifts, bitwise and and multiplication. If code using this scheme is vectorized then there is potential to replace all these operations with a single vector comparison, by reinterpreting the vector types to match the width of the SWAR register. For example, for the test function packed_cmp_16_32, the original generated code is: ldr q0, [x0] add w1, w1, 1 ushr v0.4s, v0.4s, 15 and v0.16b, v0.16b, v2.16b shl v1.4s, v0.4s, 16 sub v0.4s, v1.4s, v0.4s str q0, [x0], 16 cmp w2, w1 bhi .L20 with this pattern the above can be optimized to: ldr q0, [x0] add w1, w1, 1 cmlt v0.8h, v0.8h, #0 str q0, [x0], 16 cmp w2, w1 bhi .L20 The effect is similar for x86-64. gcc/ChangeLog: * match.pd: Simplify vector shift + bit_and + multiply in some cases. gcc/testsuite/ChangeLog: * gcc.target/aarch64/swar_to_vec_cmp.c: New test. Signed-off-by: Manolis Tsamis --- Changes in v3: - Changed pattern to use vec_cond_expr. - Changed pattern to work with VLA vector. - Added both expand_vec_cmp_expr_p and expand_vec_cond_expr_p check. - Fixed type compatibility issues. gcc/match.pd | 61 ++++++++++++++++ .../gcc.target/aarch64/swar_to_vec_cmp.c | 72 +++++++++++++++++++ 2 files changed, 133 insertions(+) create mode 100644 gcc/testsuite/gcc.target/aarch64/swar_to_vec_cmp.c diff --git a/gcc/match.pd b/gcc/match.pd index 67a0a682f31..320437f8aa3 100644 --- a/gcc/match.pd +++ b/gcc/match.pd @@ -301,6 +301,67 @@ DEFINE_INT_AND_FLOAT_ROUND_FN (RINT) (view_convert (bit_and:itype (view_convert @0) (ne @1 { build_zero_cst (type); }))))))) +/* In SWAR (SIMD within a register) code a signed comparison of packed data + can be constructed with a particular combination of shift, bitwise and, + and multiplication by constants. If that code is vectorized we can + convert this pattern into a more efficient vector comparison. */ +(simplify + (mult (bit_and (rshift @0 uniform_integer_cst_p@1) + uniform_integer_cst_p@2) + uniform_integer_cst_p@3) + (with { + tree rshift_cst = uniform_integer_cst_p (@1); + tree bit_and_cst = uniform_integer_cst_p (@2); + tree mult_cst = uniform_integer_cst_p (@3); + } + /* Make sure we're working with vectors and uniform vector constants. */ + (if (VECTOR_TYPE_P (type) + && tree_fits_uhwi_p (rshift_cst) + && tree_fits_uhwi_p (mult_cst) + && tree_fits_uhwi_p (bit_and_cst)) + /* Compute what constants would be needed for this to represent a packed + comparison based on the shift amount denoted by RSHIFT_CST. */ + (with { + HOST_WIDE_INT vec_elem_bits = vector_element_bits (type); + poly_int64 vec_nelts = TYPE_VECTOR_SUBPARTS (type); + poly_int64 vec_bits = vec_elem_bits * vec_nelts; + unsigned HOST_WIDE_INT cmp_bits_i, bit_and_i, mult_i; + unsigned HOST_WIDE_INT target_mult_i, target_bit_and_i; + cmp_bits_i = tree_to_uhwi (rshift_cst) + 1; + mult_i = tree_to_uhwi (mult_cst); + target_mult_i = (HOST_WIDE_INT_1U << cmp_bits_i) - 1; + bit_and_i = tree_to_uhwi (bit_and_cst); + target_bit_and_i = 0; + + /* The bit pattern in BIT_AND_I should be a mask for the least + significant bit of each packed element that is CMP_BITS wide. */ + for (unsigned i = 0; i < vec_elem_bits / cmp_bits_i; i++) + target_bit_and_i = (target_bit_and_i << cmp_bits_i) | 1U; + } + (if ((exact_log2 (cmp_bits_i)) >= 0 + && cmp_bits_i < HOST_BITS_PER_WIDE_INT + && multiple_p (vec_bits, cmp_bits_i) + && vec_elem_bits <= HOST_BITS_PER_WIDE_INT + && target_mult_i == mult_i + && target_bit_and_i == bit_and_i) + /* Compute the vector shape for the comparison and check if the target is + able to expand the comparison with that type. */ + (with { + /* We're doing a signed comparison. */ + tree cmp_type = build_nonstandard_integer_type (cmp_bits_i, 0); + poly_int64 vector_type_nelts = exact_div (vec_bits, cmp_bits_i); + tree vec_cmp_type = build_vector_type (cmp_type, vector_type_nelts); + tree vec_truth_type = truth_type_for (vec_cmp_type); + tree zeros = build_zero_cst (vec_cmp_type); + tree ones = build_all_ones_cst (vec_cmp_type); + } + (if (expand_vec_cmp_expr_p (vec_cmp_type, vec_truth_type, LT_EXPR) + && expand_vec_cond_expr_p (vec_cmp_type, vec_truth_type, LT_EXPR)) + (view_convert:type (vec_cond (lt:vec_truth_type + (view_convert:vec_cmp_type @0) + { zeros; }) + { ones; } { zeros; }))))))))) + (for cmp (gt ge lt le) outp (convert convert negate negate) outn (negate negate convert convert) diff --git a/gcc/testsuite/gcc.target/aarch64/swar_to_vec_cmp.c b/gcc/testsuite/gcc.target/aarch64/swar_to_vec_cmp.c new file mode 100644 index 00000000000..26f9ad9ef28 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/swar_to_vec_cmp.c @@ -0,0 +1,72 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -ftree-vectorize" } */ + +typedef unsigned char uint8_t; +typedef unsigned short uint16_t; +typedef unsigned int uint32_t; + +/* 8-bit SWAR tests. */ + +static uint8_t packed_cmp_8_8(uint8_t a) +{ + return ((a >> 7) & 0x1U) * 0xffU; +} + +/* 16-bit SWAR tests. */ + +static uint16_t packed_cmp_8_16(uint16_t a) +{ + return ((a >> 7) & 0x101U) * 0xffU; +} + +static uint16_t packed_cmp_16_16(uint16_t a) +{ + return ((a >> 15) & 0x1U) * 0xffffU; +} + +/* 32-bit SWAR tests. */ + +static uint32_t packed_cmp_8_32(uint32_t a) +{ + return ((a >> 7) & 0x1010101U) * 0xffU; +} + +static uint32_t packed_cmp_16_32(uint32_t a) +{ + return ((a >> 15) & 0x10001U) * 0xffffU; +} + +static uint32_t packed_cmp_32_32(uint32_t a) +{ + return ((a >> 31) & 0x1U) * 0xffffffffU; +} + +/* Driver function to test the vectorized code generated for the different + packed_cmp variants. */ + +#define VECTORIZED_PACKED_CMP(T, FUNC) \ + void vectorized_cmp_##FUNC(T* a, int n) \ + { \ + n = (n / 32) * 32; \ + for(int i = 0; i < n; i += 4) \ + { \ + a[i + 0] = FUNC(a[i + 0]); \ + a[i + 1] = FUNC(a[i + 1]); \ + a[i + 2] = FUNC(a[i + 2]); \ + a[i + 3] = FUNC(a[i + 3]); \ + } \ + } + +VECTORIZED_PACKED_CMP(uint8_t, packed_cmp_8_8); + +VECTORIZED_PACKED_CMP(uint16_t, packed_cmp_8_16); +VECTORIZED_PACKED_CMP(uint16_t, packed_cmp_16_16); + +VECTORIZED_PACKED_CMP(uint32_t, packed_cmp_8_32); +VECTORIZED_PACKED_CMP(uint32_t, packed_cmp_16_32); +VECTORIZED_PACKED_CMP(uint32_t, packed_cmp_32_32); + +/* { dg-final { scan-assembler {\tcmlt\t} } } */ +/* { dg-final { scan-assembler-not {\tushr\t} } } */ +/* { dg-final { scan-assembler-not {\tshl\t} } } */ +/* { dg-final { scan-assembler-not {\tmul\t} } } */