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[62.178.148.172]) by smtp.gmail.com with ESMTPSA id eg53-20020a05640228b500b0044dbecdcd29sm3744648edb.12.2022.12.18.17.08.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 18 Dec 2022 17:08:44 -0800 (PST) From: Christoph Muellner To: gcc-patches@gcc.gnu.org, Kito Cheng , Jim Wilson , Palmer Dabbelt , Andrew Waterman , Philipp Tomsich , Jeff Law , Cooper Qu , Lifang Xia , Yunhai Shang , Zhiwei Liu Cc: =?utf-8?q?Christoph_M=C3=BCllner?= Subject: [PATCH v2 02/11] riscv: Restructure callee-saved register save/restore code Date: Mon, 19 Dec 2022 02:08:29 +0100 Message-Id: <20221219010838.3878675-3-christoph.muellner@vrull.eu> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221219010838.3878675-1-christoph.muellner@vrull.eu> References: <20221219010838.3878675-1-christoph.muellner@vrull.eu> MIME-Version: 1.0 X-Spam-Status: No, score=-12.5 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, JMQ_SPF_NEUTRAL, KAM_MANYTO, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" From: Christoph Müllner This patch restructures the loop over the GP registers which saves/restores then as part of the prologue/epilogue. No functional change is intended by this patch, but it offers the possibility to use load-pair/store-pair instructions. gcc/ChangeLog: * config/riscv/riscv.cc (riscv_next_saved_reg): New function. (riscv_is_eh_return_data_register): New function. (riscv_for_each_saved_reg): Restructure loop. Signed-off-by: Christoph Müllner --- gcc/config/riscv/riscv.cc | 94 +++++++++++++++++++++++++++------------ 1 file changed, 66 insertions(+), 28 deletions(-) diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index 6dd2ab2d11e..a8d5e1dac7f 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -4835,6 +4835,49 @@ riscv_save_restore_reg (machine_mode mode, int regno, fn (gen_rtx_REG (mode, regno), mem); } +/* Return the next register up from REGNO up to LIMIT for the callee + to save or restore. OFFSET will be adjusted accordingly. + If INC is set, then REGNO will be incremented first. */ + +static unsigned int +riscv_next_saved_reg (unsigned int regno, unsigned int limit, + HOST_WIDE_INT *offset, bool inc = true) +{ + if (inc) + regno++; + + while (regno <= limit) + { + if (BITSET_P (cfun->machine->frame.mask, regno - GP_REG_FIRST)) + { + *offset = *offset - UNITS_PER_WORD; + break; + } + + regno++; + } + return regno; +} + +/* Return TRUE if provided REGNO is eh return data register. */ + +static bool +riscv_is_eh_return_data_register (unsigned int regno) +{ + unsigned int i, regnum; + + if (!crtl->calls_eh_return) + return false; + + for (i = 0; (regnum = EH_RETURN_DATA_REGNO (i)) != INVALID_REGNUM; i++) + if (regno == regnum) + { + return true; + } + + return false; +} + /* Call FN for each register that is saved by the current function. SP_OFFSET is the offset of the current stack pointer from the start of the frame. */ @@ -4844,36 +4887,31 @@ riscv_for_each_saved_reg (poly_int64 sp_offset, riscv_save_restore_fn fn, bool epilogue, bool maybe_eh_return) { HOST_WIDE_INT offset; + unsigned int regno; + unsigned int start = GP_REG_FIRST; + unsigned int limit = GP_REG_LAST; /* Save the link register and s-registers. */ - offset = (cfun->machine->frame.gp_sp_offset - sp_offset).to_constant (); - for (unsigned int regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++) - if (BITSET_P (cfun->machine->frame.mask, regno - GP_REG_FIRST)) - { - bool handle_reg = !cfun->machine->reg_is_wrapped_separately[regno]; - - /* If this is a normal return in a function that calls the eh_return - builtin, then do not restore the eh return data registers as that - would clobber the return value. But we do still need to save them - in the prologue, and restore them for an exception return, so we - need special handling here. */ - if (epilogue && !maybe_eh_return && crtl->calls_eh_return) - { - unsigned int i, regnum; - - for (i = 0; (regnum = EH_RETURN_DATA_REGNO (i)) != INVALID_REGNUM; - i++) - if (regno == regnum) - { - handle_reg = FALSE; - break; - } - } - - if (handle_reg) - riscv_save_restore_reg (word_mode, regno, offset, fn); - offset -= UNITS_PER_WORD; - } + offset = (cfun->machine->frame.gp_sp_offset - sp_offset).to_constant () + + UNITS_PER_WORD; + for (regno = riscv_next_saved_reg (start, limit, &offset, false); + regno <= limit; + regno = riscv_next_saved_reg (regno, limit, &offset)) + { + if (cfun->machine->reg_is_wrapped_separately[regno]) + continue; + + /* If this is a normal return in a function that calls the eh_return + builtin, then do not restore the eh return data registers as that + would clobber the return value. But we do still need to save them + in the prologue, and restore them for an exception return, so we + need special handling here. */ + if (epilogue && !maybe_eh_return + && riscv_is_eh_return_data_register (regno)) + continue; + + riscv_save_restore_reg (word_mode, regno, offset, fn); + } /* This loop must iterate over the same space as its companion in riscv_compute_frame_info. */