From patchwork Fri Dec 9 18:25:10 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Raphael Moreira Zinsly X-Patchwork-Id: 61734 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 5427A383AB64 for ; Fri, 9 Dec 2022 18:25:37 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mail-oo1-xc30.google.com (mail-oo1-xc30.google.com [IPv6:2607:f8b0:4864:20::c30]) by sourceware.org (Postfix) with ESMTPS id 7713B3855147 for ; Fri, 9 Dec 2022 18:25:19 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 7713B3855147 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=ventanamicro.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=ventanamicro.com Received: by mail-oo1-xc30.google.com with SMTP id f7-20020a4a8907000000b004a0cb08d0afso799446ooi.8 for ; Fri, 09 Dec 2022 10:25:19 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:from:to:cc:subject:date:message-id:reply-to; bh=P19rAcUO64S9ikrZlMLV/x0snTPpakjcpp2yDHUuNZA=; b=lqbKHkKGAw95SYAnDmfz4dPmKqJQ/z0XGOPUA1WNWqATwAx5zpYShTj6LFm9BqBYNF /X+ku+GKvI/ALVNR4lVaR2PuKWqoZStbexNe45QqzYvlxaTR3MT6HIrGE2g4brBh6vL7 fSJ+ygmLNUvXVZoYAoF+lAZ7iW59THGUn+5lnS8lPrI+dbrhhTwtyompsabXnetPn9Lv R/0SZX1riF4M8j7sAbOhHqkA8erF6JVq4KUhDzNeKfxWb2cbrRqvCJDlcci2izNS5f5X CRALg/lle8ZUla7PpjFLIAsZFv8AopzKbGzPURPJp0FhPL3abXJx8oFMEPXZQJ3vjXFv CZZA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=P19rAcUO64S9ikrZlMLV/x0snTPpakjcpp2yDHUuNZA=; b=0Dad63AqclDcVvUCwCjwdMXZdVzKCBWhS0dLVftNteaHuktgEASkGlD2MqVGAVl+Oe MmuRIHKPJ2JTTQ1O3vkek9oUInB/WT6Ko64xQ6j21cwzxoh84bUh9VkCbsd7y2odif0c 3s2ZWYxVBfKjv8JCnA8SajHbkQmTcVqiPbggGqtbWBJHnplQqakhlt7PqgJtzdh6ALT5 9/X48qCDg9gknuGlYVhTBJ9KUJd1+pq99zCY4D7vpL4gNuxdxqVIEfvEmQ2VUXwfgvip GCdh0z60nRZ4kFix6ZKKCsh4UKIUifl41kfp0wbBEkTnGvvMWV+WpBmiEjb3hxAwfSuw ok9A== X-Gm-Message-State: ANoB5pl782uI5DGjram0LjWQoAMAqcII37ax7w/LPNDm8U//UqV9t6ET Q2mUEVWu0AWtLpajjV2fSJshp9GnQG94AnZ8 X-Google-Smtp-Source: AA0mqf6pZNcJQBSeSxTQq0wE5FPoEiozF6No3v/6Xaw6DomTfoQbPERLCjeOJ8JbQZtpKvoTN34cWg== X-Received: by 2002:a4a:e8cc:0:b0:4a3:78f9:1cb1 with SMTP id h12-20020a4ae8cc000000b004a378f91cb1mr2940099ooe.4.1670610318446; Fri, 09 Dec 2022 10:25:18 -0800 (PST) Received: from marvin.dc1.ventanamicro.com ([2804:14d:baa4:50a9::1000]) by smtp.gmail.com with ESMTPSA id c12-20020a4aaccc000000b004a0b424f99dsm649459oon.43.2022.12.09.10.25.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 09 Dec 2022 10:25:17 -0800 (PST) From: Raphael Moreira Zinsly To: gcc-patches@gcc.gnu.org Cc: jlaw@ventanamicro.com, jakub@redhat.com, palmer@dabbelt.com, philipp.tomsich@vrull.eu, Raphael Moreira Zinsly Subject: [PATCH v2] RISC-V: Produce better code with complex constants [PR95632] [PR106602] Date: Fri, 9 Dec 2022 15:25:10 -0300 Message-Id: <20221209182510.43515-1-rzinsly@ventanamicro.com> X-Mailer: git-send-email 2.38.1 MIME-Version: 1.0 X-Spam-Status: No, score=-13.9 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" Changes since v1: - Fixed formatting issues. - Added a name to the define_insn_and_split pattern. - Set the target on the 'dg-do compile' in pr106602.c. - Removed the rv32 restriction in pr95632.c. -- >8 -- Due to RISC-V limitations on operations with big constants combine is failing to match such operations and is not being able to produce optimal code as it keeps splitting them. By pretending we can do those operations we can get more opportunities for simplification of surrounding instructions. 2022-12-06 Raphael Moreira Zinsly Jeff Law gcc/Changelog: PR target/95632 PR target/106602 * config/riscv/riscv.md: New pattern to simulate complex const_int loads. gcc/testsuite/ChangeLog: * gcc.target/riscv/pr95632.c: New test. * gcc.target/riscv/pr106602.c: New test. --- gcc/config/riscv/riscv.md | 15 +++++++++++++++ gcc/testsuite/gcc.target/riscv/pr106602.c | 14 ++++++++++++++ gcc/testsuite/gcc.target/riscv/pr95632.c | 15 +++++++++++++++ 3 files changed, 44 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/pr106602.c create mode 100644 gcc/testsuite/gcc.target/riscv/pr95632.c diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md index df57e2b0b4a..b0daa4b19eb 100644 --- a/gcc/config/riscv/riscv.md +++ b/gcc/config/riscv/riscv.md @@ -1667,6 +1667,21 @@ MAX_MACHINE_MODE, &operands[3], TRUE); }) +;; Pretend to have the ability to load complex const_int in order to get +;; better code generation around them. +(define_insn_and_split "*mvconst_internal" + [(set (match_operand:GPR 0 "register_operand" "=r") + (match_operand:GPR 1 "splittable_const_int_operand" "i"))] + "cse_not_expected" + "#" + "&& 1" + [(const_int 0)] +{ + riscv_move_integer (operands[0], operands[0], INTVAL (operands[1]), + mode, TRUE); + DONE; +}) + ;; 64-bit integer moves (define_expand "movdi" diff --git a/gcc/testsuite/gcc.target/riscv/pr106602.c b/gcc/testsuite/gcc.target/riscv/pr106602.c new file mode 100644 index 00000000000..825b1a143b5 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/pr106602.c @@ -0,0 +1,14 @@ +/* { dg-do compile { target { riscv64*-*-* } } } */ +/* { dg-options "-O2" } */ + +unsigned long +foo2 (unsigned long a) +{ + return (unsigned long)(unsigned int) a << 6; +} + +/* { dg-final { scan-assembler-times "slli\t" 1 } } */ +/* { dg-final { scan-assembler-times "srli\t" 1 } } */ +/* { dg-final { scan-assembler-not "\tli\t" } } */ +/* { dg-final { scan-assembler-not "addi\t" } } */ +/* { dg-final { scan-assembler-not "and\t" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/pr95632.c b/gcc/testsuite/gcc.target/riscv/pr95632.c new file mode 100644 index 00000000000..b865c2f2e97 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/pr95632.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +unsigned short +foo (unsigned short crc) +{ + crc ^= 0x4002; + crc >>= 1; + crc |= 0x8000; + + return crc; +} + +/* { dg-final { scan-assembler-times "srli\t" 1 } } */ +/* { dg-final { scan-assembler-not "slli\t" } } */