diff mbox series

[v2] RISC-V: Produce better code with complex constants [PR95632] [PR106602]

Message ID 20221209182510.43515-1-rzinsly@ventanamicro.com
State Deferred, archived
Headers
Series [v2] RISC-V: Produce better code with complex constants [PR95632] [PR106602] |

Commit Message

Raphael Moreira Zinsly Dec. 9, 2022, 6:25 p.m. UTC 
  Changes since v1:
	- Fixed formatting issues.
	- Added a name to the define_insn_and_split pattern.
	- Set the target on the 'dg-do compile' in pr106602.c.
	- Removed the rv32 restriction in pr95632.c.

-- >8 --

Due to RISC-V limitations on operations with big constants combine
is failing to match such operations and is not being able to
produce optimal code as it keeps splitting them.  By pretending we
can do those operations we can get more opportunities for
simplification of surrounding instructions.

2022-12-06  Raphael Moreira Zinsly  <rzinsly@ventanamicro.com>
	    Jeff Law  <jlaw@ventanamicro.com>

gcc/Changelog:
	PR target/95632
	PR target/106602
	* config/riscv/riscv.md: New pattern to simulate complex
	const_int loads.

gcc/testsuite/ChangeLog:
	* gcc.target/riscv/pr95632.c: New test.
	* gcc.target/riscv/pr106602.c: New test.
---
 gcc/config/riscv/riscv.md                 | 15 +++++++++++++++
 gcc/testsuite/gcc.target/riscv/pr106602.c | 14 ++++++++++++++
 gcc/testsuite/gcc.target/riscv/pr95632.c  | 15 +++++++++++++++
 3 files changed, 44 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/riscv/pr106602.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/pr95632.c

Comments

Jeff Law Dec. 16, 2022, 5:19 p.m. UTC | #1 
On 12/9/22 11:25, Raphael Moreira Zinsly wrote:
> Changes since v1:
> 	- Fixed formatting issues.
> 	- Added a name to the define_insn_and_split pattern.
> 	- Set the target on the 'dg-do compile' in pr106602.c.
> 	- Removed the rv32 restriction in pr95632.c.
> 
> -- >8 --
> 
> Due to RISC-V limitations on operations with big constants combine
> is failing to match such operations and is not being able to
> produce optimal code as it keeps splitting them.  By pretending we
> can do those operations we can get more opportunities for
> simplification of surrounding instructions.
> 
> 2022-12-06  Raphael Moreira Zinsly  <rzinsly@ventanamicro.com>
> 	    Jeff Law  <jlaw@ventanamicro.com>
> 
> gcc/Changelog:
> 	PR target/95632
> 	PR target/106602
> 	* config/riscv/riscv.md: New pattern to simulate complex
> 	const_int loads.
> 
> gcc/testsuite/ChangeLog:
> 	* gcc.target/riscv/pr95632.c: New test.
> 	* gcc.target/riscv/pr106602.c: New test.
So I was doing a bit of testing around this.  I think we need we're 
going to need a v3.

The problem is at -O1 several passes do not run.  In particular the 
post-loop CSE pass isn't run.  That causes cse_not_expected to be set 
earlier in the pipeline which in turn means the new pattern is exposed 
to fwprop -- too early IMHO and with more potential to cause minor 
regressions as can be seen with riscv/load-immediate.c

Given that bridge patterns are fairly standard and that combining, then 
resplitting has also become relatively standard (particularly for 
eliminating some data dependencies and late lowering) having a state 
variable to indicate that combine has started and such patterns should 
be exposed seems sensible.

An alternate approach would be to do something more hackish like adding 
&& flag_rerun_cse_after_loop to the condition.  That's better than what 
we do now, but not as accurate as biting the bullet and making a state 
variable for combine.

I'll cobble something together and test it.  It'll require a wider test 
because it'll touch target independent files.

Jeff
Jeff Law Dec. 27, 2022, 11:32 p.m. UTC | #2 
On 12/9/22 11:25, Raphael Moreira Zinsly wrote:
> Changes since v1:
> 	- Fixed formatting issues.
> 	- Added a name to the define_insn_and_split pattern.
> 	- Set the target on the 'dg-do compile' in pr106602.c.
> 	- Removed the rv32 restriction in pr95632.c.
> 
> -- >8 --
> 
> Due to RISC-V limitations on operations with big constants combine
> is failing to match such operations and is not being able to
> produce optimal code as it keeps splitting them.  By pretending we
> can do those operations we can get more opportunities for
> simplification of surrounding instructions.
> 
> 2022-12-06  Raphael Moreira Zinsly  <rzinsly@ventanamicro.com>
> 	    Jeff Law  <jlaw@ventanamicro.com>
> 
> gcc/Changelog:
> 	PR target/95632
> 	PR target/106602
> 	* config/riscv/riscv.md: New pattern to simulate complex
> 	const_int loads.
> 
> gcc/testsuite/ChangeLog:
> 	* gcc.target/riscv/pr95632.c: New test.
> 	* gcc.target/riscv/pr106602.c: New test.
Here's the final version of the patch that addresses these two BZs.

This version tightens slightly the condition for the new pattern so that 
it doesn't match two special cases.

In particular, we avoid certain constants which are used in 
define_splits where the constant load feeds a logical AND which can 
ultimately be implemented via a pair of shifts.

Those cases are 3->2 splits on the trunk.  If we allowed those constants 
in the new pattern, then we'd need to support 2->2 splits in combine.c 
which is a non-starter.

Bootstrapped and regression tested on riscv64-linux-gnu.  I also 
compared resultant assembly code with/without this change for all the 
source files in the compiler natively to look for further regressions.

Committed to the trunk,
Jeff
commit 2e886eef7f2b5aadb00171af868f0895b647c3a4
Author: Raphael Moreira Zinsly <rzinsly@ventanamicro.com>
Date:   Tue Dec 27 18:29:25 2022 -0500

    RISC-V: Produce better code with complex constants [PR95632] [PR106602]
    
    gcc/Changelog:
            PR target/95632
            PR target/106602
            * config/riscv/riscv.md: New pattern to simulate complex
            const_int loads.
    
    gcc/testsuite/ChangeLog:
            * gcc.target/riscv/pr95632.c: New test.
            * gcc.target/riscv/pr106602.c: New test.

diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index a8bb331f25c..020833b9206 100644
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -1670,6 +1670,23 @@ (define_split
 		      MAX_MACHINE_MODE, &operands[3], TRUE);
 })
 
+;; Pretend to have the ability to load complex const_int in order to get
+;; better code generation around them.
+;;
+;; But avoid constants that are special cased elsewhere.
+(define_insn_and_split "*mvconst_internal"
+  [(set (match_operand:GPR 0 "register_operand" "=r")
+        (match_operand:GPR 1 "splittable_const_int_operand" "i"))]
+  "!(p2m1_shift_operand (operands[1]) || high_mask_shift_operand (operands[1]))"
+  "#"
+  "&& 1"
+  [(const_int 0)]
+{
+  riscv_move_integer (operands[0], operands[0], INTVAL (operands[1]),
+                      <MODE>mode, TRUE);
+  DONE;
+})
+
 ;; 64-bit integer moves
 
 (define_expand "movdi"
diff --git a/gcc/testsuite/gcc.target/riscv/pr106602.c b/gcc/testsuite/gcc.target/riscv/pr106602.c
new file mode 100644
index 00000000000..825b1a143b5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/pr106602.c
@@ -0,0 +1,14 @@
+/* { dg-do compile { target { riscv64*-*-* } } } */
+/* { dg-options "-O2" } */
+
+unsigned long
+foo2 (unsigned long a)
+{
+  return (unsigned long)(unsigned int) a << 6;
+}
+
+/* { dg-final { scan-assembler-times "slli\t" 1 } } */
+/* { dg-final { scan-assembler-times "srli\t" 1 } } */
+/* { dg-final { scan-assembler-not "\tli\t" } } */
+/* { dg-final { scan-assembler-not "addi\t" } } */
+/* { dg-final { scan-assembler-not "and\t" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/pr95632.c b/gcc/testsuite/gcc.target/riscv/pr95632.c
new file mode 100644
index 00000000000..b865c2f2e97
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/pr95632.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+unsigned short
+foo (unsigned short crc)
+{
+  crc ^= 0x4002;
+  crc >>= 1;
+  crc |= 0x8000;
+
+  return crc;
+}
+
+/* { dg-final { scan-assembler-times "srli\t" 1 } } */
+/* { dg-final { scan-assembler-not "slli\t" } } */
Andrew Pinski Feb. 23, 2023, 9:23 p.m. UTC | #3 
On Fri, Dec 9, 2022 at 10:25 AM Raphael Moreira Zinsly
<rzinsly@ventanamicro.com> wrote:
>
> Changes since v1:
>         - Fixed formatting issues.
>         - Added a name to the define_insn_and_split pattern.
>         - Set the target on the 'dg-do compile' in pr106602.c.
>         - Removed the rv32 restriction in pr95632.c.
>
> -- >8 --
>
> Due to RISC-V limitations on operations with big constants combine
> is failing to match such operations and is not being able to
> produce optimal code as it keeps splitting them.  By pretending we
> can do those operations we can get more opportunities for
> simplification of surrounding instructions.
>
> 2022-12-06  Raphael Moreira Zinsly  <rzinsly@ventanamicro.com>
>             Jeff Law  <jlaw@ventanamicro.com>
>
> gcc/Changelog:
>         PR target/95632
>         PR target/106602
>         * config/riscv/riscv.md: New pattern to simulate complex
>         const_int loads.
>
> gcc/testsuite/ChangeLog:
>         * gcc.target/riscv/pr95632.c: New test.
>         * gcc.target/riscv/pr106602.c: New test.
> ---
>  gcc/config/riscv/riscv.md                 | 15 +++++++++++++++
>  gcc/testsuite/gcc.target/riscv/pr106602.c | 14 ++++++++++++++
>  gcc/testsuite/gcc.target/riscv/pr95632.c  | 15 +++++++++++++++
>  3 files changed, 44 insertions(+)
>  create mode 100644 gcc/testsuite/gcc.target/riscv/pr106602.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/pr95632.c
>
> diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
> index df57e2b0b4a..b0daa4b19eb 100644
> --- a/gcc/config/riscv/riscv.md
> +++ b/gcc/config/riscv/riscv.md
> @@ -1667,6 +1667,21 @@
>                       MAX_MACHINE_MODE, &operands[3], TRUE);
>  })
>
> +;; Pretend to have the ability to load complex const_int in order to get
> +;; better code generation around them.
> +(define_insn_and_split "*mvconst_internal"
> +  [(set (match_operand:GPR 0 "register_operand" "=r")
> +    (match_operand:GPR 1 "splittable_const_int_operand" "i"))]
> +  "cse_not_expected"

This is just way broken. This should be combined with the normal move
instructions and just be a define_split.
See PR 108892 for a testcase which shows this breaking how the
register allocator thinks it should work.

Thanks,
Andrew

> +  "#"
> +  "&& 1"
> +  [(const_int 0)]
> +{
> +  riscv_move_integer (operands[0], operands[0], INTVAL (operands[1]),
> +                     <MODE>mode, TRUE);
> +  DONE;
> +})
> +
>  ;; 64-bit integer moves
>
>  (define_expand "movdi"
> diff --git a/gcc/testsuite/gcc.target/riscv/pr106602.c b/gcc/testsuite/gcc.target/riscv/pr106602.c
> new file mode 100644
> index 00000000000..825b1a143b5
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/pr106602.c
> @@ -0,0 +1,14 @@
> +/* { dg-do compile { target { riscv64*-*-* } } } */
> +/* { dg-options "-O2" } */
> +
> +unsigned long
> +foo2 (unsigned long a)
> +{
> +  return (unsigned long)(unsigned int) a << 6;
> +}
> +
> +/* { dg-final { scan-assembler-times "slli\t" 1 } } */
> +/* { dg-final { scan-assembler-times "srli\t" 1 } } */
> +/* { dg-final { scan-assembler-not "\tli\t" } } */
> +/* { dg-final { scan-assembler-not "addi\t" } } */
> +/* { dg-final { scan-assembler-not "and\t" } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/pr95632.c b/gcc/testsuite/gcc.target/riscv/pr95632.c
> new file mode 100644
> index 00000000000..b865c2f2e97
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/pr95632.c
> @@ -0,0 +1,15 @@
> +/* { dg-do compile } */
> +/* { dg-options "-O2" } */
> +
> +unsigned short
> +foo (unsigned short crc)
> +{
> +  crc ^= 0x4002;
> +  crc >>= 1;
> +  crc |= 0x8000;
> +
> +  return crc;
> +}
> +
> +/* { dg-final { scan-assembler-times "srli\t" 1 } } */
> +/* { dg-final { scan-assembler-not "slli\t" } } */
> --
> 2.38.1
>
Jeff Law March 5, 2023, 6:13 p.m. UTC | #4 
On 2/23/23 14:23, Andrew Pinski via Gcc-patches wrote:
> On Fri, Dec 9, 2022 at 10:25 AM Raphael Moreira Zinsly
> <rzinsly@ventanamicro.com> wrote:
>>
>> Changes since v1:
>>          - Fixed formatting issues.
>>          - Added a name to the define_insn_and_split pattern.
>>          - Set the target on the 'dg-do compile' in pr106602.c.
>>          - Removed the rv32 restriction in pr95632.c.
>>
>> -- >8 --
>>
>> Due to RISC-V limitations on operations with big constants combine
>> is failing to match such operations and is not being able to
>> produce optimal code as it keeps splitting them.  By pretending we
>> can do those operations we can get more opportunities for
>> simplification of surrounding instructions.
>>
>> 2022-12-06  Raphael Moreira Zinsly  <rzinsly@ventanamicro.com>
>>              Jeff Law  <jlaw@ventanamicro.com>
>>
>> gcc/Changelog:
>>          PR target/95632
>>          PR target/106602
>>          * config/riscv/riscv.md: New pattern to simulate complex
>>          const_int loads.
>>
>> gcc/testsuite/ChangeLog:
>>          * gcc.target/riscv/pr95632.c: New test.
>>          * gcc.target/riscv/pr106602.c: New test.
>> ---
>>   gcc/config/riscv/riscv.md                 | 15 +++++++++++++++
>>   gcc/testsuite/gcc.target/riscv/pr106602.c | 14 ++++++++++++++
>>   gcc/testsuite/gcc.target/riscv/pr95632.c  | 15 +++++++++++++++
>>   3 files changed, 44 insertions(+)
>>   create mode 100644 gcc/testsuite/gcc.target/riscv/pr106602.c
>>   create mode 100644 gcc/testsuite/gcc.target/riscv/pr95632.c
>>
>> diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
>> index df57e2b0b4a..b0daa4b19eb 100644
>> --- a/gcc/config/riscv/riscv.md
>> +++ b/gcc/config/riscv/riscv.md
>> @@ -1667,6 +1667,21 @@
>>                        MAX_MACHINE_MODE, &operands[3], TRUE);
>>   })
>>
>> +;; Pretend to have the ability to load complex const_int in order to get
>> +;; better code generation around them.
>> +(define_insn_and_split "*mvconst_internal"
>> +  [(set (match_operand:GPR 0 "register_operand" "=r")
>> +    (match_operand:GPR 1 "splittable_const_int_operand" "i"))]
>> +  "cse_not_expected"
> 
> This is just way broken. This should be combined with the normal move
> instructions and just be a define_split.
> See PR 108892 for a testcase which shows this breaking how the
> register allocator thinks it should work.
I'm pretty sure that won't work.  You need them exposed as a define_insn 
so that they can act as a bridge pattern for combine.  You don't want to 
expose before combine as that'll regress things in a variety of other 
ways.  You don't want the bridge form to survive after splitting.  Hence 
define_insn_and_split.

I haven't looked at that bug in detail, but Raphael and I certainly will.

jeff
Andrew Pinski March 5, 2023, 7:03 p.m. UTC | #5 
On Sun, Mar 5, 2023 at 10:14 AM Jeff Law via Gcc-patches
<gcc-patches@gcc.gnu.org> wrote:
>
>
>
> On 2/23/23 14:23, Andrew Pinski via Gcc-patches wrote:
> > On Fri, Dec 9, 2022 at 10:25 AM Raphael Moreira Zinsly
> > <rzinsly@ventanamicro.com> wrote:
> >>
> >> Changes since v1:
> >>          - Fixed formatting issues.
> >>          - Added a name to the define_insn_and_split pattern.
> >>          - Set the target on the 'dg-do compile' in pr106602.c.
> >>          - Removed the rv32 restriction in pr95632.c.
> >>
> >> -- >8 --
> >>
> >> Due to RISC-V limitations on operations with big constants combine
> >> is failing to match such operations and is not being able to
> >> produce optimal code as it keeps splitting them.  By pretending we
> >> can do those operations we can get more opportunities for
> >> simplification of surrounding instructions.
> >>
> >> 2022-12-06  Raphael Moreira Zinsly  <rzinsly@ventanamicro.com>
> >>              Jeff Law  <jlaw@ventanamicro.com>
> >>
> >> gcc/Changelog:
> >>          PR target/95632
> >>          PR target/106602
> >>          * config/riscv/riscv.md: New pattern to simulate complex
> >>          const_int loads.
> >>
> >> gcc/testsuite/ChangeLog:
> >>          * gcc.target/riscv/pr95632.c: New test.
> >>          * gcc.target/riscv/pr106602.c: New test.
> >> ---
> >>   gcc/config/riscv/riscv.md                 | 15 +++++++++++++++
> >>   gcc/testsuite/gcc.target/riscv/pr106602.c | 14 ++++++++++++++
> >>   gcc/testsuite/gcc.target/riscv/pr95632.c  | 15 +++++++++++++++
> >>   3 files changed, 44 insertions(+)
> >>   create mode 100644 gcc/testsuite/gcc.target/riscv/pr106602.c
> >>   create mode 100644 gcc/testsuite/gcc.target/riscv/pr95632.c
> >>
> >> diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
> >> index df57e2b0b4a..b0daa4b19eb 100644
> >> --- a/gcc/config/riscv/riscv.md
> >> +++ b/gcc/config/riscv/riscv.md
> >> @@ -1667,6 +1667,21 @@
> >>                        MAX_MACHINE_MODE, &operands[3], TRUE);
> >>   })
> >>
> >> +;; Pretend to have the ability to load complex const_int in order to get
> >> +;; better code generation around them.
> >> +(define_insn_and_split "*mvconst_internal"
> >> +  [(set (match_operand:GPR 0 "register_operand" "=r")
> >> +    (match_operand:GPR 1 "splittable_const_int_operand" "i"))]
> >> +  "cse_not_expected"
> >
> > This is just way broken. This should be combined with the normal move
> > instructions and just be a define_split.
> > See PR 108892 for a testcase which shows this breaking how the
> > register allocator thinks it should work.
> I'm pretty sure that won't work.  You need them exposed as a define_insn
> so that they can act as a bridge pattern for combine.  You don't want to
> expose before combine as that'll regress things in a variety of other
> ways.  You don't want the bridge form to survive after splitting.  Hence
> define_insn_and_split.
>
> I haven't looked at that bug in detail, but Raphael and I certainly will.

So the register allocator does not know how to handle if there are two
different patterns which are to be used but differ by
constraints/predicats. This is especially true for mov instructions
which this is.
What I am saying is the "*movdi_64bit" and "*movsi_internal" patterns
should handle the same instruction as the above and still have a
define_split.

Take a look at how aarch64 handles this here. It has one pattern for
the move but it is a define_insn_and_split still. This is explicitly
to handle the case you are doing really.
"*movsi_aarch64" and "*movdi_aarch64" .

Thanks,
Andrew Pinski


>
> jeff
Jeff Law March 5, 2023, 7:07 p.m. UTC | #6 
On 3/5/23 12:03, Andrew Pinski wrote:
> On Sun, Mar 5, 2023 at 10:14 AM Jeff Law via Gcc-patches
> <gcc-patches@gcc.gnu.org> wrote:
>>
>>
>>
>> On 2/23/23 14:23, Andrew Pinski via Gcc-patches wrote:
>>> On Fri, Dec 9, 2022 at 10:25 AM Raphael Moreira Zinsly
>>> <rzinsly@ventanamicro.com> wrote:
>>>>
>>>> Changes since v1:
>>>>           - Fixed formatting issues.
>>>>           - Added a name to the define_insn_and_split pattern.
>>>>           - Set the target on the 'dg-do compile' in pr106602.c.
>>>>           - Removed the rv32 restriction in pr95632.c.
>>>>
>>>> -- >8 --
>>>>
>>>> Due to RISC-V limitations on operations with big constants combine
>>>> is failing to match such operations and is not being able to
>>>> produce optimal code as it keeps splitting them.  By pretending we
>>>> can do those operations we can get more opportunities for
>>>> simplification of surrounding instructions.
>>>>
>>>> 2022-12-06  Raphael Moreira Zinsly  <rzinsly@ventanamicro.com>
>>>>               Jeff Law  <jlaw@ventanamicro.com>
>>>>
>>>> gcc/Changelog:
>>>>           PR target/95632
>>>>           PR target/106602
>>>>           * config/riscv/riscv.md: New pattern to simulate complex
>>>>           const_int loads.
>>>>
>>>> gcc/testsuite/ChangeLog:
>>>>           * gcc.target/riscv/pr95632.c: New test.
>>>>           * gcc.target/riscv/pr106602.c: New test.
>>>> ---
>>>>    gcc/config/riscv/riscv.md                 | 15 +++++++++++++++
>>>>    gcc/testsuite/gcc.target/riscv/pr106602.c | 14 ++++++++++++++
>>>>    gcc/testsuite/gcc.target/riscv/pr95632.c  | 15 +++++++++++++++
>>>>    3 files changed, 44 insertions(+)
>>>>    create mode 100644 gcc/testsuite/gcc.target/riscv/pr106602.c
>>>>    create mode 100644 gcc/testsuite/gcc.target/riscv/pr95632.c
>>>>
>>>> diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
>>>> index df57e2b0b4a..b0daa4b19eb 100644
>>>> --- a/gcc/config/riscv/riscv.md
>>>> +++ b/gcc/config/riscv/riscv.md
>>>> @@ -1667,6 +1667,21 @@
>>>>                         MAX_MACHINE_MODE, &operands[3], TRUE);
>>>>    })
>>>>
>>>> +;; Pretend to have the ability to load complex const_int in order to get
>>>> +;; better code generation around them.
>>>> +(define_insn_and_split "*mvconst_internal"
>>>> +  [(set (match_operand:GPR 0 "register_operand" "=r")
>>>> +    (match_operand:GPR 1 "splittable_const_int_operand" "i"))]
>>>> +  "cse_not_expected"
>>>
>>> This is just way broken. This should be combined with the normal move
>>> instructions and just be a define_split.
>>> See PR 108892 for a testcase which shows this breaking how the
>>> register allocator thinks it should work.
>> I'm pretty sure that won't work.  You need them exposed as a define_insn
>> so that they can act as a bridge pattern for combine.  You don't want to
>> expose before combine as that'll regress things in a variety of other
>> ways.  You don't want the bridge form to survive after splitting.  Hence
>> define_insn_and_split.
>>
>> I haven't looked at that bug in detail, but Raphael and I certainly will.
> 
> So the register allocator does not know how to handle if there are two
> different patterns which are to be used but differ by
> constraints/predicats. This is especially true for mov instructions
> which this is.
The define_insn_and_split for this case shouldn't be available for the 
allocator.  If it is, then that's the source of the problem.  We may 
have missed something in the predicates.

> What I am saying is the "*movdi_64bit" and "*movsi_internal" patterns
> should handle the same instruction as the above and still have a
> define_split.
Perhaps but I think that's independent of the problem you're bumping up 
against.  Also note that by the time we're in the allocator we have to 
be more careful as we can't allocate new pseudos.


> 
> Take a look at how aarch64 handles this here. It has one pattern for
> the move but it is a define_insn_and_split still. This is explicitly
> to handle the case you are doing really.
> "*movsi_aarch64" and "*movdi_aarch64" .
Will do.
Jeff
diff mbox series

Patch

diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index df57e2b0b4a..b0daa4b19eb 100644
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -1667,6 +1667,21 @@ 
 		      MAX_MACHINE_MODE, &operands[3], TRUE);
 })
 
+;; Pretend to have the ability to load complex const_int in order to get
+;; better code generation around them.
+(define_insn_and_split "*mvconst_internal"
+  [(set (match_operand:GPR 0 "register_operand" "=r")
+    (match_operand:GPR 1 "splittable_const_int_operand" "i"))]
+  "cse_not_expected"
+  "#"
+  "&& 1"
+  [(const_int 0)]
+{
+  riscv_move_integer (operands[0], operands[0], INTVAL (operands[1]),
+		      <MODE>mode, TRUE);
+  DONE;
+})
+
 ;; 64-bit integer moves
 
 (define_expand "movdi"
diff --git a/gcc/testsuite/gcc.target/riscv/pr106602.c b/gcc/testsuite/gcc.target/riscv/pr106602.c
new file mode 100644
index 00000000000..825b1a143b5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/pr106602.c
@@ -0,0 +1,14 @@ 
+/* { dg-do compile { target { riscv64*-*-* } } } */
+/* { dg-options "-O2" } */
+
+unsigned long
+foo2 (unsigned long a)
+{
+  return (unsigned long)(unsigned int) a << 6;
+}
+
+/* { dg-final { scan-assembler-times "slli\t" 1 } } */
+/* { dg-final { scan-assembler-times "srli\t" 1 } } */
+/* { dg-final { scan-assembler-not "\tli\t" } } */
+/* { dg-final { scan-assembler-not "addi\t" } } */
+/* { dg-final { scan-assembler-not "and\t" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/pr95632.c b/gcc/testsuite/gcc.target/riscv/pr95632.c
new file mode 100644
index 00000000000..b865c2f2e97
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/pr95632.c
@@ -0,0 +1,15 @@ 
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+unsigned short
+foo (unsigned short crc)
+{
+  crc ^= 0x4002;
+  crc >>= 1;
+  crc |= 0x8000;
+
+  return crc;
+}
+
+/* { dg-final { scan-assembler-times "srli\t" 1 } } */
+/* { dg-final { scan-assembler-not "slli\t" } } */