From patchwork Fri Dec 2 04:26:05 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: liuhongt X-Patchwork-Id: 61341 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 17B883858408 for ; Fri, 2 Dec 2022 04:26:41 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 17B883858408 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1669955201; bh=h711lzUuksYripLol2NN/fNMU8tc+JNGttxkb0RGXLk=; h=To:Cc:Subject:Date:List-Id:List-Unsubscribe:List-Archive: List-Post:List-Help:List-Subscribe:From:Reply-To:From; b=t7DES2v7o7LCvAjcJ8HO6ny+Z7IZTnqruP0irF6+vuOtkDazWOW1bYJXns+hk7Jnq kFHCGWWwLrY/rHkhFHvPeVgdUNd9gaZTTbOL1/ViPHoCMXpmQofwAHGQuz6OUhFGd/ c9S+XhhyvUjLG39xT57/BvFEmoliFIPwo3MHY1ZY= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by sourceware.org (Postfix) with ESMTPS id BF99B3858C83 for ; Fri, 2 Dec 2022 04:26:09 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org BF99B3858C83 X-IronPort-AV: E=McAfee;i="6500,9779,10548"; a="296221394" X-IronPort-AV: E=Sophos;i="5.96,210,1665471600"; d="scan'208";a="296221394" Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Dec 2022 20:26:08 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10548"; a="973774764" X-IronPort-AV: E=Sophos;i="5.96,210,1665471600"; d="scan'208";a="973774764" Received: from shvmail03.sh.intel.com ([10.239.245.20]) by fmsmga005.fm.intel.com with ESMTP; 01 Dec 2022 20:26:06 -0800 Received: from shliclel4051.sh.intel.com (shliclel4051.sh.intel.com [10.239.240.51]) by shvmail03.sh.intel.com (Postfix) with ESMTP id 098FD1005678; Fri, 2 Dec 2022 12:26:06 +0800 (CST) To: gcc-patches@gcc.gnu.org Cc: crazylht@gmail.com, hjl.tools@gmail.com, ubizjak@gmail.com Subject: [PATCH] [x86] Improve ix86_expand_fast_convert_bf_to_sf with new extendbfsf2_1. Date: Fri, 2 Dec 2022 12:26:05 +0800 Message-Id: <20221202042606.551350-1-hongtao.liu@intel.com> X-Mailer: git-send-email 2.27.0 MIME-Version: 1.0 X-Spam-Status: No, score=-12.2 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: liuhongt via Gcc-patches From: liuhongt Reply-To: liuhongt Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" After supporting extendbfsf2_1, ix86_expand_fast_convert_bf_to_sf can be improved with pslld either. CONST_INT_P is not handled since constant shift can be optimized off. Bootstrapped and regtested on x86_64-pc-linux-gnu{-m32,}. Ok for trunk? gcc/ChangeLog: * config/i386/i386-expand.cc (ix86_expand_fast_convert_bf_to_sf): Optimized with extendbfsf2_1 for non-CONST_INT_P operand. gcc/testsuite/ChangeLog: * gcc.target/i386/cbranchbf4.c: New test. --- gcc/config/i386/i386-expand.cc | 13 ++++++------- gcc/testsuite/gcc.target/i386/cbranchbf4.c | 15 +++++++++++++++ 2 files changed, 21 insertions(+), 7 deletions(-) create mode 100644 gcc/testsuite/gcc.target/i386/cbranchbf4.c diff --git a/gcc/config/i386/i386-expand.cc b/gcc/config/i386/i386-expand.cc index d26e7e41445..0bc80c4b178 100644 --- a/gcc/config/i386/i386-expand.cc +++ b/gcc/config/i386/i386-expand.cc @@ -24155,14 +24155,13 @@ ix86_expand_fast_convert_bf_to_sf (rtx val) /* FLOAT_EXTEND simplification will fail if VAL is a sNaN. */ ret = gen_reg_rtx (SImode); emit_move_insn (ret, GEN_INT (INTVAL (op) & 0xffff)); + emit_insn (gen_ashlsi3 (ret, ret, GEN_INT (16))); + return gen_lowpart (SFmode, ret); } - else - { - ret = gen_reg_rtx (SImode); - emit_insn (gen_zero_extendhisi2 (ret, op)); - } - emit_insn (gen_ashlsi3 (ret, ret, GEN_INT (16))); - return gen_lowpart (SFmode, ret); + + ret = gen_reg_rtx (SFmode); + emit_insn (gen_extendbfsf2_1 (ret, force_reg (BFmode, val))); + return ret; } #include "gt-i386-expand.h" diff --git a/gcc/testsuite/gcc.target/i386/cbranchbf4.c b/gcc/testsuite/gcc.target/i386/cbranchbf4.c new file mode 100644 index 00000000000..8241a0c2165 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/cbranchbf4.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-fexcess-precision=16 -O -msse2 -mfpmath=sse" } */ +/* { dg-final { scan-assembler-times "pslld" 4 } } */ + +char +foo (__bf16 a, __bf16 b) +{ + return a > b; +} + +float +foo1 (__bf16 a, __bf16 b, float c, float d) +{ + return a > b ? c : d; +}