From patchwork Tue Nov 29 01:22:01 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "juzhe.zhong@rivai.ai" X-Patchwork-Id: 61204 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 776DF385189B for ; Tue, 29 Nov 2022 01:23:57 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from smtpbguseast3.qq.com (smtpbguseast3.qq.com [54.243.244.52]) by sourceware.org (Postfix) with ESMTPS id 6A86538432C5 for ; Tue, 29 Nov 2022 01:22:09 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 6A86538432C5 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivai.ai Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivai.ai X-QQ-mid: bizesmtp82t1669684924tls01ip2 Received: from server1.localdomain ( [58.60.1.22]) by bizesmtp.qq.com (ESMTP) with id ; Tue, 29 Nov 2022 09:22:03 +0800 (CST) X-QQ-SSF: 01400000000000D0K000000A0000000 X-QQ-FEAT: XBN7tc9DADKAUTwclrnRBiFh6ayzoffnAJrTHYmDFMS6B0ACkBp9fhdFGdczw 23NZZzGBhbMpJZEmlNLQgm0KcSyKQ99O00vJZ5JrwyDu8DhoFWSt/gPJg4kmHvkzG78Cbwk LkcAzUngDr9GZ7ZUtCg1OUq8Epcg3uzPwFZkOvg3gYJjRoeWk3oO5GmuYW31NkJpuL5ffU1 96VBtKB3YsKCJxtanx85BirQehw3489aA4I34u+71FLNiLBssKo0amL2yCGNb+jica4QJRd I8wlfCc0o2W9aw+jhAoNEVHU0nlUFMYZLaAnl33TqbYjHWpt9VVYFfRN0VgS38bB2oJFlfu JYaCjOBKmsGyp5bdsOkOVxYrq0LHAYElJjEdBhhnPATMOAaZ9CJ8QFo8uAE8g== X-QQ-GoodBg: 2 From: juzhe.zhong@rivai.ai To: gcc-patches@gcc.gnu.org Cc: kito.cheng@gmail.com, palmer@dabbelt.com, jeffreyalaw@gmail.com, Ju-Zhe Zhong Subject: [PATCH] RISC-V: Remove tail && mask policy operand for vmclr, vmset, vmld, vmst Date: Tue, 29 Nov 2022 09:22:01 +0800 Message-Id: <20221129012201.76355-1-juzhe.zhong@rivai.ai> X-Mailer: git-send-email 2.36.1 MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:rivai.ai:qybglogicsvr:qybglogicsvr7 X-Spam-Status: No, score=-10.8 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, RCVD_IN_BARRACUDACENTRAL, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_PASS, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" From: Ju-Zhe Zhong Sorry for resend this patch, I found I miss commit a file. 1. vector.md: remove tail && mask policy operand for mask mode operations since we don't need them according to RVV ISA. 2. riscv-v.cc: adapt emit_pred_op for mask mode predicated mov since all RVV modes including vector integer mode && vector float mode && vector bool mode are all use emit_pred_op function. For vector integer mode && vector float mode, we have instruction like vle.v/vse.v that we need tail && mask policy. However, for vector bool mode, the instruction is vlm/vsm that we don't need tail && mask policy. So we add a condition here to add tail && mask policy operand during expand if it is not a vector bool modes. This patch is to cleanup the code and make it be consistent with RVV ISA. gcc/ChangeLog: * config/riscv/riscv-v.cc (emit_pred_op): Adapt for mask mode. * config/riscv/vector.md: Remove Tail && make policy operand for mask mode mov. --- gcc/config/riscv/riscv-v.cc | 3 ++- gcc/config/riscv/vector.md | 2 -- 2 files changed, 2 insertions(+), 3 deletions(-) diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc index d54795694f1..4992ff2470c 100644 --- a/gcc/config/riscv/riscv-v.cc +++ b/gcc/config/riscv/riscv-v.cc @@ -136,7 +136,8 @@ emit_pred_op (unsigned icode, rtx dest, rtx src, machine_mode mask_mode) rtx vlmax = emit_vlmax_vsetvl (mode); e.add_input_operand (vlmax, Pmode); - e.add_policy_operand (TAIL_AGNOSTIC, MASK_AGNOSTIC); + if (GET_MODE_CLASS (mode) != MODE_VECTOR_BOOL) + e.add_policy_operand (TAIL_AGNOSTIC, MASK_AGNOSTIC); e.expand ((enum insn_code) icode, MEM_P (dest) || MEM_P (src)); } diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md index 3bb87232d3f..38da2f7f095 100644 --- a/gcc/config/riscv/vector.md +++ b/gcc/config/riscv/vector.md @@ -593,8 +593,6 @@ (unspec:VB [(match_operand:VB 1 "vector_mask_operand" "Wc1, Wc1, Wc1, Wc1, Wc1") (match_operand 4 "vector_length_operand" " rK, rK, rK, rK, rK") - (match_operand 5 "const_int_operand" " i, i, i, i, i") - (match_operand 6 "const_int_operand" " i, i, i, i, i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) (match_operand:VB 3 "vector_move_operand" " m, vr, vr, Wc0, Wc1")