Ver2: Riscv don't support "-fprefetch-loop-arrays" option, add "-w" option.

Message ID 20221122094842.2629693-1-chenyixuan@iscas.ac.cn
State New
Headers
Series Ver2: Riscv don't support "-fprefetch-loop-arrays" option, add "-w" option. |

Commit Message

Yixuan Chen Nov. 22, 2022, 9:48 a.m. UTC
  gcc/testsuite/ChangeLog:

Riscv don't support "-fprefetch-loop-arrays" option, add "-w" option.

2022-11-22  Yixuan Chen  <chenyixuan@iscas.ac.cn>

        * gcc.dg/pr106397.c: Riscv don't support "-fprefetch-loop-arrays" option, add "-w" option.
---
 gcc/testsuite/gcc.dg/pr106397.c | 1 +
 1 file changed, 1 insertion(+)
  

Comments

Richard Biener Nov. 22, 2022, 10:03 a.m. UTC | #1
> Am 22.11.2022 um 10:49 schrieb Yixuan Chen <chenyixuan@iscas.ac.cn>:
> 
> gcc/testsuite/ChangeLog:
> 
> Riscv don't support "-fprefetch-loop-arrays" option, add "-w" option.

Ok.

Richard 

> 2022-11-22  Yixuan Chen  <chenyixuan@iscas.ac.cn>
> 
>        * gcc.dg/pr106397.c: Riscv don't support "-fprefetch-loop-arrays" option, add "-w" option.
> ---
> gcc/testsuite/gcc.dg/pr106397.c | 1 +
> 1 file changed, 1 insertion(+)
> 
> diff --git a/gcc/testsuite/gcc.dg/pr106397.c b/gcc/testsuite/gcc.dg/pr106397.c
> index 2bc17f8cf80..b0983b61dfc 100644
> --- a/gcc/testsuite/gcc.dg/pr106397.c
> +++ b/gcc/testsuite/gcc.dg/pr106397.c
> @@ -1,6 +1,7 @@
> /* { dg-do compile } */
> /* { dg-options "-O3 -fprefetch-loop-arrays --param l2-cache-size=0 --param prefetch-latency=3 -fprefetch-loop-arrays" } */
> /* { dg-additional-options "-march=i686 -msse" { target { { i?86-*-* x86_64-*-* } && ia32 } } } */
> +/* { dg-additional-options "-w" { target riscv*-*-* } } */
> 
> int
> bar (void)
> -- 
> 2.37.2
>
  

Patch

diff --git a/gcc/testsuite/gcc.dg/pr106397.c b/gcc/testsuite/gcc.dg/pr106397.c
index 2bc17f8cf80..b0983b61dfc 100644
--- a/gcc/testsuite/gcc.dg/pr106397.c
+++ b/gcc/testsuite/gcc.dg/pr106397.c
@@ -1,6 +1,7 @@ 
 /* { dg-do compile } */
 /* { dg-options "-O3 -fprefetch-loop-arrays --param l2-cache-size=0 --param prefetch-latency=3 -fprefetch-loop-arrays" } */
 /* { dg-additional-options "-march=i686 -msse" { target { { i?86-*-* x86_64-*-* } && ia32 } } } */
+/* { dg-additional-options "-w" { target riscv*-*-* } } */
 
 int
 bar (void)