Riscv don't support "-fprefetch-loop-arrays", skip.
Commit Message
gcc/testsuite/ChangeLog:
Riscv don't support "-fprefetch-loop-arrays" option, skip.
2022-11-22 Yixuan Chen <chenyixuan@iscas.ac.cn>
* gcc.dg/pr106397.c: Riscv don't support "-fprefetch-loop-arrays" option, skip.
---
gcc/testsuite/gcc.dg/pr106397.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
Comments
On Tue, Nov 22, 2022 at 9:43 AM Yixuan Chen <chenyixuan@iscas.ac.cn> wrote:
>
> gcc/testsuite/ChangeLog:
>
> Riscv don't support "-fprefetch-loop-arrays" option, skip.
Looking around other testcases simply add -w to the set of command-line options,
can you do that instead?
OK with that change,
Richard.
> 2022-11-22 Yixuan Chen <chenyixuan@iscas.ac.cn>
>
> * gcc.dg/pr106397.c: Riscv don't support "-fprefetch-loop-arrays" option, skip.
> ---
> gcc/testsuite/gcc.dg/pr106397.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/gcc/testsuite/gcc.dg/pr106397.c b/gcc/testsuite/gcc.dg/pr106397.c
> index 2bc17f8cf80..7b507125575 100644
> --- a/gcc/testsuite/gcc.dg/pr106397.c
> +++ b/gcc/testsuite/gcc.dg/pr106397.c
> @@ -1,7 +1,7 @@
> /* { dg-do compile } */
> /* { dg-options "-O3 -fprefetch-loop-arrays --param l2-cache-size=0 --param prefetch-latency=3 -fprefetch-loop-arrays" } */
> /* { dg-additional-options "-march=i686 -msse" { target { { i?86-*-* x86_64-*-* } && ia32 } } } */
> -
> +/* { dg-skip-if "" { riscv*-*-* } } */
> int
> bar (void)
> {
> --
> 2.37.2
>
@@ -1,7 +1,7 @@
/* { dg-do compile } */
/* { dg-options "-O3 -fprefetch-loop-arrays --param l2-cache-size=0 --param prefetch-latency=3 -fprefetch-loop-arrays" } */
/* { dg-additional-options "-march=i686 -msse" { target { { i?86-*-* x86_64-*-* } && ia32 } } } */
-
+/* { dg-skip-if "" { riscv*-*-* } } */
int
bar (void)
{