Ver.2: Add compile option "-msmall-data-limit=0" to avoid using .srodata section for riscv.
| Message ID | 20221117095355.1928564-1-chenyixuan@iscas.ac.cn |
|---|---|
| State | New |
| Headers |
Return-Path: <gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org> X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id F2914396DC34 for <patchwork@sourceware.org>; Thu, 17 Nov 2022 09:54:21 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from cstnet.cn (smtp21.cstnet.cn [159.226.251.21]) by sourceware.org (Postfix) with ESMTP id BED293959C7D for <gcc-patches@gcc.gnu.org>; Thu, 17 Nov 2022 09:54:02 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org BED293959C7D Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=iscas.ac.cn Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=iscas.ac.cn Received: from ubuntu.. (unknown [27.16.214.61]) by APP-01 (Coremail) with SMTP id qwCowAC3Vmi1BHZjAnInCg--.25791S2; Thu, 17 Nov 2022 17:53:58 +0800 (CST) From: Yixuan Chen <chenyixuan@iscas.ac.cn> To: gcc-patches@gcc.gnu.org Cc: kito.cheng@gmail.com, andrew@sifive.com, oriachiuan@gmail.com, Yixuan Chen <chenyixuan@iscas.ac.cn> Subject: [PATCH] Ver.2: Add compile option "-msmall-data-limit=0" to avoid using .srodata section for riscv. Date: Thu, 17 Nov 2022 17:53:55 +0800 Message-Id: <20221117095355.1928564-1-chenyixuan@iscas.ac.cn> X-Mailer: git-send-email 2.37.2 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-CM-TRANSID: qwCowAC3Vmi1BHZjAnInCg--.25791S2 X-Coremail-Antispam: 1UD129KBjvdXoW7JryfZFy5XF13ury7Kw17Wrg_yoWxuwcEqa yYgFs3Xr45AaykAF45Xw1IyrW0kan5ur9av3WkKFnIqryDJFs5ta1qgFnxZFy7Cr45JFy3 Kw4fZrySvrnrKjkaLaAFLSUrUUUUUb8apTn2vfkv8UJUUUU8Yxn0WfASr-VFAUDa7-sFnT 9fnUUIcSsGvfJTRUUUbwxFF20E14v26r1j6r4UM7CY07I20VC2zVCF04k26cxKx2IYs7xG 6rWj6s0DM7CIcVAFz4kK6r1j6r18M28lY4IEw2IIxxk0rwA2F7IY1VAKz4vEj48ve4kI8w A2z4x0Y4vE2Ix0cI8IcVAFwI0_Gr0_Xr1l84ACjcxK6xIIjxv20xvEc7CjxVAFwI0_Gr0_ Cr1l84ACjcxK6I8E87Iv67AKxVWxJr0_GcWl84ACjcxK6I8E87Iv6xkF7I0E14v26rxl6s 0DM2AIxVAIcxkEcVAq07x20xvEncxIr21l5I8CrVACY4xI64kE6c02F40Ex7xfMcIj6xII jxv20xvE14v26r1j6r18McIj6I8E87Iv67AKxVWUJVW8JwAm72CE4IkC6x0Yz7v_Jr0_Gr 1lF7xvr2IYc2Ij64vIr41lF7I21c0EjII2zVCS5cI20VAGYxC7MxAIw28IcxkI7VAKI48J MxC20s026xCaFVCjc4AY6r1j6r4UMI8I3I0E5I8CrVAFwI0_Jr0_Jr4lx2IqxVCjr7xvwV AFwI0_JrI_JrWlx4CE17CEb7AF67AKxVWUAVWUtwCIc40Y0x0EwIxGrwCI42IY6xIIjxv2 0xvE14v26r1j6r1xMIIF0xvE2Ix0cI8IcVCY1x0267AKxVWUJVW8JwCI42IY6xAIw20EY4 v20xvaj40_Jr0_JF4lIxAIcVC2z280aVAFwI0_Jr0_Gr1lIxAIcVC2z280aVCY1x0267AK xVWUJVW8JbIYCTnIWIevJa73UjIFyTuYvjfU5WlkUUUUU X-Originating-IP: [27.16.214.61] X-CM-SenderInfo: xfkh05pl0xt046lvutnvoduhdfq/ X-Spam-Status: No, score=-13.7 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, SPF_HELO_PASS, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list <gcc-patches.gcc.gnu.org> List-Unsubscribe: <https://gcc.gnu.org/mailman/options/gcc-patches>, <mailto:gcc-patches-request@gcc.gnu.org?subject=unsubscribe> List-Archive: <https://gcc.gnu.org/pipermail/gcc-patches/> List-Post: <mailto:gcc-patches@gcc.gnu.org> List-Help: <mailto:gcc-patches-request@gcc.gnu.org?subject=help> List-Subscribe: <https://gcc.gnu.org/mailman/listinfo/gcc-patches>, <mailto:gcc-patches-request@gcc.gnu.org?subject=subscribe> Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" <gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org> |
| Series |
Ver.2: Add compile option "-msmall-data-limit=0" to avoid using .srodata section for riscv.
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Commit Message
Yixuan Chen
Nov. 17, 2022, 9:53 a.m. UTC
2022-11-17 Yixuan Chen <chenyixuan@iscas.ac.cn>
* gcc/testsuite/gcc.dg/pr25521.c: Add compile option "-msmall-data-limit=0" to avoid using .srodata section for riscv.
---
gcc/testsuite/gcc.dg/pr25521.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
Comments
On 11/17/22 02:53, Yixuan Chen wrote: > 2022-11-17 Yixuan Chen <chenyixuan@iscas.ac.cn> > > * gcc/testsuite/gcc.dg/pr25521.c: Add compile option "-msmall-data-limit=0" to avoid using .srodata section for riscv. > --- > gcc/testsuite/gcc.dg/pr25521.c | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) > > diff --git a/gcc/testsuite/gcc.dg/pr25521.c b/gcc/testsuite/gcc.dg/pr25521.c > index 74fe2ae6626..628ddf1a761 100644 > --- a/gcc/testsuite/gcc.dg/pr25521.c > +++ b/gcc/testsuite/gcc.dg/pr25521.c > @@ -2,7 +2,8 @@ > sections. > > { dg-require-effective-target elf } > - { dg-do compile } */ > + { dg-do compile } > + { dg-options "-msmall-data-limit=0" { target { riscv*-*-* } } } */ > > const volatile int foo = 30; > Wouldn't this be better? It avoids a target specific conditional by instead extending what we look for to cover [s]rodata sections. Thoughts? Jeff diff --git a/gcc/testsuite/gcc.dg/pr25521.c b/gcc/testsuite/gcc.dg/pr25521.c index 74fe2ae6626..63363a03b9f 100644 --- a/gcc/testsuite/gcc.dg/pr25521.c +++ b/gcc/testsuite/gcc.dg/pr25521.c @@ -7,4 +7,4 @@ const volatile int foo = 30; -/* { dg-final { scan-assembler "\\.rodata" } } */ +/* { dg-final { scan-assembler "\\.s\?rodata" } } */
On Thu, 17 Nov 2022 13:50:00 PST (-0800), gcc-patches@gcc.gnu.org wrote: > > On 11/17/22 02:53, Yixuan Chen wrote: >> 2022-11-17 Yixuan Chen <chenyixuan@iscas.ac.cn> >> >> * gcc/testsuite/gcc.dg/pr25521.c: Add compile option "-msmall-data-limit=0" to avoid using .srodata section for riscv. >> --- >> gcc/testsuite/gcc.dg/pr25521.c | 3 ++- >> 1 file changed, 2 insertions(+), 1 deletion(-) >> >> diff --git a/gcc/testsuite/gcc.dg/pr25521.c b/gcc/testsuite/gcc.dg/pr25521.c >> index 74fe2ae6626..628ddf1a761 100644 >> --- a/gcc/testsuite/gcc.dg/pr25521.c >> +++ b/gcc/testsuite/gcc.dg/pr25521.c >> @@ -2,7 +2,8 @@ >> sections. >> >> { dg-require-effective-target elf } >> - { dg-do compile } */ >> + { dg-do compile } >> + { dg-options "-msmall-data-limit=0" { target { riscv*-*-* } } } */ >> >> const volatile int foo = 30; >> > > Wouldn't this be better? It avoids a target specific conditional by > instead extending what we look for to cover [s]rodata sections. > > > Thoughts? > > Jeff > diff --git a/gcc/testsuite/gcc.dg/pr25521.c b/gcc/testsuite/gcc.dg/pr25521.c > index 74fe2ae6626..63363a03b9f 100644 > --- a/gcc/testsuite/gcc.dg/pr25521.c > +++ b/gcc/testsuite/gcc.dg/pr25521.c > @@ -7,4 +7,4 @@ > const volatile int foo = 30; > > > -/* { dg-final { scan-assembler "\\.rodata" } } */ > +/* { dg-final { scan-assembler "\\.s\?rodata" } } */ That's how I usually do it for these tests, there's some other targets with sdata too so it fixes the test for everyone. IIRC I said something like that in the v1, but sorry if I'm just getting it confused with some other patch. There's a few of these that need to get chased down for every release, maybe we should add some sort of DG hepler? Not sure that'd keep folks from matching on .data, though...
Got it, I used to regard this test case as targeting at test if the const data would use the ".rodata" section. Palmer Dabbelt <palmer@dabbelt.com> 于2022年11月18日周五 07:59写道： > On Thu, 17 Nov 2022 13:50:00 PST (-0800), gcc-patches@gcc.gnu.org wrote: > > > > On 11/17/22 02:53, Yixuan Chen wrote: > >> 2022-11-17 Yixuan Chen <chenyixuan@iscas.ac.cn> > >> > >> * gcc/testsuite/gcc.dg/pr25521.c: Add compile option > "-msmall-data-limit=0" to avoid using .srodata section for riscv. > >> --- > >> gcc/testsuite/gcc.dg/pr25521.c | 3 ++- > >> 1 file changed, 2 insertions(+), 1 deletion(-) > >> > >> diff --git a/gcc/testsuite/gcc.dg/pr25521.c > b/gcc/testsuite/gcc.dg/pr25521.c > >> index 74fe2ae6626..628ddf1a761 100644 > >> --- a/gcc/testsuite/gcc.dg/pr25521.c > >> +++ b/gcc/testsuite/gcc.dg/pr25521.c > >> @@ -2,7 +2,8 @@ > >> sections. > >> > >> { dg-require-effective-target elf } > >> - { dg-do compile } */ > >> + { dg-do compile } > >> + { dg-options "-msmall-data-limit=0" { target { riscv*-*-* } } } */ > >> > >> const volatile int foo = 30; > >> > > > > Wouldn't this be better? It avoids a target specific conditional by > > instead extending what we look for to cover [s]rodata sections. > > > > > > Thoughts? > > > > Jeff > > diff --git a/gcc/testsuite/gcc.dg/pr25521.c > b/gcc/testsuite/gcc.dg/pr25521.c > > index 74fe2ae6626..63363a03b9f 100644 > > --- a/gcc/testsuite/gcc.dg/pr25521.c > > +++ b/gcc/testsuite/gcc.dg/pr25521.c > > @@ -7,4 +7,4 @@ > > const volatile int foo = 30; > > > > > > -/* { dg-final { scan-assembler "\\.rodata" } } */ > > +/* { dg-final { scan-assembler "\\.s\?rodata" } } */ > > That's how I usually do it for these tests, there's some other targets > with sdata too so it fixes the test for everyone. IIRC I said something > like that in the v1, but sorry if I'm just getting it confused with some > other patch. > > There's a few of these that need to get chased down for every release, > maybe we should add some sort of DG hepler? Not sure that'd keep folks > from matching on .data, though... >
On Thu, 17 Nov 2022 19:30:23 PST (-0800), oriachiuan@gmail.com wrote: > Got it, I used to regard this test case as targeting at test if the const > data would use the ".rodata" section. Sorry, I'm not quite sure what you're trying to say here. Here's a dump of how I see things: In some targets (RISC-V and MIPS) there's multiple copies of the data/rodata sections, with the small data/rodata ending up in the small sections (`.sdata` and `.srodata`). I've never actually been 100% on that being allowed by any spec, but MIPS did it long before RISC-V so I figure software is expected to tolerate the oddness. In RISC-V we use it to try and place as many symbols as possible close to GP, so we're more likely to relax to GP-relative addressing sequences. IIRC that's pretty much the same as MIPS, though they have slightly different addressing requirements. For targets that function this way `.srodata` and `.rodata` are functionally equivalent (assuming you're not playing any GP tricks to relocate, but those are way out of what's supported). So unless the test is trying to dig into performance issues differences between these sections, it should just allow code to target either. > > Palmer Dabbelt <palmer@dabbelt.com> 于2022年11月18日周五 07:59写道： > >> On Thu, 17 Nov 2022 13:50:00 PST (-0800), gcc-patches@gcc.gnu.org wrote: >> > >> > On 11/17/22 02:53, Yixuan Chen wrote: >> >> 2022-11-17 Yixuan Chen <chenyixuan@iscas.ac.cn> >> >> >> >> * gcc/testsuite/gcc.dg/pr25521.c: Add compile option >> "-msmall-data-limit=0" to avoid using .srodata section for riscv. >> >> --- >> >> gcc/testsuite/gcc.dg/pr25521.c | 3 ++- >> >> 1 file changed, 2 insertions(+), 1 deletion(-) >> >> >> >> diff --git a/gcc/testsuite/gcc.dg/pr25521.c >> b/gcc/testsuite/gcc.dg/pr25521.c >> >> index 74fe2ae6626..628ddf1a761 100644 >> >> --- a/gcc/testsuite/gcc.dg/pr25521.c >> >> +++ b/gcc/testsuite/gcc.dg/pr25521.c >> >> @@ -2,7 +2,8 @@ >> >> sections. >> >> >> >> { dg-require-effective-target elf } >> >> - { dg-do compile } */ >> >> + { dg-do compile } >> >> + { dg-options "-msmall-data-limit=0" { target { riscv*-*-* } } } */ >> >> >> >> const volatile int foo = 30; >> >> >> > >> > Wouldn't this be better? It avoids a target specific conditional by >> > instead extending what we look for to cover [s]rodata sections. >> > >> > >> > Thoughts? >> > >> > Jeff >> > diff --git a/gcc/testsuite/gcc.dg/pr25521.c >> b/gcc/testsuite/gcc.dg/pr25521.c >> > index 74fe2ae6626..63363a03b9f 100644 >> > --- a/gcc/testsuite/gcc.dg/pr25521.c >> > +++ b/gcc/testsuite/gcc.dg/pr25521.c >> > @@ -7,4 +7,4 @@ >> > const volatile int foo = 30; >> > >> > >> > -/* { dg-final { scan-assembler "\\.rodata" } } */ >> > +/* { dg-final { scan-assembler "\\.s\?rodata" } } */ >> >> That's how I usually do it for these tests, there's some other targets >> with sdata too so it fixes the test for everyone. IIRC I said something >> like that in the v1, but sorry if I'm just getting it confused with some >> other patch. >> >> There's a few of these that need to get chased down for every release, >> maybe we should add some sort of DG hepler? Not sure that'd keep folks >> from matching on .data, though... >>
Thank you very much for your patient explanation！ Palmer Dabbelt <palmer@dabbelt.com>于2022年11月18日 周五13:02写道： > On Thu, 17 Nov 2022 19:30:23 PST (-0800), oriachiuan@gmail.com wrote: > > Got it, I used to regard this test case as targeting at test if the const > > data would use the ".rodata" section. > > Sorry, I'm not quite sure what you're trying to say here. Here's a dump > of how I see things: > > In some targets (RISC-V and MIPS) there's multiple copies of the > data/rodata sections, with the small data/rodata ending up in the small > sections (`.sdata` and `.srodata`). I've never actually been 100% on > that being allowed by any spec, but MIPS did it long before RISC-V so I > figure software is expected to tolerate the oddness. > > In RISC-V we use it to try and place as many symbols as possible close > to GP, so we're more likely to relax to GP-relative addressing > sequences. IIRC that's pretty much the same as MIPS, though they have > slightly different addressing requirements. > > For targets that function this way `.srodata` and `.rodata` are > functionally equivalent (assuming you're not playing any GP tricks to > relocate, but those are way out of what's supported). So unless the > test is trying to dig into performance issues differences between these > sections, it should just allow code to target either. > > > > > Palmer Dabbelt <palmer@dabbelt.com> 于2022年11月18日周五 07:59写道： > > > >> On Thu, 17 Nov 2022 13:50:00 PST (-0800), gcc-patches@gcc.gnu.org > wrote: > >> > > >> > On 11/17/22 02:53, Yixuan Chen wrote: > >> >> 2022-11-17 Yixuan Chen <chenyixuan@iscas.ac.cn> > >> >> > >> >> * gcc/testsuite/gcc.dg/pr25521.c: Add compile option > >> "-msmall-data-limit=0" to avoid using .srodata section for riscv. > >> >> --- > >> >> gcc/testsuite/gcc.dg/pr25521.c | 3 ++- > >> >> 1 file changed, 2 insertions(+), 1 deletion(-) > >> >> > >> >> diff --git a/gcc/testsuite/gcc.dg/pr25521.c > >> b/gcc/testsuite/gcc.dg/pr25521.c > >> >> index 74fe2ae6626..628ddf1a761 100644 > >> >> --- a/gcc/testsuite/gcc.dg/pr25521.c > >> >> +++ b/gcc/testsuite/gcc.dg/pr25521.c > >> >> @@ -2,7 +2,8 @@ > >> >> sections. > >> >> > >> >> { dg-require-effective-target elf } > >> >> - { dg-do compile } */ > >> >> + { dg-do compile } > >> >> + { dg-options "-msmall-data-limit=0" { target { riscv*-*-* } } } > */ > >> >> > >> >> const volatile int foo = 30; > >> >> > >> > > >> > Wouldn't this be better? It avoids a target specific conditional by > >> > instead extending what we look for to cover [s]rodata sections. > >> > > >> > > >> > Thoughts? > >> > > >> > Jeff > >> > diff --git a/gcc/testsuite/gcc.dg/pr25521.c > >> b/gcc/testsuite/gcc.dg/pr25521.c > >> > index 74fe2ae6626..63363a03b9f 100644 > >> > --- a/gcc/testsuite/gcc.dg/pr25521.c > >> > +++ b/gcc/testsuite/gcc.dg/pr25521.c > >> > @@ -7,4 +7,4 @@ > >> > const volatile int foo = 30; > >> > > >> > > >> > -/* { dg-final { scan-assembler "\\.rodata" } } */ > >> > +/* { dg-final { scan-assembler "\\.s\?rodata" } } */ > >> > >> That's how I usually do it for these tests, there's some other targets > >> with sdata too so it fixes the test for everyone. IIRC I said something > >> like that in the v1, but sorry if I'm just getting it confused with some > >> other patch. > >> > >> There's a few of these that need to get chased down for every release, > >> maybe we should add some sort of DG hepler? Not sure that'd keep folks > >> from matching on .data, though... > >> >
Thank you very much for your example! I have sent a new patch according to your guide. "Jeff Law" <jeffreyalaw@gmail.com>wrote: > > On 11/17/22 02:53, Yixuan Chen wrote: > > 2022-11-17 Yixuan Chen <chenyixuan@iscas.ac.cn> > > > > * gcc/testsuite/gcc.dg/pr25521.c: Add compile option "-msmall-data-limit=0" to avoid using .srodata section for riscv. > > --- > > gcc/testsuite/gcc.dg/pr25521.c | 3 ++- > > 1 file changed, 2 insertions(+), 1 deletion(-) > > > > diff --git a/gcc/testsuite/gcc.dg/pr25521.c b/gcc/testsuite/gcc.dg/pr25521.c > > index 74fe2ae6626..628ddf1a761 100644 > > --- a/gcc/testsuite/gcc.dg/pr25521.c > > +++ b/gcc/testsuite/gcc.dg/pr25521.c > > @@ -2,7 +2,8 @@ > > sections. > > > > { dg-require-effective-target elf } > > - { dg-do compile } */ > > + { dg-do compile } > > + { dg-options "-msmall-data-limit=0" { target { riscv*-*-* } } } */ > > > > const volatile int foo = 30; > > > > Wouldn't this be better? It avoids a target specific conditional by > instead extending what we look for to cover [s]rodata sections. > > > Thoughts? > > Jeff
diff --git a/gcc/testsuite/gcc.dg/pr25521.c b/gcc/testsuite/gcc.dg/pr25521.c index 74fe2ae6626..628ddf1a761 100644 --- a/gcc/testsuite/gcc.dg/pr25521.c +++ b/gcc/testsuite/gcc.dg/pr25521.c @@ -2,7 +2,8 @@ sections. { dg-require-effective-target elf } - { dg-do compile } */ + { dg-do compile } + { dg-options "-msmall-data-limit=0" { target { riscv*-*-* } } } */ const volatile int foo = 30;