| Message ID | 20221116021027.519897-1-chenglulu@loongson.cn |
|---|---|
| State | Committed |
| Commit | 3138db588a46d445876c0358df55fa3995c6f221 |
| Headers |
Return-Path: <gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org> X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 444F93959C6A for <patchwork@sourceware.org>; Wed, 16 Nov 2022 02:12:48 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from loongson.cn (mail.loongson.cn [114.242.206.163]) by sourceware.org (Postfix) with ESMTP id F140E395383C for <gcc-patches@gcc.gnu.org>; Wed, 16 Nov 2022 02:12:29 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org F140E395383C Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=loongson.cn Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=loongson.cn Received: from loongson.cn (unknown [10.2.5.5]) by gateway (Coremail) with SMTP id _____8DxPLcKR3RjXI0HAA--.10597S3; Wed, 16 Nov 2022 10:12:27 +0800 (CST) Received: from 5.5.5 (unknown [10.2.5.5]) by localhost.localdomain (Coremail) with SMTP id AQAAf8BxmFcFR3RjMUUUAA--.35898S2; Wed, 16 Nov 2022 10:12:25 +0800 (CST) From: Lulu Cheng <chenglulu@loongson.cn> To: gcc-patches@gcc.gnu.org Cc: xry111@xry111.site, i@xen0n.name, xuchenghua@loongson.cn, Lulu Cheng <chenglulu@loongson.cn>, xujiahao <xujiahao@loongson.cn> Subject: [PATCH v3] LoongArch: Add prefetch instructions. Date: Wed, 16 Nov 2022 10:10:28 +0800 Message-Id: <20221116021027.519897-1-chenglulu@loongson.cn> X-Mailer: git-send-email 2.31.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-CM-TRANSID: AQAAf8BxmFcFR3RjMUUUAA--.35898S2 X-CM-SenderInfo: xfkh0wpoxo3qxorr0wxvrqhubq/ X-Coremail-Antispam: 1Uk129KBjvJXoW3XF1rtr4UAr1DCF1rJF1UJrb_yoW7CF43pr 93uw43Jr48Jrnag3yDt34rWws8JryxKw12vay3KFyxCa17ZryUZFn5trZxXFWUX395trya qF1rKa1UZa1jyaUanT9S1TB71UUUUUDqnTZGkaVYY2UrUUUUj1kv1TuYvTs0mT0YCTnIWj qI5I8CrVACY4xI64kE6c02F40Ex7xfYxn0WfASr-VFAUDa7-sFnT9fnUUIcSsGvfJTRUUU b7xYFVCjjxCrM7AC8VAFwI0_Jr0_Gr1l1xkIjI8I6I8E6xAIw20EY4v20xvaj40_Wr0E3s 1l1IIY67AEw4v_JrI_Jryl8cAvFVAK0II2c7xJM28CjxkF64kEwVA0rcxSw2x7M28EF7xv wVC0I7IYx2IY67AKxVWUCVW8JwA2z4x0Y4vE2Ix0cI8IcVCY1x0267AKxVWUJVW8JwA2z4 x0Y4vEx4A2jsIE14v26F4j6r4UJwA2z4x0Y4vEx4A2jsIEc7CjxVAFwI0_Gr0_Gr1UM2AI xVAIcxkEcVAq07x20xvEncxIr21l57IF6xkI12xvs2x26I8E6xACxx1l5I8CrVACY4xI64 kE6c02F40Ex7xfMcIj6xIIjxv20xvE14v26r1Y6r17McIj6I8E87Iv67AKxVWUJVW8JwAm 72CE4IkC6x0Yz7v_Jr0_Gr1lF7xvr2IYc2Ij64vIr41l42xK82IYc2Ij64vIr41l4I8I3I 0E4IkC6x0Yz7v_Jr0_Gr1lx2IqxVAqx4xG67AKxVWUJVWUGwC20s026x8GjcxK67AKxVWU GVWUWwC2zVAF1VAY17CE14v26r126r1DMIIYrxkI7VAKI48JMIIF0xvE2Ix0cI8IcVAFwI 0_Jr0_JF4lIxAIcVC0I7IYx2IY6xkF7I0E14v26r1j6r4UMIIF0xvE42xK8VAvwI8IcIk0 rVWUJVWUCwCI42IY6I8E87Iv67AKxVWUJVW8JwCI42IY6I8E87Iv6xkF7I0E14v26r1j6r 4UYxBIdaVFxhVjvjDU0xZFpf9x07j1YL9UUUUU= X-Spam-Status: No, score=-12.5 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, SPF_HELO_PASS, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list <gcc-patches.gcc.gnu.org> List-Unsubscribe: <https://gcc.gnu.org/mailman/options/gcc-patches>, <mailto:gcc-patches-request@gcc.gnu.org?subject=unsubscribe> List-Archive: <https://gcc.gnu.org/pipermail/gcc-patches/> List-Post: <mailto:gcc-patches@gcc.gnu.org> List-Help: <mailto:gcc-patches-request@gcc.gnu.org?subject=help> List-Subscribe: <https://gcc.gnu.org/mailman/listinfo/gcc-patches>, <mailto:gcc-patches-request@gcc.gnu.org?subject=subscribe> Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" <gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org> |
| Series |
[v3] LoongArch: Add prefetch instructions.
|
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Commit Message
Lulu Cheng
Nov. 16, 2022, 2:10 a.m. UTC
v2 -> v3: 1. Remove preldx support. --------------------------------------- Enable sw prefetching at -O3 and higher. Co-Authored-By: xujiahao <xujiahao@loongson.cn> gcc/ChangeLog: * config/loongarch/constraints.md (ZD): New constraint. * config/loongarch/loongarch-def.c: Initial number of parallel prefetch. * config/loongarch/loongarch-tune.h (struct loongarch_cache): Define number of parallel prefetch. * config/loongarch/loongarch.cc (loongarch_option_override_internal): Set up parameters to be used in prefetching algorithm. * config/loongarch/loongarch.md (prefetch): New template. --- gcc/config/loongarch/constraints.md | 10 ++++++++++ gcc/config/loongarch/loongarch-def.c | 2 ++ gcc/config/loongarch/loongarch-tune.h | 1 + gcc/config/loongarch/loongarch.cc | 28 +++++++++++++++++++++++++++ gcc/config/loongarch/loongarch.md | 14 ++++++++++++++ 5 files changed, 55 insertions(+)
Comments
On 2022/11/16 10:10, Lulu Cheng wrote: > v2 -> v3: > 1. Remove preldx support. > > --------------------------------------- > Enable sw prefetching at -O3 and higher. > > Co-Authored-By: xujiahao <xujiahao@loongson.cn> > > gcc/ChangeLog: > > * config/loongarch/constraints.md (ZD): New constraint. > * config/loongarch/loongarch-def.c: Initial number of parallel prefetch. > * config/loongarch/loongarch-tune.h (struct loongarch_cache): > Define number of parallel prefetch. > * config/loongarch/loongarch.cc (loongarch_option_override_internal): > Set up parameters to be used in prefetching algorithm. > * config/loongarch/loongarch.md (prefetch): New template. > --- > gcc/config/loongarch/constraints.md | 10 ++++++++++ > gcc/config/loongarch/loongarch-def.c | 2 ++ > gcc/config/loongarch/loongarch-tune.h | 1 + > gcc/config/loongarch/loongarch.cc | 28 +++++++++++++++++++++++++++ > gcc/config/loongarch/loongarch.md | 14 ++++++++++++++ > 5 files changed, 55 insertions(+) > > diff --git a/gcc/config/loongarch/constraints.md b/gcc/config/loongarch/constraints.md > index 43cb7b5f0f5..46f7f63ae31 100644 > --- a/gcc/config/loongarch/constraints.md > +++ b/gcc/config/loongarch/constraints.md > @@ -86,6 +86,10 @@ > ;; "ZB" > ;; "An address that is held in a general-purpose register. > ;; The offset is zero" > +;; "ZD" > +;; "An address operand whose address is formed by a base register > +;; and offset that is suitable for use in instructions with the same > +;; addressing mode as @code{preld}." > ;; "<" "Matches a pre-dec or post-dec operand." (Global non-architectural) > ;; ">" "Matches a pre-inc or post-inc operand." (Global non-architectural) > > @@ -190,3 +194,9 @@ (define_memory_constraint "ZB" > The offset is zero" > (and (match_code "mem") > (match_test "REG_P (XEXP (op, 0))"))) > + > +(define_address_constraint "ZD" > + "An address operand whose address is formed by a base register > + and offset that is suitable for use in instructions with the same > + addressing mode as @code{preld}." > + (match_test "loongarch_12bit_offset_address_p (op, mode)")) How is this different with the "m" constraint? AFAIK preld and ld share the same addressing mode (i.e. base register + 12-bit signed immediate offset). > diff --git a/gcc/config/loongarch/loongarch-def.c b/gcc/config/loongarch/loongarch-def.c > index cbf995d81b5..80ab10a52a8 100644 > --- a/gcc/config/loongarch/loongarch-def.c > +++ b/gcc/config/loongarch/loongarch-def.c > @@ -62,11 +62,13 @@ loongarch_cpu_cache[N_TUNE_TYPES] = { > .l1d_line_size = 64, > .l1d_size = 64, > .l2d_size = 256, > + .simultaneous_prefetches = 4, > }, > [CPU_LA464] = { > .l1d_line_size = 64, > .l1d_size = 64, > .l2d_size = 256, > + .simultaneous_prefetches = 4, > }, > }; > > diff --git a/gcc/config/loongarch/loongarch-tune.h b/gcc/config/loongarch/loongarch-tune.h > index 6f3530f5c02..8e3eb29472b 100644 > --- a/gcc/config/loongarch/loongarch-tune.h > +++ b/gcc/config/loongarch/loongarch-tune.h > @@ -45,6 +45,7 @@ struct loongarch_cache { > int l1d_line_size; /* bytes */ > int l1d_size; /* KiB */ > int l2d_size; /* kiB */ > + int simultaneous_prefetches; /* number of parallel prefetch */ nit: "prefetches" or "prefetch ops" or "int prefetch_width"? > }; > > #endif /* LOONGARCH_TUNE_H */ > diff --git a/gcc/config/loongarch/loongarch.cc b/gcc/config/loongarch/loongarch.cc > index 8d5d8d965dd..8ee32c90573 100644 > --- a/gcc/config/loongarch/loongarch.cc > +++ b/gcc/config/loongarch/loongarch.cc > @@ -63,6 +63,7 @@ along with GCC; see the file COPYING3. If not see > #include "context.h" > #include "builtins.h" > #include "rtl-iter.h" > +#include "opts.h" > > /* This file should be included last. */ > #include "target-def.h" > @@ -6100,6 +6101,33 @@ loongarch_option_override_internal (struct gcc_options *opts) > if (loongarch_branch_cost == 0) > loongarch_branch_cost = loongarch_cost->branch_cost; > > + /* Set up parameters to be used in prefetching algorithm. */ > + int simultaneous_prefetches > + = loongarch_cpu_cache[LARCH_ACTUAL_TUNE].simultaneous_prefetches; > + > + SET_OPTION_IF_UNSET (opts, &global_options_set, > + param_simultaneous_prefetches, > + simultaneous_prefetches); > + > + SET_OPTION_IF_UNSET (opts, &global_options_set, > + param_l1_cache_line_size, > + loongarch_cpu_cache[LARCH_ACTUAL_TUNE].l1d_line_size); > + > + SET_OPTION_IF_UNSET (opts, &global_options_set, > + param_l1_cache_size, > + loongarch_cpu_cache[LARCH_ACTUAL_TUNE].l1d_size); > + > + SET_OPTION_IF_UNSET (opts, &global_options_set, > + param_l2_cache_size, > + loongarch_cpu_cache[LARCH_ACTUAL_TUNE].l2d_size); > + > + > + /* Enable sw prefetching at -O3 and higher. */ > + if (opts->x_flag_prefetch_loop_arrays < 0 > + && (opts->x_optimize >= 3 || opts->x_flag_profile_use) > + && !opts->x_optimize_size) > + opts->x_flag_prefetch_loop_arrays = 1; > + > if (TARGET_DIRECT_EXTERN_ACCESS && flag_shlib) > error ("%qs cannot be used for compiling a shared library", > "-mdirect-extern-access"); > diff --git a/gcc/config/loongarch/loongarch.md b/gcc/config/loongarch/loongarch.md > index 682ab961741..2fda5381904 100644 > --- a/gcc/config/loongarch/loongarch.md > +++ b/gcc/config/loongarch/loongarch.md > @@ -3282,6 +3282,20 @@ (define_expand "untyped_call" > ;; .................... > ;; > > +(define_insn "prefetch" > + [(prefetch (match_operand 0 "address_operand" "ZD") > + (match_operand 1 "const_int_operand" "n") > + (match_operand 2 "const_int_operand" "n"))] > + "" > +{ > + switch (INTVAL (operands[1])) > + { > + case 0: return "preld\t0,%a0"; > + case 1: return "preld\t8,%a0"; > + default: gcc_unreachable (); > + } > +}) > + > (define_insn "nop" > [(const_int 0)] > ""
在 2022/11/16 上午11:06, WANG Xuerui 写道: > > On 2022/11/16 10:10, Lulu Cheng wrote: >> v2 -> v3: >> 1. Remove preldx support. >> >> --------------------------------------- >> Enable sw prefetching at -O3 and higher. >> >> Co-Authored-By: xujiahao <xujiahao@loongson.cn> >> >> gcc/ChangeLog: >> >> * config/loongarch/constraints.md (ZD): New constraint. >> * config/loongarch/loongarch-def.c: Initial number of parallel >> prefetch. >> * config/loongarch/loongarch-tune.h (struct loongarch_cache): >> Define number of parallel prefetch. >> * config/loongarch/loongarch.cc >> (loongarch_option_override_internal): >> Set up parameters to be used in prefetching algorithm. >> * config/loongarch/loongarch.md (prefetch): New template. >> --- >> gcc/config/loongarch/constraints.md | 10 ++++++++++ >> gcc/config/loongarch/loongarch-def.c | 2 ++ >> gcc/config/loongarch/loongarch-tune.h | 1 + >> gcc/config/loongarch/loongarch.cc | 28 +++++++++++++++++++++++++++ >> gcc/config/loongarch/loongarch.md | 14 ++++++++++++++ >> 5 files changed, 55 insertions(+) >> >> diff --git a/gcc/config/loongarch/constraints.md >> b/gcc/config/loongarch/constraints.md >> index 43cb7b5f0f5..46f7f63ae31 100644 >> --- a/gcc/config/loongarch/constraints.md >> +++ b/gcc/config/loongarch/constraints.md >> @@ -86,6 +86,10 @@ >> ;; "ZB" >> ;; "An address that is held in a general-purpose register. >> ;; The offset is zero" >> +;; "ZD" >> +;; "An address operand whose address is formed by a base register >> +;; and offset that is suitable for use in instructions with the >> same >> +;; addressing mode as @code{preld}." >> ;; "<" "Matches a pre-dec or post-dec operand." (Global >> non-architectural) >> ;; ">" "Matches a pre-inc or post-inc operand." (Global >> non-architectural) >> @@ -190,3 +194,9 @@ (define_memory_constraint "ZB" >> The offset is zero" >> (and (match_code "mem") >> (match_test "REG_P (XEXP (op, 0))"))) >> + >> +(define_address_constraint "ZD" >> + "An address operand whose address is formed by a base register >> + and offset that is suitable for use in instructions with the same >> + addressing mode as @code{preld}." >> + (match_test "loongarch_12bit_offset_address_p (op, mode)")) > > How is this different with the "m" constraint? AFAIK preld and ld > share the same addressing mode (i.e. base register + 12-bit signed > immediate offset). The "m" constraint is defined as follows: (define_memory_constraint "m" * (and (match_code "mem")* (match_test "loongarch_12bit_offset_address_p (XEXP (op, 0), mode)"))) This setting must be a memory operand. ''ZD" constraint is a address operand. I think (mem:mode (address operand)) = memory operand. > >> diff --git a/gcc/config/loongarch/loongarch-def.c >> b/gcc/config/loongarch/loongarch-def.c >> index cbf995d81b5..80ab10a52a8 100644 >> --- a/gcc/config/loongarch/loongarch-def.c >> +++ b/gcc/config/loongarch/loongarch-def.c >> @@ -62,11 +62,13 @@ loongarch_cpu_cache[N_TUNE_TYPES] = { >> .l1d_line_size = 64, >> .l1d_size = 64, >> .l2d_size = 256, >> + .simultaneous_prefetches = 4, >> }, >> [CPU_LA464] = { >> .l1d_line_size = 64, >> .l1d_size = 64, >> .l2d_size = 256, >> + .simultaneous_prefetches = 4, >> }, >> }; >> diff --git a/gcc/config/loongarch/loongarch-tune.h >> b/gcc/config/loongarch/loongarch-tune.h >> index 6f3530f5c02..8e3eb29472b 100644 >> --- a/gcc/config/loongarch/loongarch-tune.h >> +++ b/gcc/config/loongarch/loongarch-tune.h >> @@ -45,6 +45,7 @@ struct loongarch_cache { >> int l1d_line_size; /* bytes */ >> int l1d_size; /* KiB */ >> int l2d_size; /* kiB */ >> + int simultaneous_prefetches; /* number of parallel prefetch */ > nit: "prefetches" or "prefetch ops" or "int prefetch_width"? >> }; >> #endif /* LOONGARCH_TUNE_H */ >> diff --git a/gcc/config/loongarch/loongarch.cc >> b/gcc/config/loongarch/loongarch.cc >> index 8d5d8d965dd..8ee32c90573 100644 >> --- a/gcc/config/loongarch/loongarch.cc >> +++ b/gcc/config/loongarch/loongarch.cc >> @@ -63,6 +63,7 @@ along with GCC; see the file COPYING3. If not see >> #include "context.h" >> #include "builtins.h" >> #include "rtl-iter.h" >> +#include "opts.h" >> /* This file should be included last. */ >> #include "target-def.h" >> @@ -6100,6 +6101,33 @@ loongarch_option_override_internal (struct >> gcc_options *opts) >> if (loongarch_branch_cost == 0) >> loongarch_branch_cost = loongarch_cost->branch_cost; >> + /* Set up parameters to be used in prefetching algorithm. */ >> + int simultaneous_prefetches >> + = loongarch_cpu_cache[LARCH_ACTUAL_TUNE].simultaneous_prefetches; >> + >> + SET_OPTION_IF_UNSET (opts, &global_options_set, >> + param_simultaneous_prefetches, >> + simultaneous_prefetches); >> + >> + SET_OPTION_IF_UNSET (opts, &global_options_set, >> + param_l1_cache_line_size, >> + loongarch_cpu_cache[LARCH_ACTUAL_TUNE].l1d_line_size); >> + >> + SET_OPTION_IF_UNSET (opts, &global_options_set, >> + param_l1_cache_size, >> + loongarch_cpu_cache[LARCH_ACTUAL_TUNE].l1d_size); >> + >> + SET_OPTION_IF_UNSET (opts, &global_options_set, >> + param_l2_cache_size, >> + loongarch_cpu_cache[LARCH_ACTUAL_TUNE].l2d_size); >> + >> + >> + /* Enable sw prefetching at -O3 and higher. */ >> + if (opts->x_flag_prefetch_loop_arrays < 0 >> + && (opts->x_optimize >= 3 || opts->x_flag_profile_use) >> + && !opts->x_optimize_size) >> + opts->x_flag_prefetch_loop_arrays = 1; >> + >> if (TARGET_DIRECT_EXTERN_ACCESS && flag_shlib) >> error ("%qs cannot be used for compiling a shared library", >> "-mdirect-extern-access"); >> diff --git a/gcc/config/loongarch/loongarch.md >> b/gcc/config/loongarch/loongarch.md >> index 682ab961741..2fda5381904 100644 >> --- a/gcc/config/loongarch/loongarch.md >> +++ b/gcc/config/loongarch/loongarch.md >> @@ -3282,6 +3282,20 @@ (define_expand "untyped_call" >> ;; .................... >> ;; >> +(define_insn "prefetch" >> + [(prefetch (match_operand 0 "address_operand" "ZD") >> + (match_operand 1 "const_int_operand" "n") >> + (match_operand 2 "const_int_operand" "n"))] >> + "" >> +{ >> + switch (INTVAL (operands[1])) >> + { >> + case 0: return "preld\t0,%a0"; >> + case 1: return "preld\t8,%a0"; >> + default: gcc_unreachable (); >> + } >> +}) >> + >> (define_insn "nop" >> [(const_int 0)] >> ""
On Wed, 2022-11-16 at 11:19 +0800, Lulu Cheng wrote: > The "m" constraint is defined as follows: > (define_memory_constraint "m" > (and (match_code "mem") > (match_test "loongarch_12bit_offset_address_p (XEXP (op, 0), > mode)"))) > This setting must be a memory operand. > ''ZD" constraint is a address operand. > I think (mem:mode (address operand)) = memory operand. Yes they are different. I tried reusing "m" in my previous attempt to add prefetch instruction but it didn't work.
LGTM. A minor issue is "enabling -fprefetch-loop-arrays at -O3" is not documented, but AArch64 and i386 are already doing this anyway. We can add the fact into the doc later. On Wed, 2022-11-16 at 10:10 +0800, Lulu Cheng wrote: > v2 -> v3: > 1. Remove preldx support. > > --------------------------------------- > Enable sw prefetching at -O3 and higher. > > Co-Authored-By: xujiahao <xujiahao@loongson.cn> > > gcc/ChangeLog: > > * config/loongarch/constraints.md (ZD): New constraint. > * config/loongarch/loongarch-def.c: Initial number of parallel > prefetch. > * config/loongarch/loongarch-tune.h (struct loongarch_cache): > Define number of parallel prefetch. > * config/loongarch/loongarch.cc > (loongarch_option_override_internal): > Set up parameters to be used in prefetching algorithm. > * config/loongarch/loongarch.md (prefetch): New template. > --- > gcc/config/loongarch/constraints.md | 10 ++++++++++ > gcc/config/loongarch/loongarch-def.c | 2 ++ > gcc/config/loongarch/loongarch-tune.h | 1 + > gcc/config/loongarch/loongarch.cc | 28 > +++++++++++++++++++++++++++ > gcc/config/loongarch/loongarch.md | 14 ++++++++++++++ > 5 files changed, 55 insertions(+) > > diff --git a/gcc/config/loongarch/constraints.md > b/gcc/config/loongarch/constraints.md > index 43cb7b5f0f5..46f7f63ae31 100644 > --- a/gcc/config/loongarch/constraints.md > +++ b/gcc/config/loongarch/constraints.md > @@ -86,6 +86,10 @@ > ;; "ZB" > ;; "An address that is held in a general-purpose register. > ;; The offset is zero" > +;; "ZD" > +;; "An address operand whose address is formed by a base register > +;; and offset that is suitable for use in instructions with the > same > +;; addressing mode as @code{preld}." > ;; "<" "Matches a pre-dec or post-dec operand." (Global non- > architectural) > ;; ">" "Matches a pre-inc or post-inc operand." (Global non- > architectural) > > @@ -190,3 +194,9 @@ (define_memory_constraint "ZB" > The offset is zero" > (and (match_code "mem") > (match_test "REG_P (XEXP (op, 0))"))) > + > +(define_address_constraint "ZD" > + "An address operand whose address is formed by a base register > + and offset that is suitable for use in instructions with the same > + addressing mode as @code{preld}." > + (match_test "loongarch_12bit_offset_address_p (op, mode)")) > diff --git a/gcc/config/loongarch/loongarch-def.c > b/gcc/config/loongarch/loongarch-def.c > index cbf995d81b5..80ab10a52a8 100644 > --- a/gcc/config/loongarch/loongarch-def.c > +++ b/gcc/config/loongarch/loongarch-def.c > @@ -62,11 +62,13 @@ loongarch_cpu_cache[N_TUNE_TYPES] = { > .l1d_line_size = 64, > .l1d_size = 64, > .l2d_size = 256, > + .simultaneous_prefetches = 4, > }, > [CPU_LA464] = { > .l1d_line_size = 64, > .l1d_size = 64, > .l2d_size = 256, > + .simultaneous_prefetches = 4, > }, > }; > > diff --git a/gcc/config/loongarch/loongarch-tune.h > b/gcc/config/loongarch/loongarch-tune.h > index 6f3530f5c02..8e3eb29472b 100644 > --- a/gcc/config/loongarch/loongarch-tune.h > +++ b/gcc/config/loongarch/loongarch-tune.h > @@ -45,6 +45,7 @@ struct loongarch_cache { > int l1d_line_size; /* bytes */ > int l1d_size; /* KiB */ > int l2d_size; /* kiB */ > + int simultaneous_prefetches; /* number of parallel prefetch */ > }; > > #endif /* LOONGARCH_TUNE_H */ > diff --git a/gcc/config/loongarch/loongarch.cc > b/gcc/config/loongarch/loongarch.cc > index 8d5d8d965dd..8ee32c90573 100644 > --- a/gcc/config/loongarch/loongarch.cc > +++ b/gcc/config/loongarch/loongarch.cc > @@ -63,6 +63,7 @@ along with GCC; see the file COPYING3. If not see > #include "context.h" > #include "builtins.h" > #include "rtl-iter.h" > +#include "opts.h" > > /* This file should be included last. */ > #include "target-def.h" > @@ -6100,6 +6101,33 @@ loongarch_option_override_internal (struct > gcc_options *opts) > if (loongarch_branch_cost == 0) > loongarch_branch_cost = loongarch_cost->branch_cost; > > + /* Set up parameters to be used in prefetching algorithm. */ > + int simultaneous_prefetches > + = loongarch_cpu_cache[LARCH_ACTUAL_TUNE].simultaneous_prefetches; > + > + SET_OPTION_IF_UNSET (opts, &global_options_set, > + param_simultaneous_prefetches, > + simultaneous_prefetches); > + > + SET_OPTION_IF_UNSET (opts, &global_options_set, > + param_l1_cache_line_size, > + > loongarch_cpu_cache[LARCH_ACTUAL_TUNE].l1d_line_size); > + > + SET_OPTION_IF_UNSET (opts, &global_options_set, > + param_l1_cache_size, > + > loongarch_cpu_cache[LARCH_ACTUAL_TUNE].l1d_size); > + > + SET_OPTION_IF_UNSET (opts, &global_options_set, > + param_l2_cache_size, > + > loongarch_cpu_cache[LARCH_ACTUAL_TUNE].l2d_size); > + > + > + /* Enable sw prefetching at -O3 and higher. */ > + if (opts->x_flag_prefetch_loop_arrays < 0 > + && (opts->x_optimize >= 3 || opts->x_flag_profile_use) > + && !opts->x_optimize_size) > + opts->x_flag_prefetch_loop_arrays = 1; > + > if (TARGET_DIRECT_EXTERN_ACCESS && flag_shlib) > error ("%qs cannot be used for compiling a shared library", > "-mdirect-extern-access"); > diff --git a/gcc/config/loongarch/loongarch.md > b/gcc/config/loongarch/loongarch.md > index 682ab961741..2fda5381904 100644 > --- a/gcc/config/loongarch/loongarch.md > +++ b/gcc/config/loongarch/loongarch.md > @@ -3282,6 +3282,20 @@ (define_expand "untyped_call" > ;; .................... > ;; > > +(define_insn "prefetch" > + [(prefetch (match_operand 0 "address_operand" "ZD") > + (match_operand 1 "const_int_operand" "n") > + (match_operand 2 "const_int_operand" "n"))] > + "" > +{ > + switch (INTVAL (operands[1])) > + { > + case 0: return "preld\t0,%a0"; > + case 1: return "preld\t8,%a0"; > + default: gcc_unreachable (); > + } > +}) > + > (define_insn "nop" > [(const_int 0)] > ""
Pushed r13-4259. 在 2022/11/16 10:10, Lulu Cheng 写道: > v2 -> v3: > 1. Remove preldx support. > > --------------------------------------- > Enable sw prefetching at -O3 and higher. > > Co-Authored-By: xujiahao <xujiahao@loongson.cn> > > gcc/ChangeLog: > > * config/loongarch/constraints.md (ZD): New constraint. > * config/loongarch/loongarch-def.c: Initial number of parallel prefetch. > * config/loongarch/loongarch-tune.h (struct loongarch_cache): > Define number of parallel prefetch. > * config/loongarch/loongarch.cc (loongarch_option_override_internal): > Set up parameters to be used in prefetching algorithm. > * config/loongarch/loongarch.md (prefetch): New template. > --- > gcc/config/loongarch/constraints.md | 10 ++++++++++ > gcc/config/loongarch/loongarch-def.c | 2 ++ > gcc/config/loongarch/loongarch-tune.h | 1 + > gcc/config/loongarch/loongarch.cc | 28 +++++++++++++++++++++++++++ > gcc/config/loongarch/loongarch.md | 14 ++++++++++++++ > 5 files changed, 55 insertions(+) > > diff --git a/gcc/config/loongarch/constraints.md b/gcc/config/loongarch/constraints.md > index 43cb7b5f0f5..46f7f63ae31 100644 > --- a/gcc/config/loongarch/constraints.md > +++ b/gcc/config/loongarch/constraints.md > @@ -86,6 +86,10 @@ > ;; "ZB" > ;; "An address that is held in a general-purpose register. > ;; The offset is zero" > +;; "ZD" > +;; "An address operand whose address is formed by a base register > +;; and offset that is suitable for use in instructions with the same > +;; addressing mode as @code{preld}." > ;; "<" "Matches a pre-dec or post-dec operand." (Global non-architectural) > ;; ">" "Matches a pre-inc or post-inc operand." (Global non-architectural) > > @@ -190,3 +194,9 @@ (define_memory_constraint "ZB" > The offset is zero" > (and (match_code "mem") > (match_test "REG_P (XEXP (op, 0))"))) > + > +(define_address_constraint "ZD" > + "An address operand whose address is formed by a base register > + and offset that is suitable for use in instructions with the same > + addressing mode as @code{preld}." > + (match_test "loongarch_12bit_offset_address_p (op, mode)")) > diff --git a/gcc/config/loongarch/loongarch-def.c b/gcc/config/loongarch/loongarch-def.c > index cbf995d81b5..80ab10a52a8 100644 > --- a/gcc/config/loongarch/loongarch-def.c > +++ b/gcc/config/loongarch/loongarch-def.c > @@ -62,11 +62,13 @@ loongarch_cpu_cache[N_TUNE_TYPES] = { > .l1d_line_size = 64, > .l1d_size = 64, > .l2d_size = 256, > + .simultaneous_prefetches = 4, > }, > [CPU_LA464] = { > .l1d_line_size = 64, > .l1d_size = 64, > .l2d_size = 256, > + .simultaneous_prefetches = 4, > }, > }; > > diff --git a/gcc/config/loongarch/loongarch-tune.h b/gcc/config/loongarch/loongarch-tune.h > index 6f3530f5c02..8e3eb29472b 100644 > --- a/gcc/config/loongarch/loongarch-tune.h > +++ b/gcc/config/loongarch/loongarch-tune.h > @@ -45,6 +45,7 @@ struct loongarch_cache { > int l1d_line_size; /* bytes */ > int l1d_size; /* KiB */ > int l2d_size; /* kiB */ > + int simultaneous_prefetches; /* number of parallel prefetch */ > }; > > #endif /* LOONGARCH_TUNE_H */ > diff --git a/gcc/config/loongarch/loongarch.cc b/gcc/config/loongarch/loongarch.cc > index 8d5d8d965dd..8ee32c90573 100644 > --- a/gcc/config/loongarch/loongarch.cc > +++ b/gcc/config/loongarch/loongarch.cc > @@ -63,6 +63,7 @@ along with GCC; see the file COPYING3. If not see > #include "context.h" > #include "builtins.h" > #include "rtl-iter.h" > +#include "opts.h" > > /* This file should be included last. */ > #include "target-def.h" > @@ -6100,6 +6101,33 @@ loongarch_option_override_internal (struct gcc_options *opts) > if (loongarch_branch_cost == 0) > loongarch_branch_cost = loongarch_cost->branch_cost; > > + /* Set up parameters to be used in prefetching algorithm. */ > + int simultaneous_prefetches > + = loongarch_cpu_cache[LARCH_ACTUAL_TUNE].simultaneous_prefetches; > + > + SET_OPTION_IF_UNSET (opts, &global_options_set, > + param_simultaneous_prefetches, > + simultaneous_prefetches); > + > + SET_OPTION_IF_UNSET (opts, &global_options_set, > + param_l1_cache_line_size, > + loongarch_cpu_cache[LARCH_ACTUAL_TUNE].l1d_line_size); > + > + SET_OPTION_IF_UNSET (opts, &global_options_set, > + param_l1_cache_size, > + loongarch_cpu_cache[LARCH_ACTUAL_TUNE].l1d_size); > + > + SET_OPTION_IF_UNSET (opts, &global_options_set, > + param_l2_cache_size, > + loongarch_cpu_cache[LARCH_ACTUAL_TUNE].l2d_size); > + > + > + /* Enable sw prefetching at -O3 and higher. */ > + if (opts->x_flag_prefetch_loop_arrays < 0 > + && (opts->x_optimize >= 3 || opts->x_flag_profile_use) > + && !opts->x_optimize_size) > + opts->x_flag_prefetch_loop_arrays = 1; > + > if (TARGET_DIRECT_EXTERN_ACCESS && flag_shlib) > error ("%qs cannot be used for compiling a shared library", > "-mdirect-extern-access"); > diff --git a/gcc/config/loongarch/loongarch.md b/gcc/config/loongarch/loongarch.md > index 682ab961741..2fda5381904 100644 > --- a/gcc/config/loongarch/loongarch.md > +++ b/gcc/config/loongarch/loongarch.md > @@ -3282,6 +3282,20 @@ (define_expand "untyped_call" > ;; .................... > ;; > > +(define_insn "prefetch" > + [(prefetch (match_operand 0 "address_operand" "ZD") > + (match_operand 1 "const_int_operand" "n") > + (match_operand 2 "const_int_operand" "n"))] > + "" > +{ > + switch (INTVAL (operands[1])) > + { > + case 0: return "preld\t0,%a0"; > + case 1: return "preld\t8,%a0"; > + default: gcc_unreachable (); > + } > +}) > + > (define_insn "nop" > [(const_int 0)] > ""
diff --git a/gcc/config/loongarch/constraints.md b/gcc/config/loongarch/constraints.md index 43cb7b5f0f5..46f7f63ae31 100644 --- a/gcc/config/loongarch/constraints.md +++ b/gcc/config/loongarch/constraints.md @@ -86,6 +86,10 @@ ;; "ZB" ;; "An address that is held in a general-purpose register. ;; The offset is zero" +;; "ZD" +;; "An address operand whose address is formed by a base register +;; and offset that is suitable for use in instructions with the same +;; addressing mode as @code{preld}." ;; "<" "Matches a pre-dec or post-dec operand." (Global non-architectural) ;; ">" "Matches a pre-inc or post-inc operand." (Global non-architectural) @@ -190,3 +194,9 @@ (define_memory_constraint "ZB" The offset is zero" (and (match_code "mem") (match_test "REG_P (XEXP (op, 0))"))) + +(define_address_constraint "ZD" + "An address operand whose address is formed by a base register + and offset that is suitable for use in instructions with the same + addressing mode as @code{preld}." + (match_test "loongarch_12bit_offset_address_p (op, mode)")) diff --git a/gcc/config/loongarch/loongarch-def.c b/gcc/config/loongarch/loongarch-def.c index cbf995d81b5..80ab10a52a8 100644 --- a/gcc/config/loongarch/loongarch-def.c +++ b/gcc/config/loongarch/loongarch-def.c @@ -62,11 +62,13 @@ loongarch_cpu_cache[N_TUNE_TYPES] = { .l1d_line_size = 64, .l1d_size = 64, .l2d_size = 256, + .simultaneous_prefetches = 4, }, [CPU_LA464] = { .l1d_line_size = 64, .l1d_size = 64, .l2d_size = 256, + .simultaneous_prefetches = 4, }, }; diff --git a/gcc/config/loongarch/loongarch-tune.h b/gcc/config/loongarch/loongarch-tune.h index 6f3530f5c02..8e3eb29472b 100644 --- a/gcc/config/loongarch/loongarch-tune.h +++ b/gcc/config/loongarch/loongarch-tune.h @@ -45,6 +45,7 @@ struct loongarch_cache { int l1d_line_size; /* bytes */ int l1d_size; /* KiB */ int l2d_size; /* kiB */ + int simultaneous_prefetches; /* number of parallel prefetch */ }; #endif /* LOONGARCH_TUNE_H */ diff --git a/gcc/config/loongarch/loongarch.cc b/gcc/config/loongarch/loongarch.cc index 8d5d8d965dd..8ee32c90573 100644 --- a/gcc/config/loongarch/loongarch.cc +++ b/gcc/config/loongarch/loongarch.cc @@ -63,6 +63,7 @@ along with GCC; see the file COPYING3. If not see #include "context.h" #include "builtins.h" #include "rtl-iter.h" +#include "opts.h" /* This file should be included last. */ #include "target-def.h" @@ -6100,6 +6101,33 @@ loongarch_option_override_internal (struct gcc_options *opts) if (loongarch_branch_cost == 0) loongarch_branch_cost = loongarch_cost->branch_cost; + /* Set up parameters to be used in prefetching algorithm. */ + int simultaneous_prefetches + = loongarch_cpu_cache[LARCH_ACTUAL_TUNE].simultaneous_prefetches; + + SET_OPTION_IF_UNSET (opts, &global_options_set, + param_simultaneous_prefetches, + simultaneous_prefetches); + + SET_OPTION_IF_UNSET (opts, &global_options_set, + param_l1_cache_line_size, + loongarch_cpu_cache[LARCH_ACTUAL_TUNE].l1d_line_size); + + SET_OPTION_IF_UNSET (opts, &global_options_set, + param_l1_cache_size, + loongarch_cpu_cache[LARCH_ACTUAL_TUNE].l1d_size); + + SET_OPTION_IF_UNSET (opts, &global_options_set, + param_l2_cache_size, + loongarch_cpu_cache[LARCH_ACTUAL_TUNE].l2d_size); + + + /* Enable sw prefetching at -O3 and higher. */ + if (opts->x_flag_prefetch_loop_arrays < 0 + && (opts->x_optimize >= 3 || opts->x_flag_profile_use) + && !opts->x_optimize_size) + opts->x_flag_prefetch_loop_arrays = 1; + if (TARGET_DIRECT_EXTERN_ACCESS && flag_shlib) error ("%qs cannot be used for compiling a shared library", "-mdirect-extern-access"); diff --git a/gcc/config/loongarch/loongarch.md b/gcc/config/loongarch/loongarch.md index 682ab961741..2fda5381904 100644 --- a/gcc/config/loongarch/loongarch.md +++ b/gcc/config/loongarch/loongarch.md @@ -3282,6 +3282,20 @@ (define_expand "untyped_call" ;; .................... ;; +(define_insn "prefetch" + [(prefetch (match_operand 0 "address_operand" "ZD") + (match_operand 1 "const_int_operand" "n") + (match_operand 2 "const_int_operand" "n"))] + "" +{ + switch (INTVAL (operands[1])) + { + case 0: return "preld\t0,%a0"; + case 1: return "preld\t8,%a0"; + default: gcc_unreachable (); + } +}) + (define_insn "nop" [(const_int 0)] ""