[v2,1/2] RISC-V: Add spill sp adjust check testcase.
Commit Message
This testcase mix exist spill-1.c and adding new fun to check if
there have redundant addi intructions. Idea provided by Jeff Law.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/spill-sp-adjust.c: New test.
---
.../gcc.target/riscv/rvv/base/spill-sp-adjust.c | 13 +++++++++++++
1 file changed, 13 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/spill-sp-adjust.c
Comments
On 11/15/22 01:33, jiawei wrote:
> This testcase mix exist spill-1.c and adding new fun to check if
> there have redundant addi intructions. Idea provided by Jeff Law.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/rvv/base/spill-sp-adjust.c: New test.
I made several whitespace/formatting fixes to the riscv.cc part of this
series, improved the Changelog and and committed it for you.
Thanks,
Jeff
new file mode 100644
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv" } */
+
+#include "spill-1.c"
+
+void
+spill_sp_adjust (int8_t *v)
+{
+ vint8mf8_t v1 = *(vint8mf8_t*)v;
+}
+
+/* Make sure we do not have a useless SP adjustment. */
+/* { dg-final { scan-assembler-not "addi\tsp,sp,0" } } */