| Message ID | 20221114162918.1563116-1-jiawei@iscas.ac.cn |
|---|---|
| State | Deferred, archived |
| Headers |
Return-Path: <gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org> X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 5EE7638582BE for <patchwork@sourceware.org>; Mon, 14 Nov 2022 16:29:57 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from cstnet.cn (smtp21.cstnet.cn [159.226.251.21]) by sourceware.org (Postfix) with ESMTP id B80903858D1E for <gcc-patches@gcc.gnu.org>; Mon, 14 Nov 2022 16:29:37 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org B80903858D1E Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=iscas.ac.cn Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=iscas.ac.cn Received: from localhost.localdomain (unknown [47.113.87.88]) by APP-01 (Coremail) with SMTP id qwCowABX92jsbHJjFqrGCQ--.62802S2; Tue, 15 Nov 2022 00:29:32 +0800 (CST) From: jiawei <jiawei@iscas.ac.cn> To: gcc-patches@gcc.gnu.org Cc: kito.cheng@sifive.com, palmer@rivosinc.com, juzhe.zhong@rivai.ai, christoph.muellner@vrull.eu, philipp.tomsich@vrull.eu, wuwei2016@iscas.ac.cn, jiawei <jiawei@iscas.ac.cn> Subject: [PATCH] RISC-V: Optimal RVV epilogue logic. Date: Tue, 15 Nov 2022 00:29:18 +0800 Message-Id: <20221114162918.1563116-1-jiawei@iscas.ac.cn> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-CM-TRANSID: qwCowABX92jsbHJjFqrGCQ--.62802S2 X-Coremail-Antispam: 1UD129KBjvJXoW7Cr1UCF1kCry7Gr45tr1rtFb_yoW8XFyrpF s8Wr1IvF1Yvwn3t3WxtFWakr1UWw4fKw45C34UAr43Aw4DWrW8Wrsxtay3Wr4qgFWkAr97 uF1qkrn0va1xA3DanT9S1TB71UUUUUUqnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUkY14x267AKxVW8JVW5JwAFc2x0x2IEx4CE42xK8VAvwI8IcIk0 rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2ocxC64kIII0Yj41l84x0c7CEw4AK67xGY2AK02 1l84ACjcxK6xIIjxv20xvE14v26r1j6r1xM28EF7xvwVC0I7IYx2IY6xkF7I0E14v26r1j 6r4UM28EF7xvwVC2z280aVAFwI0_Jr0_Gr1l84ACjcxK6I8E87Iv6xkF7I0E14v26r1j6r 4UM2AIxVAIcxkEcVAq07x20xvEncxIr21l5I8CrVACY4xI64kE6c02F40Ex7xfMcIj6xII jxv20xvE14v26r1j6r18McIj6I8E87Iv67AKxVWUJVW8JwAm72CE4IkC6x0Yz7v_Jr0_Gr 1lF7xvr2IYc2Ij64vIr41lF7I21c0EjII2zVCS5cI20VAGYxC7MxkIecxEwVAFjwCF04k2 0xvY0x0EwIxGrwCFx2IqxVCFs4IE7xkEbVWUJVW8JwC20s026c02F40E14v26r1j6r18MI 8I3I0E7480Y4vE14v26r106r1rMI8E67AF67kF1VAFwI0_Jw0_GFylIxkGc2Ij64vIr41l IxAIcVC0I7IYx2IY67AKxVWUJVWUCwCI42IY6xIIjxv20xvEc7CjxVAFwI0_Jr0_Gr1lIx AIcVCF04k26cxKx2IYs7xG6r1j6r1xMIIF0xvEx4A2jsIE14v26r1j6r4UMIIF0xvEx4A2 jsIEc7CjxVAFwI0_Jr0_GrUvcSsGvfC2KfnxnUUI43ZEXa7VUU7GYJUUUUU== X-Originating-IP: [47.113.87.88] X-CM-SenderInfo: 5mld4v3l6l2u1dvotugofq/1tbiCgMKAGNyU1g62QAAs6 X-Spam-Status: No, score=-11.5 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, SPF_HELO_PASS, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list <gcc-patches.gcc.gnu.org> List-Unsubscribe: <https://gcc.gnu.org/mailman/options/gcc-patches>, <mailto:gcc-patches-request@gcc.gnu.org?subject=unsubscribe> List-Archive: <https://gcc.gnu.org/pipermail/gcc-patches/> List-Post: <mailto:gcc-patches@gcc.gnu.org> List-Help: <mailto:gcc-patches-request@gcc.gnu.org?subject=help> List-Subscribe: <https://gcc.gnu.org/mailman/listinfo/gcc-patches>, <mailto:gcc-patches-request@gcc.gnu.org?subject=subscribe> Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" <gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org> |
| Series |
RISC-V: Optimal RVV epilogue logic.
|
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Commit Message
Jiawei
Nov. 14, 2022, 4:29 p.m. UTC
Skip add insn generate if the adjust size equal to zero.
gcc/ChangeLog:
* config/riscv/riscv.cc (riscv_expand_epilogue):
New if control segement.
---
gcc/config/riscv/riscv.cc | 18 ++++++++++--------
1 file changed, 10 insertions(+), 8 deletions(-)
Comments
Could you provide some testcase? On Tue, Nov 15, 2022 at 12:29 AM jiawei <jiawei@iscas.ac.cn> wrote: > > Skip add insn generate if the adjust size equal to zero. > > gcc/ChangeLog: > > * config/riscv/riscv.cc (riscv_expand_epilogue): > New if control segement. > > --- > gcc/config/riscv/riscv.cc | 18 ++++++++++-------- > 1 file changed, 10 insertions(+), 8 deletions(-) > > diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc > index 02a01ca0b7c..af138db7545 100644 > --- a/gcc/config/riscv/riscv.cc > +++ b/gcc/config/riscv/riscv.cc > @@ -5186,24 +5186,26 @@ riscv_expand_epilogue (int style) > } > > /* Get an rtx for STEP1 that we can add to BASE. */ > - rtx adjust = GEN_INT (step1.to_constant ()); > - if (!SMALL_OPERAND (step1.to_constant ())) > + if (step1.to_constant () != 0){ > + rtx adjust = GEN_INT (step1.to_constant ()); > + if (!SMALL_OPERAND (step1.to_constant ())) > { > riscv_emit_move (RISCV_PROLOGUE_TEMP (Pmode), adjust); > adjust = RISCV_PROLOGUE_TEMP (Pmode); > } > > - insn = emit_insn ( > + insn = emit_insn ( > gen_add3_insn (stack_pointer_rtx, stack_pointer_rtx, adjust)); > > - rtx dwarf = NULL_RTX; > - rtx cfa_adjust_rtx = gen_rtx_PLUS (Pmode, stack_pointer_rtx, > + rtx dwarf = NULL_RTX; > + rtx cfa_adjust_rtx = gen_rtx_PLUS (Pmode, stack_pointer_rtx, > GEN_INT (step2)); > > - dwarf = alloc_reg_note (REG_CFA_DEF_CFA, cfa_adjust_rtx, dwarf); > - RTX_FRAME_RELATED_P (insn) = 1; > + dwarf = alloc_reg_note (REG_CFA_DEF_CFA, cfa_adjust_rtx, dwarf); > + RTX_FRAME_RELATED_P (insn) = 1; > > - REG_NOTES (insn) = dwarf; > + REG_NOTES (insn) = dwarf; > + } > } > else if (frame_pointer_needed) > { > -- > 2.25.1 >
> -----原始邮件-----
> 发件人: "Kito Cheng" <kito.cheng@gmail.com>
> 发送时间: 2022-11-15 09:48:26 (星期二)
> 收件人: jiawei <jiawei@iscas.ac.cn>
> 抄送: gcc-patches@gcc.gnu.org, kito.cheng@sifive.com, palmer@rivosinc.com, juzhe.zhong@rivai.ai, christoph.muellner@vrull.eu, philipp.tomsich@vrull.eu, wuwei2016@iscas.ac.cn
> 主题: Re: [PATCH] RISC-V: Optimal RVV epilogue logic.
>
> Could you provide some testcase?
Sorry for not giving a clear description，
You can use amost all testcases in gcc.target/riscv/rvv/base/spill-*.c
compile with -march=rv64gcv and check the assemble file spill-*.s,
before this patch, it will generate assemble code contain additional
`addi sp,sp,0`:
```
csrr t0,vlenb
slli t1,t0,1
add sp,sp,t1
addi sp,sp,0
ld s0,24(sp)
addi sp,sp,32
jr ra
```
after this patch it will removed:
```
csrr t0,vlenb
slli t1,t0,1
add sp,sp,t1
ld s0,24(sp)
addi sp,sp,32
jr ra
```
>
> On Tue, Nov 15, 2022 at 12:29 AM jiawei <jiawei@iscas.ac.cn> wrote:
> >
> > Skip add insn generate if the adjust size equal to zero.
> >
> > gcc/ChangeLog:
> >
> > * config/riscv/riscv.cc (riscv_expand_epilogue):
> > New if control segement.
> >
> > ---
> > gcc/config/riscv/riscv.cc | 18 ++++++++++--------
> > 1 file changed, 10 insertions(+), 8 deletions(-)
> >
> > diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
> > index 02a01ca0b7c..af138db7545 100644
> > --- a/gcc/config/riscv/riscv.cc
> > +++ b/gcc/config/riscv/riscv.cc
> > @@ -5186,24 +5186,26 @@ riscv_expand_epilogue (int style)
> > }
> >
> > /* Get an rtx for STEP1 that we can add to BASE. */
> > - rtx adjust = GEN_INT (step1.to_constant ());
> > - if (!SMALL_OPERAND (step1.to_constant ()))
> > + if (step1.to_constant () != 0){
> > + rtx adjust = GEN_INT (step1.to_constant ());
> > + if (!SMALL_OPERAND (step1.to_constant ()))
> > {
> > riscv_emit_move (RISCV_PROLOGUE_TEMP (Pmode), adjust);
> > adjust = RISCV_PROLOGUE_TEMP (Pmode);
> > }
> >
> > - insn = emit_insn (
> > + insn = emit_insn (
> > gen_add3_insn (stack_pointer_rtx, stack_pointer_rtx, adjust));
> >
> > - rtx dwarf = NULL_RTX;
> > - rtx cfa_adjust_rtx = gen_rtx_PLUS (Pmode, stack_pointer_rtx,
> > + rtx dwarf = NULL_RTX;
> > + rtx cfa_adjust_rtx = gen_rtx_PLUS (Pmode, stack_pointer_rtx,
> > GEN_INT (step2));
> >
> > - dwarf = alloc_reg_note (REG_CFA_DEF_CFA, cfa_adjust_rtx, dwarf);
> > - RTX_FRAME_RELATED_P (insn) = 1;
> > + dwarf = alloc_reg_note (REG_CFA_DEF_CFA, cfa_adjust_rtx, dwarf);
> > + RTX_FRAME_RELATED_P (insn) = 1;
> >
> > - REG_NOTES (insn) = dwarf;
> > + REG_NOTES (insn) = dwarf;
> > + }
> > }
> > else if (frame_pointer_needed)
> > {
> > --
> > 2.25.1
> >
</jiawei@iscas.ac.cn></jiawei@iscas.ac.cn></kito.cheng@gmail.com>
I think you'd better change assembler checking of "spill-*.c" cases.
Check they don't have "addi sp,sp,0" redundant instruction.
Let's see whether Kito aggree with that.
juzhe.zhong@rivai.ai
From: jiawei
Date: 2022-11-15 10:37
To: Kito Cheng
CC: gcc-patches; kito.cheng; palmer; juzhe.zhong; christoph.muellner; philipp.tomsich; wuwei2016
Subject: Re: Re: [PATCH] RISC-V: Optimal RVV epilogue logic.
> -----原始邮件-----
> 发件人: "Kito Cheng" <kito.cheng@gmail.com>
> 发送时间: 2022-11-15 09:48:26 (星期二)
> 收件人: jiawei <jiawei@iscas.ac.cn>
> 抄送: gcc-patches@gcc.gnu.org, kito.cheng@sifive.com, palmer@rivosinc.com, juzhe.zhong@rivai.ai, christoph.muellner@vrull.eu, philipp.tomsich@vrull.eu, wuwei2016@iscas.ac.cn
> 主题: Re: [PATCH] RISC-V: Optimal RVV epilogue logic.
>
> Could you provide some testcase?
Sorry for not giving a clear description，
You can use amost all testcases in gcc.target/riscv/rvv/base/spill-*.c
compile with -march=rv64gcv and check the assemble file spill-*.s,
before this patch, it will generate assemble code contain additional
`addi sp,sp,0`:
```
csrr t0,vlenb
slli t1,t0,1
add sp,sp,t1
addi sp,sp,0
ld s0,24(sp)
addi sp,sp,32
jr ra
```
after this patch it will removed:
```
csrr t0,vlenb
slli t1,t0,1
add sp,sp,t1
ld s0,24(sp)
addi sp,sp,32
jr ra
```
>
> On Tue, Nov 15, 2022 at 12:29 AM jiawei <jiawei@iscas.ac.cn> wrote:
> >
> > Skip add insn generate if the adjust size equal to zero.
> >
> > gcc/ChangeLog:
> >
> > * config/riscv/riscv.cc (riscv_expand_epilogue):
> > New if control segement.
> >
> > ---
> > gcc/config/riscv/riscv.cc | 18 ++++++++++--------
> > 1 file changed, 10 insertions(+), 8 deletions(-)
> >
> > diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
> > index 02a01ca0b7c..af138db7545 100644
> > --- a/gcc/config/riscv/riscv.cc
> > +++ b/gcc/config/riscv/riscv.cc
> > @@ -5186,24 +5186,26 @@ riscv_expand_epilogue (int style)
> > }
> >
> > /* Get an rtx for STEP1 that we can add to BASE. */
> > - rtx adjust = GEN_INT (step1.to_constant ());
> > - if (!SMALL_OPERAND (step1.to_constant ()))
> > + if (step1.to_constant () != 0){
> > + rtx adjust = GEN_INT (step1.to_constant ());
> > + if (!SMALL_OPERAND (step1.to_constant ()))
> > {
> > riscv_emit_move (RISCV_PROLOGUE_TEMP (Pmode), adjust);
> > adjust = RISCV_PROLOGUE_TEMP (Pmode);
> > }
> >
> > - insn = emit_insn (
> > + insn = emit_insn (
> > gen_add3_insn (stack_pointer_rtx, stack_pointer_rtx, adjust));
> >
> > - rtx dwarf = NULL_RTX;
> > - rtx cfa_adjust_rtx = gen_rtx_PLUS (Pmode, stack_pointer_rtx,
> > + rtx dwarf = NULL_RTX;
> > + rtx cfa_adjust_rtx = gen_rtx_PLUS (Pmode, stack_pointer_rtx,
> > GEN_INT (step2));
> >
> > - dwarf = alloc_reg_note (REG_CFA_DEF_CFA, cfa_adjust_rtx, dwarf);
> > - RTX_FRAME_RELATED_P (insn) = 1;
> > + dwarf = alloc_reg_note (REG_CFA_DEF_CFA, cfa_adjust_rtx, dwarf);
> > + RTX_FRAME_RELATED_P (insn) = 1;
> >
> > - REG_NOTES (insn) = dwarf;
> > + REG_NOTES (insn) = dwarf;
> > + }
> > }
> > else if (frame_pointer_needed)
> > {
> > --
> > 2.25.1
> >
</jiawei@iscas.ac.cn></jiawei@iscas.ac.cn></kito.cheng@gmail.com>
I would suggest add a sperated case and scan-assembly-not to demonstrate this patch. juzhe.zhong@rivai.ai <juzhe.zhong@rivai.ai> 於 2022年11月15日 週二 10:47 寫道： > I think you'd better change assembler checking of "spill-*.c" cases. > Check they don't have "addi sp,sp,0" redundant instruction. > Let's see whether Kito aggree with that. > ------------------------------ > juzhe.zhong@rivai.ai > > > *From:* jiawei <jiawei@iscas.ac.cn> > *Date:* 2022-11-15 10:37 > *To:* Kito Cheng <kito.cheng@gmail.com> > *CC:* gcc-patches <gcc-patches@gcc.gnu.org>; kito.cheng > <kito.cheng@sifive.com>; palmer <palmer@rivosinc.com>; juzhe.zhong > <juzhe.zhong@rivai.ai>; christoph.muellner <christoph.muellner@vrull.eu>; > philipp.tomsich <philipp.tomsich@vrull.eu>; wuwei2016 > <wuwei2016@iscas.ac.cn> > *Subject:* Re: Re: [PATCH] RISC-V: Optimal RVV epilogue logic. > > -----原始邮件----- > > 发件人: "Kito Cheng" <kito.cheng@gmail.com> > > 发送时间: 2022-11-15 09:48:26 (星期二) > > 收件人: jiawei <jiawei@iscas.ac.cn> > > 抄送: gcc-patches@gcc.gnu.org, kito.cheng@sifive.com, > palmer@rivosinc.com, juzhe.zhong@rivai.ai, christoph.muellner@vrull.eu, > philipp.tomsich@vrull.eu, wuwei2016@iscas.ac.cn > > 主题: Re: [PATCH] RISC-V: Optimal RVV epilogue logic. > > > > Could you provide some testcase? > > Sorry for not giving a clear description， > > You can use amost all testcases in gcc.target/riscv/rvv/base/spill-*.c > > compile with -march=rv64gcv and check the assemble file spill-*.s, > > before this patch, it will generate assemble code contain additional > > `addi sp,sp,0`: > > ``` > csrr t0,vlenb > slli t1,t0,1 > add sp,sp,t1 > addi sp,sp,0 > ld s0,24(sp) > addi sp,sp,32 > jr ra > ``` > > after this patch it will removed: > > ``` > csrr t0,vlenb > slli t1,t0,1 > add sp,sp,t1 > ld s0,24(sp) > addi sp,sp,32 > jr ra > ``` > > > > > On Tue, Nov 15, 2022 at 12:29 AM jiawei <jiawei@iscas.ac.cn> wrote: > > > > > > Skip add insn generate if the adjust size equal to zero. > > > > > > gcc/ChangeLog: > > > > > > * config/riscv/riscv.cc (riscv_expand_epilogue): > > > New if control segement. > > > > > > --- > > > gcc/config/riscv/riscv.cc | 18 ++++++++++-------- > > > 1 file changed, 10 insertions(+), 8 deletions(-) > > > > > > diff --git a/gcc/config/riscv/riscv.cc > b/gcc/config/riscv/riscv.cc > > > index 02a01ca0b7c..af138db7545 100644 > > > --- a/gcc/config/riscv/riscv.cc > > > +++ b/gcc/config/riscv/riscv.cc > > > @@ -5186,24 +5186,26 @@ riscv_expand_epilogue (int style) > > > } > > > > > > /* Get an rtx for STEP1 that we can add to BASE. */ > > > - rtx adjust = GEN_INT (step1.to_constant ()); > > > - if (!SMALL_OPERAND (step1.to_constant ())) > > > + if (step1.to_constant () != 0){ > > > + rtx adjust = GEN_INT (step1.to_constant ()); > > > + if (!SMALL_OPERAND (step1.to_constant ())) > > > { > > > riscv_emit_move (RISCV_PROLOGUE_TEMP (Pmode), adjust); > > > adjust = RISCV_PROLOGUE_TEMP (Pmode); > > > } > > > > > > - insn = emit_insn ( > > > + insn = emit_insn ( > > > gen_add3_insn (stack_pointer_rtx, > stack_pointer_rtx, adjust)); > > > > > > - rtx dwarf = NULL_RTX; > > > - rtx cfa_adjust_rtx = gen_rtx_PLUS (Pmode, > stack_pointer_rtx, > > > + rtx dwarf = NULL_RTX; > > > + rtx cfa_adjust_rtx = gen_rtx_PLUS (Pmode, > stack_pointer_rtx, > > > GEN_INT (step2)); > > > > > > - dwarf = alloc_reg_note (REG_CFA_DEF_CFA, cfa_adjust_rtx, > dwarf); > > > - RTX_FRAME_RELATED_P (insn) = 1; > > > + dwarf = alloc_reg_note (REG_CFA_DEF_CFA, > cfa_adjust_rtx, dwarf); > > > + RTX_FRAME_RELATED_P (insn) = 1; > > > > > > - REG_NOTES (insn) = dwarf; > > > + REG_NOTES (insn) = dwarf; > > > + } > > > } > > > else if (frame_pointer_needed) > > > { > > > -- > > > 2.25.1 > > > > </jiawei@iscas.ac.cn></jiawei@iscas.ac.cn></kito.cheng@gmail.com> > >
On 11/14/22 09:29, jiawei wrote: > Skip add insn generate if the adjust size equal to zero. > > gcc/ChangeLog: > > * config/riscv/riscv.cc (riscv_expand_epilogue): > New if control segement. > > --- > gcc/config/riscv/riscv.cc | 18 ++++++++++-------- > 1 file changed, 10 insertions(+), 8 deletions(-) > > diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc > index 02a01ca0b7c..af138db7545 100644 > --- a/gcc/config/riscv/riscv.cc > +++ b/gcc/config/riscv/riscv.cc > @@ -5186,24 +5186,26 @@ riscv_expand_epilogue (int style) > } > > /* Get an rtx for STEP1 that we can add to BASE. */ > - rtx adjust = GEN_INT (step1.to_constant ()); > - if (!SMALL_OPERAND (step1.to_constant ())) > + if (step1.to_constant () != 0){ This doesn't follow GCC formatting rules. The open-curley should go on a new line, intended two spaces further in. This will (of course) cause other code to need to be reindented as well. Jeff
On 11/14/22 20:13, Kito Cheng wrote: > I would suggest add a sperated case and scan-assembly-not to demonstrate > this patch. Agreed. One way to do this would be to have new tests which have the proper dg-directives for testing this issue and #include the original test. So, something like this: /* { dg-do compile } */ /* { dg-options "-march=rv32gcv -mabi=ilp32 -mpreferred-stack-boundary=3 -O3 -fno-schedule-insns -fno-schedule-insns2" } */ #include "spill-1.c" /* Make sure we do not have a useless SP adjustment. */ /* { dg-final { scan-assembler-not "addi sp, sp, 0" } } */ The key thing to know is that the dg directives are parsed by the framework before preprocessing. So the dg-directives in spill-1.c would not affect this new test. That requires us to provide our own, both for how to run the test and what to look for. Jeff
On Mon, 14 Nov 2022 at 17:29, jiawei <jiawei@iscas.ac.cn> wrote: > > Skip add insn generate if the adjust size equal to zero. > > gcc/ChangeLog: > > * config/riscv/riscv.cc (riscv_expand_epilogue): > New if control segement. > > --- > gcc/config/riscv/riscv.cc | 18 ++++++++++-------- > 1 file changed, 10 insertions(+), 8 deletions(-) > > diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc > index 02a01ca0b7c..af138db7545 100644 > --- a/gcc/config/riscv/riscv.cc > +++ b/gcc/config/riscv/riscv.cc > @@ -5186,24 +5186,26 @@ riscv_expand_epilogue (int style) > } > > /* Get an rtx for STEP1 that we can add to BASE. */ > - rtx adjust = GEN_INT (step1.to_constant ()); > - if (!SMALL_OPERAND (step1.to_constant ())) > + if (step1.to_constant () != 0){ > + rtx adjust = GEN_INT (step1.to_constant ()); > + if (!SMALL_OPERAND (step1.to_constant ())) Please take a look at the recent improvements for the add<mode>3 expander (recently submitted as https://patchwork.ozlabs.org/project/gcc/patch/20221109230718.3240479-1-philipp.tomsich@vrull.eu/). Maybe you also want to use the test for the addi_operand(...) instead of SMALL_OPERAND? > { > riscv_emit_move (RISCV_PROLOGUE_TEMP (Pmode), adjust); > adjust = RISCV_PROLOGUE_TEMP (Pmode); > } > > - insn = emit_insn ( > + insn = emit_insn ( > gen_add3_insn (stack_pointer_rtx, stack_pointer_rtx, adjust)); > > - rtx dwarf = NULL_RTX; > - rtx cfa_adjust_rtx = gen_rtx_PLUS (Pmode, stack_pointer_rtx, > + rtx dwarf = NULL_RTX; > + rtx cfa_adjust_rtx = gen_rtx_PLUS (Pmode, stack_pointer_rtx, > GEN_INT (step2)); > > - dwarf = alloc_reg_note (REG_CFA_DEF_CFA, cfa_adjust_rtx, dwarf); > - RTX_FRAME_RELATED_P (insn) = 1; > + dwarf = alloc_reg_note (REG_CFA_DEF_CFA, cfa_adjust_rtx, dwarf); > + RTX_FRAME_RELATED_P (insn) = 1; > > - REG_NOTES (insn) = dwarf; > + REG_NOTES (insn) = dwarf; > + } > } > else if (frame_pointer_needed) > { > -- > 2.25.1 >
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index 02a01ca0b7c..af138db7545 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -5186,24 +5186,26 @@ riscv_expand_epilogue (int style) } /* Get an rtx for STEP1 that we can add to BASE. */ - rtx adjust = GEN_INT (step1.to_constant ()); - if (!SMALL_OPERAND (step1.to_constant ())) + if (step1.to_constant () != 0){ + rtx adjust = GEN_INT (step1.to_constant ()); + if (!SMALL_OPERAND (step1.to_constant ())) { riscv_emit_move (RISCV_PROLOGUE_TEMP (Pmode), adjust); adjust = RISCV_PROLOGUE_TEMP (Pmode); } - insn = emit_insn ( + insn = emit_insn ( gen_add3_insn (stack_pointer_rtx, stack_pointer_rtx, adjust)); - rtx dwarf = NULL_RTX; - rtx cfa_adjust_rtx = gen_rtx_PLUS (Pmode, stack_pointer_rtx, + rtx dwarf = NULL_RTX; + rtx cfa_adjust_rtx = gen_rtx_PLUS (Pmode, stack_pointer_rtx, GEN_INT (step2)); - dwarf = alloc_reg_note (REG_CFA_DEF_CFA, cfa_adjust_rtx, dwarf); - RTX_FRAME_RELATED_P (insn) = 1; + dwarf = alloc_reg_note (REG_CFA_DEF_CFA, cfa_adjust_rtx, dwarf); + RTX_FRAME_RELATED_P (insn) = 1; - REG_NOTES (insn) = dwarf; + REG_NOTES (insn) = dwarf; + } } else if (frame_pointer_needed) {