diff mbox series

[7/7] riscv: Add basic extension support for XTheadFmv and XTheadInt

Message ID 20221113214636.2747737-8-christoph.muellner@vrull.eu
State Committed
Headers
Series Add XThead* support |

Commit Message

Christoph Müllner Nov. 13, 2022, 9:46 p.m. UTC 
  From: Christoph Müllner <christoph.muellner@vrull.eu>

This patch add basic support for the XTheadFmv and XTheadInt
ISA extension. As both extensions only contain instruction,
which are not supposed to be emitted by the compiler, the support
only covers awareness of the extension name in the march string
and the definition of a feature test macro.

gcc/ChangeLog:

	* common/config/riscv/riscv-common.cc: Add xtheadfmv and
	  xtheadint.
	* config/riscv/riscv-opts.h (MASK_XTHEADMAC): New.
	(MASK_XTHEADFMV): New.
	(TARGET_XTHEADFMV): New.
	(MASK_XTHEADINT): New.
	(TARGET_XTHEADINT): New.
	(MASK_XTHEADMEMIDX): New.
	(MASK_XTHEADSYNC): New.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/xtheadfmv.c: New test.
	* gcc.target/riscv/xtheadint.c: New test.

Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
---
 gcc/common/config/riscv/riscv-common.cc    |  4 ++++
 gcc/config/riscv/riscv-opts.h              | 10 +++++++---
 gcc/testsuite/gcc.target/riscv/xtheadfmv.c | 14 ++++++++++++++
 gcc/testsuite/gcc.target/riscv/xtheadint.c | 14 ++++++++++++++
 4 files changed, 39 insertions(+), 3 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadfmv.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadint.c

Comments

Cui, Lili via Gcc-patches Nov. 18, 2022, 4:43 a.m. UTC | #1 
On Sun, Nov 13, 2022 at 10:46:36PM +0100, Christoph Muellner wrote:
> From: Christoph Müllner <christoph.muellner@vrull.eu>
> 
> This patch add basic support for the XTheadFmv and XTheadInt
> ISA extension. As both extensions only contain instruction,
> which are not supposed to be emitted by the compiler, the support
> only covers awareness of the extension name in the march string
> and the definition of a feature test macro.
>

I think the XTheadFmv can be emitted when the data is moved between
DImode and DFmode in rv32 target. The intructions are similar to the
move instructions of new standard extension "zfa".

Thanks,
Cooper
diff mbox series

Patch

diff --git a/gcc/common/config/riscv/riscv-common.cc b/gcc/common/config/riscv/riscv-common.cc
index 8e1449d3543..b3e6732dddd 100644
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -228,6 +228,8 @@  static const struct riscv_ext_version riscv_ext_version_table[] =
   {"xtheadcmo", ISA_SPEC_CLASS_NONE, 1, 0},
   {"xtheadcondmov", ISA_SPEC_CLASS_NONE, 1, 0},
   {"xtheadfmemidx", ISA_SPEC_CLASS_NONE, 1, 0},
+  {"xtheadfmv", ISA_SPEC_CLASS_NONE, 1, 0},
+  {"xtheadint", ISA_SPEC_CLASS_NONE, 1, 0},
   {"xtheadmac", ISA_SPEC_CLASS_NONE, 1, 0},
   {"xtheadmemidx", ISA_SPEC_CLASS_NONE, 1, 0},
   {"xtheadsync", ISA_SPEC_CLASS_NONE, 1, 0},
@@ -1263,6 +1265,8 @@  static const riscv_ext_flag_table_t riscv_ext_flag_table[] =
   {"xtheadcmo",     &gcc_options::x_riscv_xthead_subext, MASK_XTHEADCMO},
   {"xtheadcondmov", &gcc_options::x_riscv_xthead_subext, MASK_XTHEADCONDMOV},
   {"xtheadfmemidx", &gcc_options::x_riscv_xthead_subext, MASK_XTHEADFMEMIDX},
+  {"xtheadfmv",     &gcc_options::x_riscv_xthead_subext, MASK_XTHEADFMV},
+  {"xtheadint",     &gcc_options::x_riscv_xthead_subext, MASK_XTHEADINT},
   {"xtheadmac",     &gcc_options::x_riscv_xthead_subext, MASK_XTHEADMAC},
   {"xtheadmemidx",  &gcc_options::x_riscv_xthead_subext, MASK_XTHEADMEMIDX},
   {"xtheadsync",    &gcc_options::x_riscv_xthead_subext, MASK_XTHEADSYNC},
diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h
index 18daac40dbd..c1868dcf284 100644
--- a/gcc/config/riscv/riscv-opts.h
+++ b/gcc/config/riscv/riscv-opts.h
@@ -201,11 +201,15 @@  enum stack_protector_guard {
 #define TARGET_XTHEADCONDMOV	((riscv_xthead_subext & MASK_XTHEADCONDMOV) != 0)
 #define MASK_XTHEADFMEMIDX	(1 << 5)
 #define TARGET_XTHEADFMEMIDX	((riscv_xthead_subext & MASK_XTHEADFMEMIDX) != 0)
-#define MASK_XTHEADMAC		(1 << 6)
+#define MASK_XTHEADFMV		(1 << 6)
+#define TARGET_XTHEADFMV	((riscv_xthead_subext & MASK_XTHEADFMV) != 0)
+#define MASK_XTHEADINT		(1 << 7)
+#define TARGET_XTHEADINT	((riscv_xthead_subext & MASK_XTHEADINT) != 0)
+#define MASK_XTHEADMAC		(1 << 8)
 #define TARGET_XTHEADMAC	((riscv_xthead_subext & MASK_XTHEADMAC) != 0)
-#define MASK_XTHEADMEMIDX	(1 << 7)
+#define MASK_XTHEADMEMIDX	(1 << 9)
 #define TARGET_XTHEADMEMIDX	((riscv_xthead_subext & MASK_XTHEADMEMIDX) != 0)
-#define MASK_XTHEADSYNC		(1 << 8)
+#define MASK_XTHEADSYNC		(1 << 10)
 #define TARGET_XTHEADSYNC	((riscv_xthead_subext & MASK_XTHEADSYNC) != 0)
 
 #endif /* ! GCC_RISCV_OPTS_H */
diff --git a/gcc/testsuite/gcc.target/riscv/xtheadfmv.c b/gcc/testsuite/gcc.target/riscv/xtheadfmv.c
new file mode 100644
index 00000000000..e97e8f461f6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/xtheadfmv.c
@@ -0,0 +1,14 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gc_xtheadfmv" { target { rv32 } } } */
+/* { dg-options "-march=rv64gc_xtheadfmv" { target { rv64 } } } */
+
+#ifndef __riscv_xtheadfmv
+#error Feature macro not defined
+#endif
+
+int
+foo (int a)
+{
+  return a;
+}
+
diff --git a/gcc/testsuite/gcc.target/riscv/xtheadint.c b/gcc/testsuite/gcc.target/riscv/xtheadint.c
new file mode 100644
index 00000000000..ee6989a380e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/xtheadint.c
@@ -0,0 +1,14 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gc_xtheadint" { target { rv32 } } } */
+/* { dg-options "-march=rv64gc_xtheadint" { target { rv64 } } } */
+
+#ifndef __riscv_xtheadint
+#error Feature macro not defined
+#endif
+
+int
+foo (int a)
+{
+  return a;
+}
+