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[62.178.148.172]) by smtp.gmail.com with ESMTPSA id lb17-20020a170907785100b00734bfab4d59sm3432282ejc.170.2022.11.13.13.46.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 13 Nov 2022 13:46:48 -0800 (PST) From: Christoph Muellner To: gcc-patches@gcc.gnu.org, Kito Cheng , Jim Wilson , Palmer Dabbelt , Andrew Waterman , Philipp Tomsich , Cooper Qu , Lifang Xia , Yunhai Shang , Zhiwei Liu Cc: =?utf-8?q?Christoph_M=C3=BCllner?= , quxm Subject: [PATCH 6/7] riscv: thead: Add support for XTheadMac ISA extension Date: Sun, 13 Nov 2022 22:46:35 +0100 Message-Id: <20221113214636.2747737-7-christoph.muellner@vrull.eu> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221113214636.2747737-1-christoph.muellner@vrull.eu> References: <20221113214636.2747737-1-christoph.muellner@vrull.eu> MIME-Version: 1.0 X-Spam-Status: No, score=-12.5 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, JMQ_SPF_NEUTRAL, KAM_MANYTO, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" From: Christoph Müllner The XTheadMac ISA extension provides multiply-accumulate/subtract instructions: * mula/mulaw/mulah * muls/mulsw/mulsh To benefit from middle-end passes, we expand the following named patterns in riscv.md (as they are not T-Head-specific): * maddhisi4 * msubhisi4 gcc/ChangeLog: * config/riscv/riscv.md (maddhisi4): New expand. (msubhisi4): New expand. * config/riscv/thead.md (*th_mula): New pattern. (*th_mulawsi): New pattern. (*th_mulawsi2): New pattern. (*th_maddhisi4): New pattern. (*th_sextw_maddhisi4): New pattern. (*th_muls): New pattern. (*th_mulswsi): New pattern. (*th_mulswsi2): New pattern. (*th_msubhisi4): New pattern. (*th_sextw_msubhisi4): New pattern. gcc/testsuite/ChangeLog: * gcc.target/riscv/thead-mula-1.c: New test. * gcc.target/riscv/thead-mula-2.c: New test. Co-Developed-by: quxm Signed-off-by: quxm Signed-off-by: Christoph Müllner --- gcc/config/riscv/riscv.md | 18 +++ gcc/config/riscv/thead.md | 117 ++++++++++++++++++ gcc/testsuite/gcc.target/riscv/thead-mula-1.c | 40 ++++++ gcc/testsuite/gcc.target/riscv/thead-mula-2.c | 28 +++++ 4 files changed, 203 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/thead-mula-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/thead-mula-2.c diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md index cfe1fd6baea..998169115f2 100644 --- a/gcc/config/riscv/riscv.md +++ b/gcc/config/riscv/riscv.md @@ -3029,6 +3029,24 @@ (define_expand "extzv" FAIL; }) +(define_expand "maddhisi4" + [(set (match_operand:SI 0 "register_operand") + (plus:SI + (mult:SI (sign_extend:SI (match_operand:HI 1 "register_operand")) + (sign_extend:SI (match_operand:HI 2 "register_operand"))) + (match_operand:SI 3 "register_operand")))] + "TARGET_XTHEADMAC" +) + +(define_expand "msubhisi4" + [(set (match_operand:SI 0 "register_operand") + (minus:SI + (match_operand:SI 3 "register_operand") + (mult:SI (sign_extend:SI (match_operand:HI 1 "register_operand")) + (sign_extend:SI (match_operand:HI 2 "register_operand")))))] + "TARGET_XTHEADMAC" +) + (include "bitmanip.md") (include "sync.md") (include "peephole.md") diff --git a/gcc/config/riscv/thead.md b/gcc/config/riscv/thead.md index ad42c03c0ce..f31ba18aa84 100644 --- a/gcc/config/riscv/thead.md +++ b/gcc/config/riscv/thead.md @@ -133,3 +133,120 @@ (define_insn "*th_cond_gpr_mov" th.mveqz\t%0,%z3,%1" [(set_attr "type" "condmove") (set_attr "mode" "")]) + +;; XTheadMac + +(define_insn "*th_mula" + [(set (match_operand:X 0 "register_operand" "=r") + (plus:X (mult:X (match_operand:X 1 "register_operand" "r") + (match_operand:X 2 "register_operand" "r")) + (match_operand:X 3 "register_operand" "0")))] + "TARGET_XTHEADMAC" + "th.mula\\t%0,%1,%2" + [(set_attr "type" "imul") + (set_attr "mode" "")] +) + +(define_insn "*th_mulawsi" + [(set (match_operand:DI 0 "register_operand" "=r") + (sign_extend:DI + (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r")) + (match_operand:SI 3 "register_operand" "0"))))] + "TARGET_XTHEADMAC && TARGET_64BIT" + "th.mulaw\\t%0,%1,%2" + [(set_attr "type" "imul") + (set_attr "mode" "SI")] +) + +(define_insn "*th_mulawsi2" + [(set (match_operand:SI 0 "register_operand" "=r") + (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r")) + (match_operand:SI 3 "register_operand" "0")))] + "TARGET_XTHEADMAC && TARGET_64BIT" + "mulaw\\t%0,%1,%2" + [(set_attr "type" "imul") + (set_attr "mode" "SI")] +) + +(define_insn "*th_maddhisi4" + [(set (match_operand:SI 0 "register_operand" "=r") + (plus:SI (mult:SI (sign_extend:SI (match_operand:HI 1 "register_operand" " r")) + (sign_extend:SI (match_operand:HI 2 "register_operand" " r"))) + (match_operand:SI 3 "register_operand" " 0")))] + "TARGET_XTHEADMAC" + "th.mulah\\t%0,%1,%2" + [(set_attr "type" "imul") + (set_attr "mode" "SI")] +) + +(define_insn "*th_sextw_maddhisi4" + [(set (match_operand:DI 0 "register_operand" "=r") + (sign_extend:DI + (plus:SI (mult:SI (sign_extend:SI (match_operand:HI 1 "register_operand" " r")) + (sign_extend:SI (match_operand:HI 2 "register_operand" " r"))) + (match_operand:SI 3 "register_operand" " 0"))))] + "TARGET_XTHEADMAC && TARGET_64BIT" + "th.mulah\\t%0,%1,%2" + [(set_attr "type" "imul") + (set_attr "mode" "SI")] +) + +(define_insn "*th_muls" + [(set (match_operand:X 0 "register_operand" "=r") + (minus:X (match_operand:X 3 "register_operand" "0") + (mult:X (match_operand:X 1 "register_operand" "r") + (match_operand:X 2 "register_operand" "r"))))] + "TARGET_XTHEADMAC" + "th.muls\\t%0,%1,%2" + [(set_attr "type" "imul") + (set_attr "mode" "")] +) + +(define_insn "*th_mulswsi" + [(set (match_operand:DI 0 "register_operand" "=r") + (sign_extend:DI + (minus:SI (match_operand:SI 3 "register_operand" "0") + (mult:SI (match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r")))))] + "TARGET_XTHEADMAC && TARGET_64BIT" + "th.mulsw\\t%0,%1,%2" + [(set_attr "type" "imul") + (set_attr "mode" "SI")] +) + +(define_insn "*th_mulswsi2" + [(set (match_operand:SI 0 "register_operand" "=r") + (minus:SI (match_operand:SI 3 "register_operand" "0") + (mult:SI (match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r"))))] + "TARGET_XTHEADMAC && TARGET_64BIT" + "th.mulsw\\t%0,%1,%2" + [(set_attr "type" "imul") + (set_attr "mode" "SI")] +) + +(define_insn "*th_msubhisi4" + [(set (match_operand:SI 0 "register_operand" "=r") + (minus:SI (match_operand:SI 3 "register_operand" " 0") + (mult:SI (sign_extend:SI (match_operand:HI 1 "register_operand" " r")) + (sign_extend:SI (match_operand:HI 2 "register_operand" " r")))))] + "TARGET_XTHEADMAC" + "th.mulsh\\t%0,%1,%2" + [(set_attr "type" "imul") + (set_attr "mode" "SI")] +) + +(define_insn "*th_sextw_msubhisi4" + [(set (match_operand:DI 0 "register_operand" "=r") + (sign_extend:DI + (minus:SI (match_operand:SI 3 "register_operand" " 0") + (mult:SI (sign_extend:SI (match_operand:HI 1 "register_operand" " r")) + (sign_extend:SI (match_operand:HI 2 "register_operand" " r"))))))] + "TARGET_XTHEADMAC && TARGET_64BIT" + "th.mulsh\\t%0,%1,%2" + [(set_attr "type" "imul") + (set_attr "mode" "SI")] +) + diff --git a/gcc/testsuite/gcc.target/riscv/thead-mula-1.c b/gcc/testsuite/gcc.target/riscv/thead-mula-1.c new file mode 100644 index 00000000000..446bbdd98a1 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/thead-mula-1.c @@ -0,0 +1,40 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=rv64gc_xtheadmac -mabi=lp64" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-O1" "-Og" } } */ + +long f_mula(long a, long b, long c) +{ + return a + b * c; +} + +long f_muls(long a, long b, long c) +{ + return a - b * c; +} + +int f_mulaw(int a, int b, int c) +{ + return a + b * c; +} + +int f_mulsw(int a, int b, int c) +{ + return a - b * c; +} + +long f_mulah(int a, unsigned short b, unsigned short c) +{ + return a + (int)(short)b * (int)(short)c; +} + +long f_mulsh(int a, unsigned short b, unsigned short c) +{ + return a - (int)(short)b * (int)(short)c; +} + +/* { dg-final { scan-assembler-times "th.mula\t" 1 } } */ +/* { dg-final { scan-assembler-times "th.muls\t" 1 } } */ +/* { dg-final { scan-assembler-times "th.mulaw\t" 1 } } */ +/* { dg-final { scan-assembler-times "th.mulsw\t" 1 } } */ +/* { dg-final { scan-assembler-times "th.mulah\t" 1 } } */ +/* { dg-final { scan-assembler-times "th.mulsh\t" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/thead-mula-2.c b/gcc/testsuite/gcc.target/riscv/thead-mula-2.c new file mode 100644 index 00000000000..87145669573 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/thead-mula-2.c @@ -0,0 +1,28 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=rv32gc_xtheadmac -mabi=ilp32" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-O1" "-Og" } } */ + +long f_mula(long a, long b, long c) +{ + return a + b * c; +} + +long f_muls(long a, long b, long c) +{ + return a - b * c; +} + +long f_mulah(int a, unsigned short b, unsigned short c) +{ + return a + (int)(short)b * (int)(short)c; +} + +long f_mulsh(int a, unsigned short b, unsigned short c) +{ + return a - (int)(short)b * (int)(short)c; +} + +/* { dg-final { scan-assembler-times "th.mula\t" 1 } } */ +/* { dg-final { scan-assembler-times "th.muls\t" 1 } } */ +/* { dg-final { scan-assembler-times "th.mulah\t" 1 } } */ +/* { dg-final { scan-assembler-times "th.mulsh\t" 1 } } */