[5/7] riscv: thead: Add support for XTheadBb ISA extension
Commit Message
From: Christoph Müllner <christoph.muellner@vrull.eu>
The XTheadBb ISA extension provides instructions similar to Zbb:
* th.srri/th.srriw
* th.ext/th.extu
* th.ff1 (count-leading-zeros)
* th.rev/th.revw
Instructions that are not covered, because they don't fit into a
pattern:
* th.ff0 (count-leading-ones)
* th.tstnbz
For the cases where the RISC-V backend already provides instruction
patterns with GCC standard pattern names (e.g. rotatert<mode>), this
patch simply uses expanders so we can match the pattern using unnamed
instruction patterns for zb* and xtheadb*.
gcc/ChangeLog:
* config/riscv/bitmanip.md (clz<mode>2): Add expand.
(ctz<mode>2): Add expand.
(popcount<mode>2): Add expand.
(*<bitmanip_optab>si2): Hide pattern name.
(*<bitmanip_optab>di2): Hide pattern name.
(rotr<mode>3): Add expand.
(*rotrsi3): Hide pattern name.
(*rotrdi3): Hide pattern name.
(*rotrsi3_sext): Hide pattern name.
(bswapdi2): Add expand.
(bswapsi2): Add expand.
(*bswap<mode>2): Hide pattern name.
* config/riscv/riscv.cc (riscv_rtx_costs): Add support for
sign-extract.
* config/riscv/riscv.md (extv<mode>): New expand.
(extzv<mode>): New expand.
* config/riscv/thead.md (*th_srrisi3): New pattern.
(*th_srridi3): New pattern.
(*th_ext<mode>): New pattern.
(*th_extu<mode>): New pattern.
(*th_clz<mode>): New pattern.
(*th_revsi2): New pattern.
(*th_revdi2): New pattern.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/xtheadbb-ext.c: New test.
* gcc.target/riscv/xtheadbb-extu.c: New test.
* gcc.target/riscv/xtheadbb-rev.c: New test.
* gcc.target/riscv/xtheadbb-srri.c: New test.
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
---
gcc/config/riscv/bitmanip.md | 47 ++++++++++++--
gcc/config/riscv/riscv.cc | 10 +++
gcc/config/riscv/riscv.md | 26 ++++++++
gcc/config/riscv/thead.md | 62 +++++++++++++++++++
gcc/testsuite/gcc.target/riscv/xtheadbb-ext.c | 19 ++++++
.../gcc.target/riscv/xtheadbb-extu.c | 12 ++++
gcc/testsuite/gcc.target/riscv/xtheadbb-rev.c | 40 ++++++++++++
.../gcc.target/riscv/xtheadbb-srri.c | 18 ++++++
8 files changed, 228 insertions(+), 6 deletions(-)
create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadbb-ext.c
create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadbb-extu.c
create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadbb-rev.c
create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadbb-srri.c
Comments
On Sun, Nov 13, 2022 at 10:46:34PM +0100, Christoph Muellner wrote:
> +(define_expand "extv<mode>"
> + [(set (match_operand:GPR 0 "register_operand" "=r")
> + (sign_extract:GPR (match_operand:GPR 1 "register_operand" "r")
> + (match_operand 2 "const_int_operand")
> + (match_operand 3 "const_int_operand")))]
> + "TARGET_XTHEADBB"
> +{
> + if (TARGET_XTHEADBB
> + && ((INTVAL (operands[2]) + INTVAL (operands[3]))
> + >= GET_MODE_BITSIZE (GET_MODE (operands[1])).to_constant ()))
> + FAIL;
> +})
> +
> +(define_expand "extzv<mode>"
> + [(set (match_operand:GPR 0 "register_operand" "=r")
> + (zero_extract:GPR (match_operand:GPR 1 "register_operand" "r")
> + (match_operand 2 "const_int_operand")
> + (match_operand 3 "const_int_operand")))]
> + "TARGET_XTHEADBB"
> +{
> + if (TARGET_XTHEADBB
> + && ((INTVAL (operands[2]) + INTVAL (operands[3]))
> + >= GET_MODE_BITSIZE (GET_MODE (operands[1])).to_constant ()))
> + FAIL;
I doubt whether it is necessary to add this judgment here,
and other architectures seem to have not added it. But there's nothing wrong with adding
> +
> +(define_insn "*th_ext<mode>"
> + [(set (match_operand:X 0 "register_operand" "=r")
> + (sign_extract:X (match_operand:X 1 "register_operand" "r")
> + (match_operand 2 "const_int_operand")
> + (match_operand 3 "const_int_operand")))]
> + "TARGET_XTHEADBB"
> +{
> + operands[3] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[3]));
> + return "th.ext\t%0,%1,%2,%3";
> +}
> + [(set_attr "type" "bitmanip")])
> +
> +(define_insn "*th_extu<mode>"
> + [(set (match_operand:X 0 "register_operand" "=r")
> + (zero_extract:X (match_operand:X 1 "register_operand" "r")
> + (match_operand 2 "const_int_operand")
> + (match_operand 3 "const_int_operand")))]
> + "TARGET_XTHEADBB"
> +{
> + operands[3] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[3]));
> + return "th.extu\t%0,%1,%2,%3";
> +}
> + [(set_attr "type" "bitmanip")])
> +
I think the operands[3] should be:
operands[3] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[3])) - 1
Because the ext and extu extract the bits %2..%3, when size is 1, the 2%
equals to 3%.
And a small optimization can be done here, the extzv can generate c.andi
when the start bit is 0 and the size is less than 7.
> +/* { dg-final { scan-assembler-times "th.revw\t" 2 } } */
> +/* { dg-final { scan-assembler-times "th.rev\t" 2 } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/xtheadbb-srri.c b/gcc/testsuite/gcc.target/riscv/xtheadbb-srri.c
> new file mode 100644
> index 00000000000..cd992ae3f0a
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/xtheadbb-srri.c
> @@ -0,0 +1,18 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv64gc_xtheadbb -mabi=lp64" } */
> +/* { dg-skip-if "" { *-*-* } { "-O0" "-g" } } */
> +
> +unsigned long foo1(unsigned long rs1)
> +{
> + long shamt = __riscv_xlen - 11;
> + return (rs1 << shamt) |
> + (rs1 >> ((__riscv_xlen - shamt) & (__riscv_xlen - 1)));
> +}
> +unsigned long foo2(unsigned long rs1)
> +{
> + unsigned long shamt = __riscv_xlen - 11;
> + return (rs1 >> shamt) |
> + (rs1 << ((__riscv_xlen - shamt) & (__riscv_xlen - 1)));
> +}
> +
> +/* { dg-final { scan-assembler-times "th.srri" 2 } } */
Why is there no testcase for ff1 here? It can be generated by the builtin function '__builtin_clzl'.
Thanks,
Cooper
@@ -119,6 +119,21 @@ (define_insn "*slliuw"
;; ZBB extension.
+(define_expand "clz<mode>2"
+ [(set (match_operand:GPR 0 "register_operand")
+ (clz:GPR (match_operand:GPR 1 "register_operand")))]
+ "TARGET_ZBB || TARGET_XTHEADBB")
+
+(define_expand "ctz<mode>2"
+ [(set (match_operand:GPR 0 "register_operand")
+ (ctz:GPR (match_operand:GPR 1 "register_operand")))]
+ "TARGET_ZBB")
+
+(define_expand "popcount<mode>2"
+ [(set (match_operand:GPR 0 "register_operand")
+ (popcount:GPR (match_operand:GPR 1 "register_operand")))]
+ "TARGET_ZBB")
+
(define_insn "*<optab>_not<mode>"
[(set (match_operand:X 0 "register_operand" "=r")
(bitmanip_bitwise:X (not:X (match_operand:X 1 "register_operand" "r"))
@@ -137,7 +152,7 @@ (define_insn "*xor_not<mode>"
[(set_attr "type" "bitmanip")
(set_attr "mode" "<X:MODE>")])
-(define_insn "<bitmanip_optab>si2"
+(define_insn "*<bitmanip_optab>si2"
[(set (match_operand:SI 0 "register_operand" "=r")
(clz_ctz_pcnt:SI (match_operand:SI 1 "register_operand" "r")))]
"TARGET_ZBB"
@@ -154,7 +169,7 @@ (define_insn "*<bitmanip_optab>disi2"
[(set_attr "type" "bitmanip")
(set_attr "mode" "SI")])
-(define_insn "<bitmanip_optab>di2"
+(define_insn "*<bitmanip_optab>di2"
[(set (match_operand:DI 0 "register_operand" "=r")
(clz_ctz_pcnt:DI (match_operand:DI 1 "register_operand" "r")))]
"TARGET_64BIT && TARGET_ZBB"
@@ -194,7 +209,17 @@ (define_insn "*zero_extendhi<GPR:mode>2_zbb"
[(set_attr "type" "bitmanip,load")
(set_attr "mode" "HI")])
-(define_insn "rotrsi3"
+(define_expand "rotr<mode>3"
+ [(set (match_operand:GPR 0 "register_operand")
+ (rotatert:GPR (match_operand:GPR 1 "register_operand")
+ (match_operand:QI 2 "arith_operand")))]
+ "TARGET_ZBB || TARGET_XTHEADBB"
+{
+ if (TARGET_XTHEADBB && !immediate_operand (operands[2], VOIDmode))
+ FAIL;
+})
+
+(define_insn "*rotrsi3"
[(set (match_operand:SI 0 "register_operand" "=r")
(rotatert:SI (match_operand:SI 1 "register_operand" "r")
(match_operand:QI 2 "arith_operand" "rI")))]
@@ -202,7 +227,7 @@ (define_insn "rotrsi3"
"ror%i2%~\t%0,%1,%2"
[(set_attr "type" "bitmanip")])
-(define_insn "rotrdi3"
+(define_insn "*rotrdi3"
[(set (match_operand:DI 0 "register_operand" "=r")
(rotatert:DI (match_operand:DI 1 "register_operand" "r")
(match_operand:QI 2 "arith_operand" "rI")))]
@@ -210,7 +235,7 @@ (define_insn "rotrdi3"
"ror%i2\t%0,%1,%2"
[(set_attr "type" "bitmanip")])
-(define_insn "rotrsi3_sext"
+(define_insn "*rotrsi3_sext"
[(set (match_operand:DI 0 "register_operand" "=r")
(sign_extend:DI (rotatert:SI (match_operand:SI 1 "register_operand" "r")
(match_operand:QI 2 "register_operand" "r"))))]
@@ -242,7 +267,17 @@ (define_insn "rotlsi3_sext"
"rolw\t%0,%1,%2"
[(set_attr "type" "bitmanip")])
-(define_insn "bswap<mode>2"
+(define_expand "bswapdi2"
+ [(set (match_operand:DI 0 "register_operand")
+ (bswap:DI (match_operand:DI 1 "register_operand")))]
+ "TARGET_64BIT && (TARGET_ZBB || TARGET_XTHEADBB)")
+
+(define_expand "bswapsi2"
+ [(set (match_operand:SI 0 "register_operand")
+ (bswap:SI (match_operand:SI 1 "register_operand")))]
+ "(!TARGET_64BIT && TARGET_ZBB) || TARGET_XTHEADBB")
+
+(define_insn "*bswap<mode>2"
[(set (match_operand:X 0 "register_operand" "=r")
(bswap:X (match_operand:X 1 "register_operand" "r")))]
"TARGET_ZBB"
@@ -2377,6 +2377,16 @@ riscv_rtx_costs (rtx x, machine_mode mode, int outer_code, int opno ATTRIBUTE_UN
*total = COSTS_N_INSNS (SINGLE_SHIFT_COST);
return true;
}
+ /* Fall through. */
+ case SIGN_EXTRACT:
+ if (TARGET_XTHEADBB
+ && REG_P (XEXP (x, 0))
+ && CONST_INT_P (XEXP (x, 1))
+ && CONST_INT_P (XEXP (x, 2)))
+ {
+ *total = COSTS_N_INSNS (SINGLE_SHIFT_COST);
+ return true;
+ }
return false;
case ASHIFT:
@@ -3003,6 +3003,32 @@ (define_insn "riscv_prefetchi_<mode>"
"prefetch.i\t%a0"
)
+(define_expand "extv<mode>"
+ [(set (match_operand:GPR 0 "register_operand" "=r")
+ (sign_extract:GPR (match_operand:GPR 1 "register_operand" "r")
+ (match_operand 2 "const_int_operand")
+ (match_operand 3 "const_int_operand")))]
+ "TARGET_XTHEADBB"
+{
+ if (TARGET_XTHEADBB
+ && ((INTVAL (operands[2]) + INTVAL (operands[3]))
+ >= GET_MODE_BITSIZE (GET_MODE (operands[1])).to_constant ()))
+ FAIL;
+})
+
+(define_expand "extzv<mode>"
+ [(set (match_operand:GPR 0 "register_operand" "=r")
+ (zero_extract:GPR (match_operand:GPR 1 "register_operand" "r")
+ (match_operand 2 "const_int_operand")
+ (match_operand 3 "const_int_operand")))]
+ "TARGET_XTHEADBB"
+{
+ if (TARGET_XTHEADBB
+ && ((INTVAL (operands[2]) + INTVAL (operands[3]))
+ >= GET_MODE_BITSIZE (GET_MODE (operands[1])).to_constant ()))
+ FAIL;
+})
+
(include "bitmanip.md")
(include "sync.md")
(include "peephole.md")
@@ -28,6 +28,68 @@ (define_insn "*th_addsl"
[(set_attr "type" "bitmanip")
(set_attr "mode" "<X:MODE>")])
+(define_insn "*th_srrisi3"
+ [(set (match_operand:SI 0 "register_operand" "=r")
+ (rotatert:SI (match_operand:SI 1 "register_operand" "r")
+ (match_operand:QI 2 "immediate_operand" "I")))]
+ "TARGET_XTHEADBB"
+ { return TARGET_64BIT ? "th.srriw\t%0,%1,%2" : "th.srri\t%0,%1,%2"; }
+ [(set_attr "type" "bitmanip")])
+
+(define_insn "*th_srridi3"
+ [(set (match_operand:DI 0 "register_operand" "=r")
+ (rotatert:DI (match_operand:DI 1 "register_operand" "r")
+ (match_operand:QI 2 "immediate_operand" "I")))]
+ "TARGET_XTHEADBB && TARGET_64BIT"
+ "th.srri\t%0,%1,%2"
+ [(set_attr "type" "bitmanip")])
+
+(define_insn "*th_ext<mode>"
+ [(set (match_operand:X 0 "register_operand" "=r")
+ (sign_extract:X (match_operand:X 1 "register_operand" "r")
+ (match_operand 2 "const_int_operand")
+ (match_operand 3 "const_int_operand")))]
+ "TARGET_XTHEADBB"
+{
+ operands[3] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[3]));
+ return "th.ext\t%0,%1,%2,%3";
+}
+ [(set_attr "type" "bitmanip")])
+
+(define_insn "*th_extu<mode>"
+ [(set (match_operand:X 0 "register_operand" "=r")
+ (zero_extract:X (match_operand:X 1 "register_operand" "r")
+ (match_operand 2 "const_int_operand")
+ (match_operand 3 "const_int_operand")))]
+ "TARGET_XTHEADBB"
+{
+ operands[3] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[3]));
+ return "th.extu\t%0,%1,%2,%3";
+}
+ [(set_attr "type" "bitmanip")])
+
+(define_insn "*th_clz<mode>"
+ [(set (match_operand:X 0 "register_operand" "=r")
+ (clz:X (match_operand:X 1 "register_operand" "r")))]
+ "TARGET_XTHEADBB"
+ "th.ff1\t%0,%1"
+ [(set_attr "type" "bitmanip")
+ (set_attr "mode" "<X:MODE>")])
+
+(define_insn "*th_revsi2"
+ [(set (match_operand:SI 0 "register_operand" "=r")
+ (bswap:SI (match_operand:SI 1 "register_operand" "r")))]
+ "TARGET_XTHEADBB"
+ { return TARGET_64BIT ? "th.revw\t%0,%1" : "th.rev\t%0,%1"; }
+ [(set_attr "type" "bitmanip")])
+
+(define_insn "*th_revdi2"
+ [(set (match_operand:DI 0 "register_operand" "=r")
+ (bswap:DI (match_operand:DI 1 "register_operand" "r")))]
+ "TARGET_XTHEADBB && TARGET_64BIT"
+ "th.rev\t%0,%1"
+ [(set_attr "type" "bitmanip")])
+
(define_insn "*th_tst"
[(set (match_operand:X 0 "register_operand" "=r")
(zero_extract:X (match_operand:X 1 "register_operand" "r")
new file mode 100644
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc_xtheadbb -mabi=lp64" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Os" "-Og" } } */
+
+struct bar
+{
+ long a:18;
+ long b:24;
+ long c:22;
+};
+
+long
+foo (struct bar *s)
+{
+ return s->b;
+}
+
+/* { dg-final { scan-assembler "ext\t" } } */
+/* { dg-final { scan-assembler-not "andi" } } */
new file mode 100644
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc_xtheadbb -mabi=lp64" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Os" "-Og" } } */
+
+int
+foo (int a, int b)
+{
+ return ((a & (1 << 25)) ? 5 : 4);
+}
+
+/* { dg-final { scan-assembler "extu\t" } } */
+/* { dg-final { scan-assembler-not "andi" } } */
new file mode 100644
@@ -0,0 +1,40 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc_xtheadbb -mabi=lp64" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-O1" "-Og" } } */
+
+unsigned int
+foo32 (unsigned int x)
+{
+ return (((x << 24) & 0xff000000)
+ | ((x << 8) & 0xff0000)
+ | ((x >> 8) & 0xff00)
+ | ((x >> 24) & 0xff));
+}
+
+unsigned int
+foo32_1 (unsigned int x)
+{
+ return __builtin_bswap32 (x);
+}
+
+unsigned long
+foo64 (unsigned long x)
+{
+ return (((x << 56) & 0xff00000000000000ull)
+ | ((x << 40) & 0xff000000000000ull)
+ | ((x << 24) & 0xff0000000000ull)
+ | ((x << 8) & 0xff00000000ull)
+ | ((x >> 8) & 0xff000000)
+ | ((x >> 24) & 0xff0000)
+ | ((x >> 40) & 0xff00)
+ | ((x >> 56) & 0xff));
+}
+
+unsigned long
+foo64_1 (unsigned long x)
+{
+ return __builtin_bswap64 (x);
+}
+
+/* { dg-final { scan-assembler-times "th.revw\t" 2 } } */
+/* { dg-final { scan-assembler-times "th.rev\t" 2 } } */
new file mode 100644
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc_xtheadbb -mabi=lp64" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-g" } } */
+
+unsigned long foo1(unsigned long rs1)
+{
+ long shamt = __riscv_xlen - 11;
+ return (rs1 << shamt) |
+ (rs1 >> ((__riscv_xlen - shamt) & (__riscv_xlen - 1)));
+}
+unsigned long foo2(unsigned long rs1)
+{
+ unsigned long shamt = __riscv_xlen - 11;
+ return (rs1 >> shamt) |
+ (rs1 << ((__riscv_xlen - shamt) & (__riscv_xlen - 1)));
+}
+
+/* { dg-final { scan-assembler-times "th.srri" 2 } } */