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[62.178.148.172]) by smtp.gmail.com with ESMTPSA id lb17-20020a170907785100b00734bfab4d59sm3432282ejc.170.2022.11.13.13.46.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 13 Nov 2022 13:46:45 -0800 (PST) From: Christoph Muellner To: gcc-patches@gcc.gnu.org, Kito Cheng , Jim Wilson , Palmer Dabbelt , Andrew Waterman , Philipp Tomsich , Cooper Qu , Lifang Xia , Yunhai Shang , Zhiwei Liu Cc: =?utf-8?q?Christoph_M=C3=BCllner?= Subject: [PATCH 3/7] riscv: thead: Add support for XTheadBa and XTheadBs ISA extensions Date: Sun, 13 Nov 2022 22:46:32 +0100 Message-Id: <20221113214636.2747737-4-christoph.muellner@vrull.eu> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221113214636.2747737-1-christoph.muellner@vrull.eu> References: <20221113214636.2747737-1-christoph.muellner@vrull.eu> MIME-Version: 1.0 X-Spam-Status: No, score=-12.5 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, JMQ_SPF_NEUTRAL, KAM_MANYTO, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" From: Christoph Müllner This patch adds support for the following T-Head vendor extensions: * XTheadBa * XTheadBs Both extensions provide just one instruction, that has a counterpart in the similar named Bitmanip ISA extension. gcc/ChangeLog: * config/riscv/riscv.cc (riscv_rtx_costs): Adjust for th.tst. * config/riscv/riscv.md: Include thead.md. * config/riscv/thead.md: New file. gcc/testsuite/ChangeLog: * gcc.target/riscv/xtheadba-addsl-64.c: New test. * gcc.target/riscv/xtheadba-addsl.c: New test. * gcc.target/riscv/xtheadbs-tst.c: New test. Signed-off-by: Christoph Müllner --- gcc/config/riscv/riscv.cc | 4 +- gcc/config/riscv/riscv.md | 1 + gcc/config/riscv/thead.md | 38 +++++++++++++++++++ .../gcc.target/riscv/xtheadba-addsl-64.c | 18 +++++++++ .../gcc.target/riscv/xtheadba-addsl.c | 20 ++++++++++ gcc/testsuite/gcc.target/riscv/xtheadbs-tst.c | 12 ++++++ 6 files changed, 91 insertions(+), 2 deletions(-) create mode 100644 gcc/config/riscv/thead.md create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadba-addsl-64.c create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadba-addsl.c create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadbs-tst.c diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index 02a01ca0b7c..decade0fedd 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -2369,8 +2369,8 @@ riscv_rtx_costs (rtx x, machine_mode mode, int outer_code, int opno ATTRIBUTE_UN *total = COSTS_N_INSNS (SINGLE_SHIFT_COST); return true; } - /* bext pattern for zbs. */ - if (TARGET_ZBS && outer_code == SET + /* bit extraction pattern (zbs:bext, xtheadbs:tst). */ + if ((TARGET_ZBS || TARGET_XTHEADBS) && outer_code == SET && GET_CODE (XEXP (x, 1)) == CONST_INT && INTVAL (XEXP (x, 1)) == 1) { diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md index 798f7370a08..a9254df7820 100644 --- a/gcc/config/riscv/riscv.md +++ b/gcc/config/riscv/riscv.md @@ -3009,3 +3009,4 @@ (define_insn "riscv_prefetchi_" (include "generic.md") (include "sifive-7.md") (include "vector.md") +(include "thead.md") diff --git a/gcc/config/riscv/thead.md b/gcc/config/riscv/thead.md new file mode 100644 index 00000000000..676d10b71d7 --- /dev/null +++ b/gcc/config/riscv/thead.md @@ -0,0 +1,38 @@ +;; Machine description for T-Head vendor extensions +;; Copyright (C) 2021-2022 Free Software Foundation, Inc. + +;; This file is part of GCC. + +;; GCC is free software; you can redistribute it and/or modify +;; it under the terms of the GNU General Public License as published by +;; the Free Software Foundation; either version 3, or (at your option) +;; any later version. + +;; GCC is distributed in the hope that it will be useful, +;; but WITHOUT ANY WARRANTY; without even the implied warranty of +;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +;; GNU General Public License for more details. + +;; You should have received a copy of the GNU General Public License +;; along with GCC; see the file COPYING3. If not see +;; . + +(define_insn "*th_addsl" + [(set (match_operand:X 0 "register_operand" "=r") + (plus:X (ashift:X (match_operand:X 1 "register_operand" "r") + (match_operand:QI 2 "immediate_operand" "I")) + (match_operand:X 3 "register_operand" "r")))] + "TARGET_XTHEADBA + && (INTVAL (operands[2]) >= 0) && (INTVAL (operands[2]) <= 3)" + "th.addsl\t%0,%1,%3,%2" + [(set_attr "type" "bitmanip") + (set_attr "mode" "")]) + +(define_insn "*th_tst" + [(set (match_operand:X 0 "register_operand" "=r") + (zero_extract:X (match_operand:X 1 "register_operand" "r") + (const_int 1) + (match_operand 2 "immediate_operand" "i")))] + "TARGET_XTHEADBS" + "th.tst\t%0,%1,%2" + [(set_attr "type" "bitmanip")]) diff --git a/gcc/testsuite/gcc.target/riscv/xtheadba-addsl-64.c b/gcc/testsuite/gcc.target/riscv/xtheadba-addsl-64.c new file mode 100644 index 00000000000..7f47929967a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/xtheadba-addsl-64.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_xtheadba -mabi=lp64" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +/* RV64 only. */ +int foos(short *x, int n){ + return x[n]; +} +int fooi(int *x, int n){ + return x[n]; +} +int fooll(long long *x, int n){ + return x[n]; +} + +/* { dg-final { scan-assembler-times "th.addsl\[ \t\]*a\[0-9\]+,a\[0-9\]+,a\[0-9\]+,1" 1 } } */ +/* { dg-final { scan-assembler-times "th.addsl\[ \t\]*a\[0-9\]+,a\[0-9\]+,a\[0-9\]+,2" 1 } } */ +/* { dg-final { scan-assembler-times "th.addsl\[ \t\]*a\[0-9\]+,a\[0-9\]+,a\[0-9\]+,3" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/xtheadba-addsl.c b/gcc/testsuite/gcc.target/riscv/xtheadba-addsl.c new file mode 100644 index 00000000000..d739f715430 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/xtheadba-addsl.c @@ -0,0 +1,20 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_xtheadba -mabi=lp64" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +long test_1(long a, long b) +{ + return a + (b << 1); +} +long test_2(long a, long b) +{ + return a + (b << 2); +} +long test_3(long a, long b) +{ + return a + (b << 3); +} + +/* { dg-final { scan-assembler-times "th.addsl\[ \t\]*a\[0-9\]+,a\[0-9\]+,a\[0-9\]+,1" 1 } } */ +/* { dg-final { scan-assembler-times "th.addsl\[ \t\]*a\[0-9\]+,a\[0-9\]+,a\[0-9\]+,2" 1 } } */ +/* { dg-final { scan-assembler-times "th.addsl\[ \t\]*a\[0-9\]+,a\[0-9\]+,a\[0-9\]+,3" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/xtheadbs-tst.c b/gcc/testsuite/gcc.target/riscv/xtheadbs-tst.c new file mode 100644 index 00000000000..f4887bde535 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/xtheadbs-tst.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_xtheadbs -mabi=lp64" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +long +foo1 (long i) +{ + return 1L & (i >> 20); +} + +/* { dg-final { scan-assembler-times "th.tst\t" 1 } } */ +/* { dg-final { scan-assembler-not "andi" } } */