diff mbox series

[1/7] riscv: Add basic XThead* vendor extension support

Message ID 20221113214636.2747737-2-christoph.muellner@vrull.eu
State Committed
Headers
Series Add XThead* support |

Commit Message

Christoph Müllner Nov. 13, 2022, 9:46 p.m. UTC 
  From: Christoph Müllner <christoph.muellner@vrull.eu>

This patch add basic support for the following XThead* ISA extensions:

* XTheadCmo, XTheadSync
* XTheadBa, XTheadBb, XTheadBs, XTheadCondMov
* XTheadMac
* XTheadFMemIdx, XTheadMemIdx

gcc/ChangeLog:

	* common/config/riscv/riscv-common.cc: Add xthead* extensions.
	* config/riscv/riscv-opts.h (MASK_XTHEADBA): New.
	(TARGET_XTHEADBA): New.
	(MASK_XTHEADBB): New.
	(TARGET_XTHEADBB): New.
	(MASK_XTHEADBS): New.
	(TARGET_XTHEADBS): New.
	(MASK_XTHEADCMO): New.
	(TARGET_XTHEADCMO): New.
	(MASK_XTHEADCONDMOV): New.
	(TARGET_XTHEADCONDMOV): New.
	(MASK_XTHEADFMEMIDX): New.
	(TARGET_XTHEADFMEMIDX): New.
	(MASK_XTHEADMAC): New.
	(TARGET_XTHEADMAC): New.
	(MASK_XTHEADMEMIDX): New.
	(TARGET_XTHEADMEMIDX): New.
	(MASK_XTHEADSYNC): New.
	(TARGET_XTHEADSYNC): New.
	* config/riscv/riscv.opt: Add riscv_xthead_subext.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/xtheadba.c: New test.
	* gcc.target/riscv/xtheadbb.c: New test.
	* gcc.target/riscv/xtheadbs.c: New test.
	* gcc.target/riscv/xtheadcmo.c: New test.
	* gcc.target/riscv/xtheadcondmov.c: New test.
	* gcc.target/riscv/xtheadfmemidx.c: New test.
	* gcc.target/riscv/xtheadmac.c: New test.
	* gcc.target/riscv/xtheadmemidx.c: New test.
	* gcc.target/riscv/xtheadsync.c: New test.

Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
---
 gcc/common/config/riscv/riscv-common.cc       | 20 +++++++++++++++++++
 gcc/config/riscv/riscv-opts.h                 | 19 ++++++++++++++++++
 gcc/config/riscv/riscv.opt                    |  3 +++
 gcc/testsuite/gcc.target/riscv/xtheadba.c     | 13 ++++++++++++
 gcc/testsuite/gcc.target/riscv/xtheadbb.c     | 13 ++++++++++++
 gcc/testsuite/gcc.target/riscv/xtheadbs.c     | 13 ++++++++++++
 gcc/testsuite/gcc.target/riscv/xtheadcmo.c    | 13 ++++++++++++
 .../gcc.target/riscv/xtheadcondmov.c          | 13 ++++++++++++
 .../gcc.target/riscv/xtheadfmemidx.c          | 13 ++++++++++++
 gcc/testsuite/gcc.target/riscv/xtheadmac.c    | 13 ++++++++++++
 gcc/testsuite/gcc.target/riscv/xtheadmemidx.c | 13 ++++++++++++
 gcc/testsuite/gcc.target/riscv/xtheadsync.c   | 13 ++++++++++++
 12 files changed, 159 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadba.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadbb.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadbs.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadcmo.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadcondmov.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadfmemidx.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadmac.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadmemidx.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadsync.c
diff mbox series

Patch

diff --git a/gcc/common/config/riscv/riscv-common.cc b/gcc/common/config/riscv/riscv-common.cc
index 4b7f777c103..8e1449d3543 100644
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -222,6 +222,16 @@  static const struct riscv_ext_version riscv_ext_version_table[] =
   {"svinval", ISA_SPEC_CLASS_NONE, 1, 0},
   {"svnapot", ISA_SPEC_CLASS_NONE, 1, 0},
 
+  {"xtheadba", ISA_SPEC_CLASS_NONE, 1, 0},
+  {"xtheadbb", ISA_SPEC_CLASS_NONE, 1, 0},
+  {"xtheadbs", ISA_SPEC_CLASS_NONE, 1, 0},
+  {"xtheadcmo", ISA_SPEC_CLASS_NONE, 1, 0},
+  {"xtheadcondmov", ISA_SPEC_CLASS_NONE, 1, 0},
+  {"xtheadfmemidx", ISA_SPEC_CLASS_NONE, 1, 0},
+  {"xtheadmac", ISA_SPEC_CLASS_NONE, 1, 0},
+  {"xtheadmemidx", ISA_SPEC_CLASS_NONE, 1, 0},
+  {"xtheadsync", ISA_SPEC_CLASS_NONE, 1, 0},
+
   /* Terminate the list.  */
   {NULL, ISA_SPEC_CLASS_NONE, 0, 0}
 };
@@ -1247,6 +1257,16 @@  static const riscv_ext_flag_table_t riscv_ext_flag_table[] =
   {"svinval", &gcc_options::x_riscv_sv_subext, MASK_SVINVAL},
   {"svnapot", &gcc_options::x_riscv_sv_subext, MASK_SVNAPOT},
 
+  {"xtheadba",      &gcc_options::x_riscv_xthead_subext, MASK_XTHEADBA},
+  {"xtheadbb",      &gcc_options::x_riscv_xthead_subext, MASK_XTHEADBB},
+  {"xtheadbs",      &gcc_options::x_riscv_xthead_subext, MASK_XTHEADBS},
+  {"xtheadcmo",     &gcc_options::x_riscv_xthead_subext, MASK_XTHEADCMO},
+  {"xtheadcondmov", &gcc_options::x_riscv_xthead_subext, MASK_XTHEADCONDMOV},
+  {"xtheadfmemidx", &gcc_options::x_riscv_xthead_subext, MASK_XTHEADFMEMIDX},
+  {"xtheadmac",     &gcc_options::x_riscv_xthead_subext, MASK_XTHEADMAC},
+  {"xtheadmemidx",  &gcc_options::x_riscv_xthead_subext, MASK_XTHEADMEMIDX},
+  {"xtheadsync",    &gcc_options::x_riscv_xthead_subext, MASK_XTHEADSYNC},
+
   {NULL, NULL, 0}
 };
 
diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h
index 25fd85b09b1..18daac40dbd 100644
--- a/gcc/config/riscv/riscv-opts.h
+++ b/gcc/config/riscv/riscv-opts.h
@@ -189,4 +189,23 @@  enum stack_protector_guard {
    ? 0 \
    : 32 << (__builtin_popcount (riscv_zvl_flags) - 1))
 
+#define MASK_XTHEADBA		(1 << 0)
+#define TARGET_XTHEADBA		((riscv_xthead_subext & MASK_XTHEADBA) != 0)
+#define MASK_XTHEADBB		(1 << 1)
+#define TARGET_XTHEADBB		((riscv_xthead_subext & MASK_XTHEADBB) != 0)
+#define MASK_XTHEADBS		(1 << 2)
+#define TARGET_XTHEADBS		((riscv_xthead_subext & MASK_XTHEADBS) != 0)
+#define MASK_XTHEADCMO		(1 << 3)
+#define TARGET_XTHEADCMO	((riscv_xthead_subext & MASK_XTHEADCMO) != 0)
+#define MASK_XTHEADCONDMOV	(1 << 4)
+#define TARGET_XTHEADCONDMOV	((riscv_xthead_subext & MASK_XTHEADCONDMOV) != 0)
+#define MASK_XTHEADFMEMIDX	(1 << 5)
+#define TARGET_XTHEADFMEMIDX	((riscv_xthead_subext & MASK_XTHEADFMEMIDX) != 0)
+#define MASK_XTHEADMAC		(1 << 6)
+#define TARGET_XTHEADMAC	((riscv_xthead_subext & MASK_XTHEADMAC) != 0)
+#define MASK_XTHEADMEMIDX	(1 << 7)
+#define TARGET_XTHEADMEMIDX	((riscv_xthead_subext & MASK_XTHEADMEMIDX) != 0)
+#define MASK_XTHEADSYNC		(1 << 8)
+#define TARGET_XTHEADSYNC	((riscv_xthead_subext & MASK_XTHEADSYNC) != 0)
+
 #endif /* ! GCC_RISCV_OPTS_H */
diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt
index 7c3ca48d1cc..3f2dd24d59b 100644
--- a/gcc/config/riscv/riscv.opt
+++ b/gcc/config/riscv/riscv.opt
@@ -233,6 +233,9 @@  int riscv_zm_subext
 TargetVariable
 int riscv_sv_subext
 
+TargetVariable
+int riscv_xthead_subext
+
 Enum
 Name(isa_spec_class) Type(enum riscv_isa_spec_class)
 Supported ISA specs (for use with the -misa-spec= option):
diff --git a/gcc/testsuite/gcc.target/riscv/xtheadba.c b/gcc/testsuite/gcc.target/riscv/xtheadba.c
new file mode 100644
index 00000000000..c91b95b94a8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/xtheadba.c
@@ -0,0 +1,13 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc_xtheadba" { target { rv64 } } } */
+
+#ifndef __riscv_xtheadba
+#error Feature macro not defined
+#endif
+
+int
+foo (int a)
+{
+  return a;
+}
+
diff --git a/gcc/testsuite/gcc.target/riscv/xtheadbb.c b/gcc/testsuite/gcc.target/riscv/xtheadbb.c
new file mode 100644
index 00000000000..4872faa999d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/xtheadbb.c
@@ -0,0 +1,13 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc_xtheadbb" { target { rv64 } } } */
+
+#ifndef __riscv_xtheadbb
+#error Feature macro not defined
+#endif
+
+int
+foo (int a)
+{
+  return a;
+}
+
diff --git a/gcc/testsuite/gcc.target/riscv/xtheadbs.c b/gcc/testsuite/gcc.target/riscv/xtheadbs.c
new file mode 100644
index 00000000000..9350505ebb1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/xtheadbs.c
@@ -0,0 +1,13 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc_xtheadbs" { target { rv64 } } } */
+
+#ifndef __riscv_xtheadbs
+#error Feature macro not defined
+#endif
+
+int
+foo (int a)
+{
+  return a;
+}
+
diff --git a/gcc/testsuite/gcc.target/riscv/xtheadcmo.c b/gcc/testsuite/gcc.target/riscv/xtheadcmo.c
new file mode 100644
index 00000000000..ce56f9a1277
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/xtheadcmo.c
@@ -0,0 +1,13 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc_xtheadcmo" { target { rv64 } } } */
+
+#ifndef __riscv_xtheadcmo
+#error Feature macro not defined
+#endif
+
+int
+foo (int a)
+{
+  return a;
+}
+
diff --git a/gcc/testsuite/gcc.target/riscv/xtheadcondmov.c b/gcc/testsuite/gcc.target/riscv/xtheadcondmov.c
new file mode 100644
index 00000000000..9324b30f6bd
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/xtheadcondmov.c
@@ -0,0 +1,13 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc_xtheadcondmov" { target { rv64 } } } */
+
+#ifndef __riscv_xtheadcondmov
+#error Feature macro not defined
+#endif
+
+int
+foo (int a)
+{
+  return a;
+}
+
diff --git a/gcc/testsuite/gcc.target/riscv/xtheadfmemidx.c b/gcc/testsuite/gcc.target/riscv/xtheadfmemidx.c
new file mode 100644
index 00000000000..9e69ee45cad
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/xtheadfmemidx.c
@@ -0,0 +1,13 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc_xtheadfmemidx" { target { rv64 } } } */
+
+#ifndef __riscv_xtheadfmemidx
+#error Feature macro not defined
+#endif
+
+int
+foo (int a)
+{
+  return a;
+}
+
diff --git a/gcc/testsuite/gcc.target/riscv/xtheadmac.c b/gcc/testsuite/gcc.target/riscv/xtheadmac.c
new file mode 100644
index 00000000000..d8f356bbdec
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/xtheadmac.c
@@ -0,0 +1,13 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc_xtheadmac" { target { rv64 } } } */
+
+#ifndef __riscv_xtheadmac
+#error Feature macro not defined
+#endif
+
+int
+foo (int a)
+{
+  return a;
+}
+
diff --git a/gcc/testsuite/gcc.target/riscv/xtheadmemidx.c b/gcc/testsuite/gcc.target/riscv/xtheadmemidx.c
new file mode 100644
index 00000000000..bd1545c0c24
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/xtheadmemidx.c
@@ -0,0 +1,13 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc_xtheadmemidx" { target { rv64 } } } */
+
+#ifndef __riscv_xtheadmemidx
+#error Feature macro not defined
+#endif
+
+int
+foo (int a)
+{
+  return a;
+}
+
diff --git a/gcc/testsuite/gcc.target/riscv/xtheadsync.c b/gcc/testsuite/gcc.target/riscv/xtheadsync.c
new file mode 100644
index 00000000000..e51457e5376
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/xtheadsync.c
@@ -0,0 +1,13 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc_xtheadsync" { target { rv64 } } } */
+
+#ifndef __riscv_xtheadsync
+#error Feature macro not defined
+#endif
+
+int
+foo (int a)
+{
+  return a;
+}
+