From patchwork Mon Oct 31 15:45:00 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Engel X-Patchwork-Id: 59665 X-Patchwork-Delegate: rearnsha@gcc.gnu.org Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id EDE9A38460AB for ; Mon, 31 Oct 2022 15:47:57 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from wout3-smtp.messagingengine.com (wout3-smtp.messagingengine.com [64.147.123.19]) by sourceware.org (Postfix) with ESMTPS id BDCA53853570 for ; Mon, 31 Oct 2022 15:46:29 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org BDCA53853570 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=danielengel.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=danielengel.com Received: from compute5.internal (compute5.nyi.internal [10.202.2.45]) by mailout.west.internal (Postfix) with ESMTP id A513032008FE; Mon, 31 Oct 2022 11:46:28 -0400 (EDT) Received: from mailfrontend2 ([10.202.2.163]) by compute5.internal (MEProxy); Mon, 31 Oct 2022 11:46:28 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=danielengel.com; h=cc:cc:content-transfer-encoding:date:date:from:from :in-reply-to:in-reply-to:message-id:mime-version:references :reply-to:sender:subject:subject:to:to; s=fm1; t=1667231188; x= 1667317588; bh=bizKXgz+Av2KRD555WC7aw8ta7XIGtFIpQMxI1WEAC4=; b=I NHrbvZs2NVc373Ua1xkKcREuMt1YMTuRhyALP0lMABBBUfCyQse3i3drppwtC53I X58rY/uAOKBUiLtOiEmbF9RxR4dz+pugKjalP445PTYBOcwNOBiGbihDlZIQ5wy6 EFATQShvHib58p+bO8cu3pnV4P03w2VQhL+DjqB+xItualtG6bknQRqzB2wx1dLu 8fxeCTAFPogEHKWQi9Ubl5eY1lNcF3XOeEkeLyL+hbHNnM/OFwj2J2SrIrYx58uf 1Se1+Z25MBeJRNrhFSz87mc6Aj6xHlbKZBvU2tfc0jIV9g2J/JnwdCserWLsIhQP JdwpkyMd9XmicxvSo3pCA== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:cc:content-transfer-encoding:date:date :feedback-id:feedback-id:from:from:in-reply-to:in-reply-to :message-id:mime-version:references:reply-to:sender:subject :subject:to:to:x-me-proxy:x-me-proxy:x-me-sender:x-me-sender :x-sasl-enc; s=fm3; t=1667231188; x=1667317588; bh=bizKXgz+Av2KR D555WC7aw8ta7XIGtFIpQMxI1WEAC4=; b=KDg2/Y2UwRZyiJ8GGdQstvAujd+HR o64rvF8tjuFlWmU/scuvRO4zF7HF9aN9LDydtAyCYjt9sQ0vqRx+lVL28JGvZelV WczzsVcIFU1ilQgGYGuIDuR+CG5fEO/Eg4pWqgMmoQDlAkqD0RKv71vTtPEtGOqH 0TJabAVkHNWQyolnvPiHBo6QSqKXkcpzgvlgRfwSxkaSVCx/fO0d9Bjn5Ia8p9ce aRfM9Hvmdfq2jxmgnuQK/fMcQPvykA9AmmJapgx7owQyDfsuoutjQGA8FivCjqAe IKhlhXvtZbaudSvmJ1YQsxf1zoHOv50Vn6avoQOu9GiKRBGhH98uhGncQ== X-ME-Sender: X-ME-Received: X-ME-Proxy-Cause: gggruggvucftvghtrhhoucdtuddrgedvgedrudefgdejlecutefuodetggdotefrodftvf curfhrohhfihhlvgemucfhrghsthforghilhdpqfgfvfdpuffrtefokffrpgfnqfghnecu uegrihhlohhuthemuceftddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmdenuc fjughrpefhvfevufffkffojghfggfgsedtkeertdertddtnecuhfhrohhmpeffrghnihgv lhcugfhnghgvlhcuoehgnhhusegurghnihgvlhgvnhhgvghlrdgtohhmqeenucggtffrrg htthgvrhhnpeeuieekgfegkeekleffkefhleevgfekkeekheeffeevkeehvdduvdfgvdeg heeuhfenucffohhmrghinheplhhisgdufhhunhgtshdrshgsnecuvehluhhsthgvrhfuih iivgepvdenucfrrghrrghmpehmrghilhhfrhhomhepghhnuhesuggrnhhivghlvghnghgv lhdrtghomh X-ME-Proxy: Feedback-ID: i791144d6:Fastmail Received: by mail.messagingengine.com (Postfix) with ESMTPA; Mon, 31 Oct 2022 11:46:27 -0400 (EDT) Received: from ubuntu.lorien.danielengel.com (ubuntu.lorien.danielengel.com [10.0.0.96]) by sendmail.lorien.danielengel.com (8.15.2/8.15.2) with ESMTP id 29VFkJqe087244; Mon, 31 Oct 2022 08:46:19 -0700 (PDT) (envelope-from gnu@danielengel.com) From: Daniel Engel To: Richard Earnshaw , gcc-patches@gcc.gnu.org Subject: [PATCH v7 05/34] Add the __HAVE_FEATURE_IT and IT() macros Date: Mon, 31 Oct 2022 08:45:00 -0700 Message-Id: <20221031154529.3627576-6-gnu@danielengel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221031154529.3627576-1-gnu@danielengel.com> References: <20221031154529.3627576-1-gnu@danielengel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-13.3 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, JMQ_SPF_NEUTRAL, RCVD_IN_DNSWL_LOW, SPF_HELO_PASS, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Daniel Engel , Christophe Lyon Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" These macros complement and extend the existing do_it() macro. Together, they streamline the process of optimizing short branchless contitional sequences to support ARM, Thumb-2, and Thumb-1. The inherent architecture limitations of Thumb-1 means that writing assembly code is somewhat more tedious. And, while such code will run unmodified in an ARM or Thumb-2 enfironment, it will lack one of the key performance optimizations available there. Initially, the first idea might be to split the an instruction sequence with #ifdef(s): one path for Thumb-1 and the other for ARM/Thumb-2. This could suffice if conditional execution optimizations were rare. However, #ifdef(s) break flow of an algorithm and shift focus to the architectural differences instead of the similarities. On functions with a high percentage of conditional execution, it starts to become attractive to split everything into distinct architecture-specific function objects -- even when the underlying algorithm is identical. Additionally, duplicated code and comments (whether an individual operand, a line, or a larger block) become a future maintenance liability if the two versions aren't kept in sync. See code comments for limitations and expecated usage. gcc/libgcc/ChangeLog: 2022-10-09 Daniel Engel (__HAVE_FEATURE_IT, IT): New macros. --- libgcc/config/arm/lib1funcs.S | 68 +++++++++++++++++++++++++++++++++++ 1 file changed, 68 insertions(+) diff --git a/libgcc/config/arm/lib1funcs.S b/libgcc/config/arm/lib1funcs.S index f2f82f9d509..7a941ee9fc8 100644 --- a/libgcc/config/arm/lib1funcs.S +++ b/libgcc/config/arm/lib1funcs.S @@ -230,6 +230,7 @@ LSYM(Lend_fde): ARM and Thumb-2. However this is only supported by recent gas, so define a set of macros to allow ARM code on older assemblers. */ #if defined(__thumb2__) +#define __HAVE_FEATURE_IT .macro do_it cond, suffix="" it\suffix \cond .endm @@ -245,6 +246,9 @@ LSYM(Lend_fde): \name \dest, \src1, \tmp .endm #else +#if !defined(__thumb__) +#define __HAVE_FEATURE_IT +#endif .macro do_it cond, suffix="" .endm .macro shift1 op, arg0, arg1, arg2 @@ -259,6 +263,70 @@ LSYM(Lend_fde): #define COND(op1, op2, cond) op1 ## op2 ## cond + +/* The IT() macro streamlines the construction of short branchless contitional + sequences that support ARM, Thumb-2, and Thumb-1. It is intended as an + extension to the .do_it macro defined above. Code not written with the + intent to support Thumb-1 need not use IT(). + + IT()'s main advantage is the minimization of syntax differences. Unified + functions can support Thumb-1 without imposiing an undue performance + penalty on ARM and Thumb-2. Writing code without duplicate instructions + and operands keeps the high level function flow clearer and should reduce + the incidence of maintenance bugs. + + Where conditional execution is supported by ARM and Thumb-2, the specified + instruction compiles with the conditional suffix 'c'. + + Where Thumb-1 and v6m do not support IT, the given instruction compiles + with the standard unified syntax suffix "s", and a preceding branch + instruction is required to implement conditional behavior. + + (Aside: The Thumb-1 "s"-suffix pattern is somewhat simplistic, since it + does not support 'cmp' or 'tst' with a non-"s" suffix. It also appends + "s" to 'mov' and 'add' with high register operands which are otherwise + legal on v6m. Use of IT() will result in a compiler error for all of + these exceptional cases, and a full #ifdef code split will be required. + However, it is unlikely that code written with Thumb-1 compatibility + in mind will use such patterns, so IT() still promises a good value.) + + Typical if/then/else usage is: + + #ifdef __HAVE_FEATURE_IT + // ARM and Thumb-2 'true' condition. + do_it c, tee + #else + // Thumb-1 'false' condition. This must be opposite the + // sense of the ARM and Thumb-2 condition, since the + // branch is taken to skip the 'true' instruction block. + b!c else_label + #endif + + // Conditional 'true' execution for all compile modes. + IT(ins1,c) op1, op2 + IT(ins2,c) op1, op2 + + #ifndef __HAVE_FEATURE_IT + // Thumb-1 branch to skip the 'else' instruction block. + // Omitted for if/then usage. + b end_label + #endif + + else_label: + // Conditional 'false' execution for all compile modes. + // Omitted for if/then usage. + IT(ins3,!c) op1, op2 + IT(ins4,!c) op1, op2 + + end_label: + // Unconditional execution resumes here. + */ +#ifdef __HAVE_FEATURE_IT + #define IT(ins,c) ins##c +#else + #define IT(ins,c) ins##s +#endif + #ifdef __ARM_EABI__ .macro ARM_LDIV0 name signed cmp r0, #0