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Mon, 31 Oct 2022 11:46:22 -0400 (EDT) Received: from ubuntu.lorien.danielengel.com (ubuntu.lorien.danielengel.com [10.0.0.96]) by sendmail.lorien.danielengel.com (8.15.2/8.15.2) with ESMTP id 29VFkEZh087241; Mon, 31 Oct 2022 08:46:14 -0700 (PDT) (envelope-from gnu@danielengel.com) From: Daniel Engel To: Richard Earnshaw , gcc-patches@gcc.gnu.org Subject: [PATCH v7 04/34] Reorganize LIB1ASMFUNCS object wrapper macros Date: Mon, 31 Oct 2022 08:44:59 -0700 Message-Id: <20221031154529.3627576-5-gnu@danielengel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221031154529.3627576-1-gnu@danielengel.com> References: <20221031154529.3627576-1-gnu@danielengel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-13.3 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, JMQ_SPF_NEUTRAL, RCVD_IN_DNSWL_LOW, SPF_HELO_PASS, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Daniel Engel , Christophe Lyon Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" This will make it easier to isolate changes in subsequent patches. gcc/libgcc/ChangeLog: 2022-10-09 Daniel Engel * config/arm/t-elf (LIB1ASMFUNCS): Split macros into logical groups. --- libgcc/config/arm/t-elf | 66 +++++++++++++++++++++++++++++++++-------- 1 file changed, 53 insertions(+), 13 deletions(-) diff --git a/libgcc/config/arm/t-elf b/libgcc/config/arm/t-elf index 9da6cd37054..93ea1cd8f76 100644 --- a/libgcc/config/arm/t-elf +++ b/libgcc/config/arm/t-elf @@ -14,19 +14,59 @@ LIB1ASMFUNCS += _arm_muldf3 _arm_mulsf3 endif endif # !__symbian__ -# For most CPUs we have an assembly soft-float implementations. -# However this is not true for ARMv6M. Here we want to use the soft-fp C -# implementation. The soft-fp code is only build for ARMv6M. This pulls -# in the asm implementation for other CPUs. -LIB1ASMFUNCS += _udivsi3 _divsi3 _umodsi3 _modsi3 _dvmd_tls _bb_init_func \ - _call_via_rX _interwork_call_via_rX \ - _lshrdi3 _ashrdi3 _ashldi3 \ - _arm_negdf2 _arm_addsubdf3 _arm_muldivdf3 _arm_cmpdf2 _arm_unorddf2 \ - _arm_fixdfsi _arm_fixunsdfsi \ - _arm_truncdfsf2 _arm_negsf2 _arm_addsubsf3 _arm_muldivsf3 \ - _arm_cmpsf2 _arm_unordsf2 _arm_fixsfsi _arm_fixunssfsi \ - _arm_floatdidf _arm_floatdisf _arm_floatundidf _arm_floatundisf \ - _clzsi2 _clzdi2 _ctzsi2 +# This pulls in the available assembly function implementations. +# The soft-fp code is only built for ARMv6M, since there is no +# assembly implementation here for double-precision values. + + +# Group 1: Integer function objects. +LIB1ASMFUNCS += \ + _ashldi3 \ + _ashrdi3 \ + _lshrdi3 \ + _clzdi2 \ + _clzsi2 \ + _ctzsi2 \ + _dvmd_tls \ + _divsi3 \ + _modsi3 \ + _udivsi3 \ + _umodsi3 \ + + +# Group 2: Single precision floating point function objects. +LIB1ASMFUNCS += \ + _arm_addsubsf3 \ + _arm_cmpsf2 \ + _arm_fixsfsi \ + _arm_fixunssfsi \ + _arm_floatdisf \ + _arm_floatundisf \ + _arm_muldivsf3 \ + _arm_negsf2 \ + _arm_unordsf2 \ + + +# Group 3: Double precision floating point function objects. +LIB1ASMFUNCS += \ + _arm_addsubdf3 \ + _arm_cmpdf2 \ + _arm_fixdfsi \ + _arm_fixunsdfsi \ + _arm_floatdidf \ + _arm_floatundidf \ + _arm_muldivdf3 \ + _arm_negdf2 \ + _arm_truncdfsf2 \ + _arm_unorddf2 \ + + +# Group 4: Miscellaneous function objects. +LIB1ASMFUNCS += \ + _bb_init_func \ + _call_via_rX \ + _interwork_call_via_rX \ + # Currently there is a bug somewhere in GCC's alias analysis # or scheduling code that is breaking _fpmul_parts in fp-bit.c.