From patchwork Thu Oct 27 18:11:25 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?q?Christoph_M=C3=BCllner?= X-Patchwork-Id: 59557 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 00120383FBBF for ; Thu, 27 Oct 2022 18:11:49 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mail-ej1-x636.google.com (mail-ej1-x636.google.com [IPv6:2a00:1450:4864:20::636]) by sourceware.org (Postfix) with ESMTPS id 289453846421 for ; Thu, 27 Oct 2022 18:11:31 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 289453846421 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=vrull.eu Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=vrull.eu Received: by mail-ej1-x636.google.com with SMTP id k2so7019197ejr.2 for ; Thu, 27 Oct 2022 11:11:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vrull.eu; s=google; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:from:to:cc:subject:date:message-id:reply-to; bh=iz4y7JoqxApTa0MYjBlooZQFAzlgbuoop2iP7njo5YU=; b=F+e3MVH49f3C4/gNBAzCwjtXzw/XIXmq7cNihNHSJ2HdtNsHXNoEWH2fqXN5Su69Wa a6u7UafdTj0kp8d/4XvkDyOg4tm4dNkGDvw65UxKGqG6vQeLwKOAsanJiQIfPHjq6uIg Q59HDjzZcDKQbq4Q6CFTvHGXLr9LXtd6Qh/Wg6XWeYw/fcbxLRDLqnXylyEn2Lrt5xD/ hwISLADmnnK8vtOII7XS5g6Q3Jg30IJY55KrZB9qpJ/jTT7SNfjX3/0vTGs0ZhTHIR8c a0TvvurdYL1QWwUGF9Q748Ge0gjnagtPRtVot+teEZXMCAcUlZA8TL83t1PKqYaXSBYQ /+Jg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=iz4y7JoqxApTa0MYjBlooZQFAzlgbuoop2iP7njo5YU=; b=rSiOrGi+xzRrQZHDCT4a90tneGSi8Ppp0LH1GpZB8YxFHLS0QghE+aD73VlG+jCNyo ZL/+yr8dwvPRdf1IR+C30QQsEJaKGtNdYRt/kZmxc/tVv5BCxK/oIYfoZkhvr14lWpMT hBwMEXnKRidU8Cr1P6iJdQp4Ad1JXyO6yYR0MPGNN7wmmI7I1MJDx1mZYkqrIP5ix8w9 WnUIOdg7TlzdfLEOsTszuixn1MXDse0bpk8sZYm5xFQDfZ6EDaOAvGm8RqE8VJQOzoll 3O+oo+oBlsc3a9NftPKIqdWWEf9HknFaQEZARygpdsByYL3N3bD+Le8O5dehiwYFppMr xotQ== X-Gm-Message-State: ACrzQf0RjgoXIY3FJWRkcVu1G6Mo4ydk3ygsHbRiNIZlZ+lH4MguEO6w Y975BnITO+WcP97m32lZTa9wvSumW/a01mx3 X-Google-Smtp-Source: AMsMyM4ps+ZuxKq7kO5jh9X3lWHn7foTDjabqUzrUDaaSu1HQcY6Q96gKDJXcvUWalugSSxEP2/NIg== X-Received: by 2002:a17:906:db0c:b0:77b:7d7d:5805 with SMTP id xj12-20020a170906db0c00b0077b7d7d5805mr44828965ejb.726.1666894289013; Thu, 27 Oct 2022 11:11:29 -0700 (PDT) Received: from beast.fritz.box (62-178-148-172.cable.dynamic.surfer.at. [62.178.148.172]) by smtp.gmail.com with ESMTPSA id o11-20020a170906768b00b0077d6f628e14sm1113408ejm.83.2022.10.27.11.11.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 27 Oct 2022 11:11:28 -0700 (PDT) From: Christoph Muellner To: gcc-patches@gcc.gnu.org, Kito Cheng , Jim Wilson , Palmer Dabbelt , Andrew Waterman , Philipp Tomsich , Jeff Law , Aaron Durbin , Vineet Gupta Subject: [PATCH] RISC-V: Add Zawrs ISA extension support Date: Thu, 27 Oct 2022 20:11:25 +0200 Message-Id: <20221027181125.1658982-1-christoph.muellner@vrull.eu> X-Mailer: git-send-email 2.37.3 MIME-Version: 1.0 X-Spam-Status: No, score=-12.5 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, JMQ_SPF_NEUTRAL, KAM_MANYTO, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" From: Christoph Muellner This patch adds support for the Zawrs ISA extension. The patch depends on the corresponding Binutils patch to be usable (see [1]) The specification can be found here: https://github.com/riscv/riscv-zawrs/blob/main/zawrs.adoc Note, that the Zawrs extension is not frozen or ratified yet. Therefore this patch is an RFC and not intended to get merged. [1] https://sourceware.org/pipermail/binutils/2022-April/120559.html gcc/ChangeLog: * common/config/riscv/riscv-common.cc: Add zawrs extension. * config/riscv/riscv-opts.h (MASK_ZAWRS): New. (TARGET_ZAWRS): New. * config/riscv/riscv.opt: New. gcc/testsuite/ChangeLog: * gcc.target/riscv/zawrs.c: New test. Signed-off-by: Christoph Muellner --- gcc/common/config/riscv/riscv-common.cc | 4 ++++ gcc/config/riscv/riscv-opts.h | 3 +++ gcc/config/riscv/riscv.opt | 3 +++ gcc/testsuite/gcc.target/riscv/zawrs.c | 13 +++++++++++++ 4 files changed, 23 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/zawrs.c diff --git a/gcc/common/config/riscv/riscv-common.cc b/gcc/common/config/riscv/riscv-common.cc index d6404a01205..4b7f777c103 100644 --- a/gcc/common/config/riscv/riscv-common.cc +++ b/gcc/common/config/riscv/riscv-common.cc @@ -163,6 +163,8 @@ static const struct riscv_ext_version riscv_ext_version_table[] = {"zifencei", ISA_SPEC_CLASS_20191213, 2, 0}, {"zifencei", ISA_SPEC_CLASS_20190608, 2, 0}, + {"zawrs", ISA_SPEC_CLASS_NONE, 1, 0}, + {"zba", ISA_SPEC_CLASS_NONE, 1, 0}, {"zbb", ISA_SPEC_CLASS_NONE, 1, 0}, {"zbc", ISA_SPEC_CLASS_NONE, 1, 0}, @@ -1180,6 +1182,8 @@ static const riscv_ext_flag_table_t riscv_ext_flag_table[] = {"zicsr", &gcc_options::x_riscv_zi_subext, MASK_ZICSR}, {"zifencei", &gcc_options::x_riscv_zi_subext, MASK_ZIFENCEI}, + {"zawrs", &gcc_options::x_riscv_za_subext, MASK_ZAWRS}, + {"zba", &gcc_options::x_riscv_zb_subext, MASK_ZBA}, {"zbb", &gcc_options::x_riscv_zb_subext, MASK_ZBB}, {"zbc", &gcc_options::x_riscv_zb_subext, MASK_ZBC}, diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h index 1dfe8c89209..25fd85b09b1 100644 --- a/gcc/config/riscv/riscv-opts.h +++ b/gcc/config/riscv/riscv-opts.h @@ -73,6 +73,9 @@ enum stack_protector_guard { #define TARGET_ZICSR ((riscv_zi_subext & MASK_ZICSR) != 0) #define TARGET_ZIFENCEI ((riscv_zi_subext & MASK_ZIFENCEI) != 0) +#define MASK_ZAWRS (1 << 0) +#define TARGET_ZAWRS ((riscv_za_subext & MASK_ZAWRS) != 0) + #define MASK_ZBA (1 << 0) #define MASK_ZBB (1 << 1) #define MASK_ZBC (1 << 2) diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt index 426ea95cd14..7c3ca48d1cc 100644 --- a/gcc/config/riscv/riscv.opt +++ b/gcc/config/riscv/riscv.opt @@ -203,6 +203,9 @@ long riscv_stack_protector_guard_offset = 0 TargetVariable int riscv_zi_subext +TargetVariable +int riscv_za_subext + TargetVariable int riscv_zb_subext diff --git a/gcc/testsuite/gcc.target/riscv/zawrs.c b/gcc/testsuite/gcc.target/riscv/zawrs.c new file mode 100644 index 00000000000..0b7e2662343 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/zawrs.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zawrs" { target { rv64 } } } */ +/* { dg-options "-march=rv32gc_zawrs" { target { rv32 } } } */ + +#ifndef __riscv_zawrs +#error Feature macro not defined +#endif + +int +foo (int a) +{ + return a; +}