From patchwork Tue Oct 18 23:23:01 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: liuhongt X-Patchwork-Id: 59028 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id D90D0385841A for ; Tue, 18 Oct 2022 23:25:33 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org D90D0385841A DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1666135533; bh=ccxJpE+Fuyjr7Lhu2GXiOHMGNuDjeFU/Odk3hR3irLs=; h=To:Subject:Date:List-Id:List-Unsubscribe:List-Archive:List-Post: List-Help:List-Subscribe:From:Reply-To:From; b=uLne5R+med/oTR45NlhoZIYSspY+VNS32+jTtCayO3JrhOS9rqGUU5gJDWnxKDo9H jbT+cjjWKSfmrOfDSD6FwlvCzHz18JK3mH8oX3ah6PGZJDZNqaH3TyHquWRMweUnLv uqdSpkuJQ9hrLrYvSyo0/7e1oDGdXXvgquePHh/U= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by sourceware.org (Postfix) with ESMTPS id D15B33858D32 for ; Tue, 18 Oct 2022 23:25:04 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org D15B33858D32 X-IronPort-AV: E=McAfee;i="6500,9779,10504"; a="304994096" X-IronPort-AV: E=Sophos;i="5.95,194,1661842800"; d="scan'208";a="304994096" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Oct 2022 16:25:03 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10504"; a="692064875" X-IronPort-AV: E=Sophos;i="5.95,194,1661842800"; d="scan'208";a="692064875" Received: from shvmail03.sh.intel.com ([10.239.245.20]) by fmsmga008.fm.intel.com with ESMTP; 18 Oct 2022 16:25:02 -0700 Received: from shliclel4051.sh.intel.com (shliclel4051.sh.intel.com [10.239.240.51]) by shvmail03.sh.intel.com (Postfix) with ESMTP id 65AC61007813; Wed, 19 Oct 2022 07:25:01 +0800 (CST) To: gcc-patches@gcc.gnu.org Subject: [PATCH] Canonicalize vec_perm index to make the first index come from the first vector. Date: Wed, 19 Oct 2022 07:23:01 +0800 Message-Id: <20221018232301.264776-1-hongtao.liu@intel.com> X-Mailer: git-send-email 2.27.0 MIME-Version: 1.0 X-Spam-Status: No, score=-12.3 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: liuhongt via Gcc-patches From: liuhongt Reply-To: liuhongt Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" Fix unexpected non-canon form from gimple vector selector. Bootstrapped and regtested on x86_64-pc-linux-gnu{-m32,}. Ok for trunk? gcc/ChangeLog: PR target/107271 * config/i386/i386-expand.cc (ix86_vec_perm_index_canon): New. (expand_vec_perm_shufps_shufps): Call ix86_vec_perm_index_canon gcc/testsuite/ChangeLog: * gcc.target/i386/pr107271.c: New test. --- gcc/config/i386/i386-expand.cc | 17 +++++++++++++++++ gcc/testsuite/gcc.target/i386/pr107271.c | 16 ++++++++++++++++ 2 files changed, 33 insertions(+) create mode 100644 gcc/testsuite/gcc.target/i386/pr107271.c diff --git a/gcc/config/i386/i386-expand.cc b/gcc/config/i386/i386-expand.cc index 6baff6d0e61..4f121516091 100644 --- a/gcc/config/i386/i386-expand.cc +++ b/gcc/config/i386/i386-expand.cc @@ -19604,6 +19604,22 @@ expand_vec_perm_1 (struct expand_vec_perm_d *d) return false; } +/* Canonicalize vec_perm index to make the first index + always comes from the first index. */ +static void +ix86_vec_perm_index_canon (struct expand_vec_perm_d *d) +{ + unsigned nelt = d->nelt; + if (d->perm[0] < nelt) + return; + + for (unsigned i = 0; i != nelt; i++) + d->perm[i] = (d->perm[i] + nelt) % (2 * nelt); + + std::swap (d->op0, d->op1); + return; +} + /* A subroutine of ix86_expand_vec_perm_const_1. Try to implement D in terms of a pair of shufps+ shufps/pshufd instructions. */ static bool @@ -19621,6 +19637,7 @@ expand_vec_perm_shufps_shufps (struct expand_vec_perm_d *d) if (d->testing_p) return true; + ix86_vec_perm_index_canon (d); for (i = 0; i < 4; ++i) count += d->perm[i] > 3 ? 1 : 0; diff --git a/gcc/testsuite/gcc.target/i386/pr107271.c b/gcc/testsuite/gcc.target/i386/pr107271.c new file mode 100644 index 00000000000..fe89c9a5bef --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr107271.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-options "-O0" } */ + +typedef int __attribute__((__vector_size__ (16))) V; + +static inline __attribute__((__always_inline__)) V +bar (V v128u32_0) +{ + return __builtin_shuffle ((V){}, v128u32_0, v128u32_0); +} + +V +foo (void) +{ + return bar ((V){7, 4, 4}); +}