From patchwork Tue Oct 11 08:03:16 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Liu, Hongtao" X-Patchwork-Id: 58636 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 9A715385740E for ; Tue, 11 Oct 2022 08:04:25 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 9A715385740E DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1665475465; bh=i7CfmYrq0DSiTh0A3mTQSFG/qRkGv65m6drpO63s4ik=; h=To:Subject:Date:List-Id:List-Unsubscribe:List-Archive:List-Post: List-Help:List-Subscribe:From:Reply-To:From; b=w1RnFsnO5EqrQ09m4MpYWEW6um3sPOw+nT7I2HUHb77MFPMkW6bDWhMmnklJAuQ+3 9BYaYYPNuWDH1NdB9FnLVoloU/HxA7ojH+uf2aslOo0kWOu4Cl/SbGtgx/n2b/pvtn rRrfUzuUiCWzGsoZq3V56E3uFPqtzqHmrF06bY2g= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by sourceware.org (Postfix) with ESMTPS id E83163858C2D for ; Tue, 11 Oct 2022 08:03:21 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org E83163858C2D X-IronPort-AV: E=McAfee;i="6500,9779,10496"; a="306062411" X-IronPort-AV: E=Sophos;i="5.95,175,1661842800"; d="scan'208";a="306062411" Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 Oct 2022 01:03:19 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10496"; a="730883098" X-IronPort-AV: E=Sophos;i="5.95,175,1661842800"; d="scan'208";a="730883098" Received: from shvmail03.sh.intel.com ([10.239.245.20]) by fmsmga002.fm.intel.com with ESMTP; 11 Oct 2022 01:03:17 -0700 Received: from shliclel4051.sh.intel.com (shliclel4051.sh.intel.com [10.239.240.51]) by shvmail03.sh.intel.com (Postfix) with ESMTP id 13E67100AC43; Tue, 11 Oct 2022 16:03:16 +0800 (CST) To: gcc-patches@gcc.gnu.org Subject: [PATCH] [x86] Add define_insn_and_split to support general version of "kxnor". Date: Tue, 11 Oct 2022 16:03:16 +0800 Message-Id: <20221011080316.1778261-1-hongtao.liu@intel.com> X-Mailer: git-send-email 2.27.0 MIME-Version: 1.0 X-Spam-Status: No, score=-12.2 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: liuhongt via Gcc-patches From: "Liu, Hongtao" Reply-To: liuhongt Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" For genereal_reg_operand, it will be splitted into xor + not. For mask_reg_operand, it will be splitted with UNSPEC_MASK_OP just like what we did for other logic operations. The patch will optimize xor+not to kxnor when possible. Bootstrapped and regtested on x86_64-pc-linux-gnu. Ok for trunk? gcc/ChangeLog: * config/i386/i386.md (*notxor_1): New post_reload define_insn_and_split. (*notxorqi_1): Ditto. gcc/testsuite/ChangeLog: * gcc.target/i386/pr107093.c: New test. --- gcc/config/i386/i386.md | 71 ++++++++++++++++++++++++ gcc/testsuite/gcc.target/i386/pr107093.c | 38 +++++++++++++ 2 files changed, 109 insertions(+) create mode 100644 gcc/testsuite/gcc.target/i386/pr107093.c diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md index 1be9b669909..228edba2b40 100644 --- a/gcc/config/i386/i386.md +++ b/gcc/config/i386/i386.md @@ -10826,6 +10826,39 @@ (define_insn "*_1" (set_attr "type" "alu, alu, msklog") (set_attr "mode" "")]) +(define_insn_and_split "*notxor_1" + [(set (match_operand:SWI248 0 "nonimmediate_operand" "=rm,r,?k") + (not:SWI248 + (xor:SWI248 + (match_operand:SWI248 1 "nonimmediate_operand" "%0,0,k") + (match_operand:SWI248 2 "" "r,,k")))) + (clobber (reg:CC FLAGS_REG))] + "ix86_binary_operator_ok (XOR, mode, operands)" + "#" + "&& reload_completed" + [(parallel + [(set (match_dup 0) + (xor:SWI248 (match_dup 1) (match_dup 2))) + (clobber (reg:CC FLAGS_REG))]) + (set (match_dup 0) + (not:SWI248 (match_dup 1)))] +{ + if (MASK_REGNO_P (REGNO (operands[0]))) + { + emit_insn (gen_kxnor (operands[0], operands[1], operands[2])); + DONE; + } +} + [(set (attr "isa") + (cond [(eq_attr "alternative" "2") + (if_then_else (eq_attr "mode" "SI,DI") + (const_string "avx512bw") + (const_string "avx512f")) + ] + (const_string "*"))) + (set_attr "type" "alu, alu, msklog") + (set_attr "mode" "")]) + (define_insn_and_split "*iordi_1_bts" [(set (match_operand:DI 0 "nonimmediate_operand" "=rm") (ior:DI @@ -10959,6 +10992,44 @@ (define_insn "*qi_1" (symbol_ref "!TARGET_PARTIAL_REG_STALL")] (symbol_ref "true")))]) +(define_insn_and_split "*notxorqi_1" + [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,q,r,?k") + (not:QI + (xor:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0,k") + (match_operand:QI 2 "general_operand" "qn,m,rn,k")))) + (clobber (reg:CC FLAGS_REG))] + "ix86_binary_operator_ok (XOR, QImode, operands)" + "#" + "&& reload_completed" + [(parallel + [(set (match_dup 0) + (xor:QI (match_dup 1) (match_dup 2))) + (clobber (reg:CC FLAGS_REG))]) + (set (match_dup 0) + (not:QI (match_dup 0)))] +{ + if (mask_reg_operand (operands[0], QImode)) + { + emit_insn (gen_kxnorqi (operands[0], operands[1], operands[2])); + DONE; + } +} + [(set_attr "isa" "*,*,*,avx512f") + (set_attr "type" "alu,alu,alu,msklog") + (set (attr "mode") + (cond [(eq_attr "alternative" "2") + (const_string "SI") + (and (eq_attr "alternative" "3") + (match_test "!TARGET_AVX512DQ")) + (const_string "HI") + ] + (const_string "QI"))) + ;; Potential partial reg stall on alternative 2. + (set (attr "preferred_for_speed") + (cond [(eq_attr "alternative" "2") + (symbol_ref "!TARGET_PARTIAL_REG_STALL")] + (symbol_ref "true")))]) + ;; Alternative 1 is needed to work around LRA limitation, see PR82524. (define_insn_and_split "*_1_slp" [(set (strict_low_part (match_operand:SWI12 0 "register_operand" "+,&")) diff --git a/gcc/testsuite/gcc.target/i386/pr107093.c b/gcc/testsuite/gcc.target/i386/pr107093.c new file mode 100644 index 00000000000..23e30cbac0f --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr107093.c @@ -0,0 +1,38 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx512bw -O2 -mavx512vl" } */ +/* { dg-final { scan-assembler-times {(?n)kxnor[bwqd]} 4 { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler-times {(?n)kxnor[bwdq]} 3 { target ia32 } } } */ + +#include + +__m512i +foo (__m512i a, __m512i b, __m512i c, __m512i d) +{ + __mmask32 k1 = _mm512_cmp_epi16_mask (a, b, 1); + __mmask32 k2 = _mm512_cmp_epi16_mask (c, d, 2); + return _mm512_mask_mov_epi16 (a, ~(k1 ^ k2), c); +} + +__m512i +foo1 (__m512i a, __m512i b, __m512i c, __m512i d) +{ + __mmask16 k1 = _mm512_cmp_epi32_mask (a, b, 1); + __mmask16 k2 = _mm512_cmp_epi32_mask (c, d, 2); + return _mm512_mask_mov_epi32 (a, ~(k1 ^ k2), c); +} + +__m512i +foo2 (__m512i a, __m512i b, __m512i c, __m512i d) +{ + __mmask64 k1 = _mm512_cmp_epi8_mask (a, b, 1); + __mmask64 k2 = _mm512_cmp_epi8_mask (c, d, 2); + return _mm512_mask_mov_epi8 (a, ~(k1 ^ k2), c); +} + +__m512i +foo3 (__m512i a, __m512i b, __m512i c, __m512i d) +{ + __mmask8 k1 = _mm512_cmp_epi64_mask (a, b, 1); + __mmask8 k2 = _mm512_cmp_epi64_mask (c, d, 2); + return _mm512_mask_mov_epi64 (a, ~(k1 ^ k2), c); +}